ES2365131T3 - PROCEDURE AND APPLIANCE TO DECODE LDPC CODES. - Google Patents

Abstract

An apparatus (1500, 1600, 1700) for performing message step decoding operations using LDPC graphics converted to vectors that represent high parity check matrices so that, in a high parity check matrix the zero elements of a parity check matrix H of a projected LDPC code is replaced with matrices of Z x Z zeros and elements 1 of the parity check matrix H are replaced with permutation matrices of Z x Z comprising the apparatus: a memory ( 1506) including a set of memory locations for storing L sets of Z K-bit messages, where Z is a positive integer greater than one and K and L are non-zero positive integers; a node vector processor (1508) including Z parallel node processing units, each of the node processing units (1508) to perform at least one of the restriction node processing operations and a processing operation of variable nodes; and a switching device (1520) coupled to memory (1506) and to the node vector processor (1508), the switching device (1520) for passing sets of Z messages of K bits, passing each set of Z messages of K bits in parallel between said memory and said node vector processor and to reorder the messages in at least one of said message sets in response to the switching control information, a message order module (1504) coupled to said switching device for generating said switching control information used to control the reordering of messages in said at least one set of messages, in which the message reordering module (1504) is further coupled to said memory and generates sequentially sets of indicators, each of the set identifiers controlling the memory to access the memory locations corresponding to one of said sets of messages in a single read or write operation whereby one of said sets of Z messages of K bits is written or read as a single unit accessing all Z messages of said set using a SIMD instruction.

Description

Field of the Invention

The present invention is directed to methods and apparatus for the detection and / or correction of errors in binary data, for example, through the use of parity check codes, such as low density parity check codes (LDPC ).

Background

In the modern information age, binary values, ie ones and zeros, are used to represent and communicate various types of information, for example, video, audio, statistical information, etc. Unfortunately, during the storage, transmission and / or processing of binary data, unintended errors can be introduced, for example a one can change to zero or vice versa.

Generally, in the case of data transmission, a receiver observes each of the bits received in the presence of noise or distortion and only an indication of the bit value is obtained. Under these circumstances the observed values are interpreted as a source of "software" bits. A software bit indicates a preferred estimate of the bit value, that is, a one or a zero, along with some indication of the reliability of the estimate. Although the number of errors may be relatively low, even a small number of errors or a level of distortion may result in the data becoming unusable, in the case of transmission errors, they may need to retransmit the data.

To provide a mechanism for error checking and, in some cases, to correct errors, binary data can be encoded to carefully introduce a designed redundancy. The encoding of a data unit produces what is commonly referred to as a code word. Due to its redundancy, a code word will often include more bits than the data input unit from which the code word was produced.

When signals that arise from transmitted code words are received or processed, the redundant information included in the code word as seen in the signal can be used to identify and / or correct errors in them or eliminate signal distortion received to retrieve the original data unit. Such checking and / or error correction can be implemented as part of the decoding process. In the absence of errors, or in the case of correctable errors or distortion, decoding can be used to retrieve from the source data being processed, the original data unit that was encoded. In the case of non-recoverable errors, the decoding process can produce an indication that the original data cannot be fully recovered. Such indications of decoding failure can be used to initiate the retransmission of the data.

Although data redundancy can increase the reliability of the data to be stored or transmitted, it is done at the cost of storage space and / or the use of a valuable communications bandwidth. Therefore, it is desirable to add redundancy in an efficient manner, maximizing the magnitude of the error correction / detection capability obtained for a given amount of redundancy introduced into the data.

With the increased use of fiber optic lines for data communications and the increase in the rate at which data can be read and stored on data storage devices, for example on disk devices, tapes, etc., there are an increasing need not only for effective use of storage and data transmission capacity but also for the ability to encode and decode data at high rates of speed.

Although the coding efficiency and high data rates are important, for a coding and / or decoding system to be practical to use in a wide range of devices, for example, consumer devices, it is important that the encoders and / or decoders can be implemented at a reasonable cost. Therefore, the ability to effectively implement the encoding / decoding schemes used for the purpose of correction and / or error detection in terms, for example, of hardware cost, may be important.

Over the years various types of coding schemes have been used for error correction purposes. A class of codes, generally referred to as "turbo codes" were recently invented (1993). Turbo codes offer significant benefits over older coding techniques such as convolutional codes and have found numerous applications.

In conjunction with the advent of turbo codes, there has been an increasing interest in another class of related, apparently simpler codes, commonly referred to as low density parity check codes (LDPC). The LDPC codes were actually invented by Gallager about 40 years ago (1961) but have only recently come to the forefront. The turbo codes and the LDPC codes are coding schemes that are used in the context of the so-called iterative coding systems, that is, they are decoded using iterative decoders. Recently, it has been shown that LDPC codes can provide very good error detection and correction operation, exceeding or matching that of turbo codes for long code words, for example code word sizes that exceed approximately 1000 bits, given the proper selection of LDPC coding parameters. In addition, LDPC codes can potentially be decoded at much higher speeds than turbo codes.

In many coding schemes, longer code words are often more resistant for the purposes of error detection and correction due to the interaction of the coding over a larger number of bits. Thus the use of long code words can be beneficial in terms of increasing the ability to detect and correct errors. This is particularly true for turbo codes and LDPC codes. Thus, in many applications it is desirable to use long code words, for example, code words that exceed one thousand bits in length.

The main difficulty encountered in adopting LDPC coding and Turbo coding in the context of long code words, where the use of such codes offers to be the most promising, is the complexity of implementing these coding systems. In a practical sense, complexity translates directly into cost of implementation. Both coding systems are significantly more complex than traditionally used coding systems such as convolutional codes and Reed Solomon codes.

The analysis of the complexity of the signal processing algorithms usually focuses on the accounts of the operations. When trying to exploit the hardware parallelism in iterative coding systems, especially in the case of LDPC codes, there is significant complexity not from the point of view of the calculation requirements but rather of the routing requirements. The root of the problems lies in the construction of the codes themselves.

LDPC codes and turbo codes rely on the interleaving of messages within an iterative process. To perform the code well, the interleaving must have good mixing properties. This requires the implementation of a complex interleaving process.

LDPC codes are well represented by bipartite graphics, often called Tanner graphics, in which one set of nodes, the variable nodes, correspond to the bits of the code word and the other set of nodes, the restriction nodes , often called check nodes, correspond to the set of parity check restrictions that define the code. The edges in the graph connect the variable nodes to the restriction nodes. A variable node and a restriction node are said to be neighbors if they are connected by an edge in the graph. For simplicity, we generally assume that a pair of nodes are connected at most by an edge. A bit of the code word is associated to each of the variable nodes. In some cases, some of these bits may be perforated or known, as will be discussed further below.

A bit sequence associated one by one with the sequence of variable nodes is a code word if and only if, for each of the restriction nodes, the neighboring bits of the restriction node (through its association with the nodes of variables) add zero in module two, that is, it comprises an even number of ones.

The decoders and decoding algorithms used to decode the LDPC code words operate by exchanging messages within the graphic along the edges and updating these messages by calculating the nodes based on the incoming messages. Such algorithms will generally be referred to as message passing algorithms. Each of the variable nodes in the graph is initially provided with a software bit, called received value, which indicates an estimate of the associated value of the bit as determined by observations from, for example, the communications channel. Ideally, estimates for separate bits are statistically independent. This ideal can be violated in practice, and is often violated. A collection of received values constitutes a received word. For the purposes of this application we can identify the signal observed by the receiver, for example, in a communication system with the word received.

The number of edges connected to a node, that is a variable node or a restriction node, is referred to as the degree of the node. A regular graph or code is one for which all variable nodes have the same degree, say j, and all restriction nodes have the same degree, say k. In this case we say that the code is a regular code (j, k). These were the codes originally considered by Gallager (1961). In contrast to a "regular" code, an irregular code has restriction nodes and / or variable nodes of different degrees. For example, some variable nodes may be grade 4, others grade 3 and others more grade 2.

Although irregular codes may be more complicated to represent and / or implement, it has been shown that irregular LDPC codes can provide superior error correction / detection operation when compared to regular LDPC codes.

To describe more accurately the decoding process we introduce the notion of a fit in the description of the LDPC graphics. A lace can be seen as an association of an edge in the graph with a node in the graph. Each of the nodes has a lace for each of the edges connected to it and the edges "connect" within the lace. In this way, a node of degree d has d laces attached to it. If the chart has L edges then there are L laces on the side of the variable nodes of the chart, called variable laces, and L laces on the side of the restriction nodes of the chart, called restriction laces. For the purpose of identification and sorting, variable fittings can be numbered 1,…, L so that all variable fittings connected to a variable node appear contiguously. In such a case, if the first three variable nodes have degrees d1, d2, and d3 respectively, then the variable fits 1, ..., d1 are connected to the first variable node, the variable fits d1 + 1, ..., d1 + d2 are connected to the second variable node, and the variable sockets d1 + d2 +1, ..., d1 + d2 + d3 are connected to the third variable node. The constraints of the restriction nodes can be numbered similarly to 1, ..., L with all constraint fittings connected to a constraint node appearing contiguously. An edge can be seen as a matching of lace, each of the pair coming from each side of the graph. Thus, the edges of the graph represent an interleaving or permutation on the fittings from one side of the graph, for example, the side of the variable nodes, to the other, for example the side of the restriction nodes. The permutations associated with these systems are often complex, reflecting the complexity of the interleaver as indicated above, requiring a complex routing of the message passing for implementation.

The notion of message passing algorithms implemented on graphics is more general than LDPC decoding. The overview is a graph with nodes exchanging messages along the edges of the graph and performing calculations based on incoming messages to produce outgoing messages.

An example bipartite graph 100 that determines a regular LDPC code (3, 6) of length 10 and rate of a medium is shown in Fig. 1. Length 10 indicates that there are 10 nodes of variables V1-V10, each identified with a bit of the code word X1 - X10 (and without perforation in this case), generally identified by the reference number 102. A medium rate indicates that there are half of nodes of verification that of nodes of variables , that is, there are five C1-C5 check nodes identified by reference number 106. A one-way rate further indicates that the five restrictions are linearly independent, as discussed below. Each of the lines 104 represents an edge, for example a communication or connection path, between the check nodes and the variable nodes to which the line is connected. Each edge identifies two lace, one variable and one restriction. The edges can be numbered according to their variable fittings and their constraint fittings. The numbering of the variable fittings corresponds to the ordering of the edges (from top to bottom) as it appears on the side of the variable nodes to the point where they are connected to the variable nodes. The numbering of the restriction fittings corresponds to the ordering of edges (from top to bottom) as it appears on the side of the restriction nodes at the point where they are connected to the restriction nodes. During decoding, messages are passed in both directions along the edges. Thus, as part of the decoding process, messages are passed along an edge from a restriction node to a variable node and vice versa.

Although Fig. 1 illustrates the graph associated with a code of length 10, it can be appreciated that the representation of the graph for a code word of length 1000 would be 100 times more complicated.

An alternative to using a graph to represent codes is to use a matrix representation such as that shown in Fig. 2. In the matrix representation of a code, matrix 202 H, commonly referred to as the parity checking matrix , includes the connection of relevant edges, the information of the variable nodes and the restriction nodes. In matrix H, each of the columns corresponds to one of the variable nodes while each of the rows corresponds to one of the restriction nodes. Since there are 10 variable nodes and 5 restriction nodes in the sample code, matrix H includes 10 columns and 5 rows. The matrix entry that corresponds to a particular variable node and a particular restriction node is set to 1 if the edge is present in the graph, that is, if the two nodes are neighbors, otherwise it is set to 0. For example, since the variable node V1 is connected to the restriction node C1 by an edge, a one is placed in the upper left corner of the matrix 202. However, the variable node V4 is not connected to the restriction node C1 so that a 0 is placed in the fourth position of the first row of matrix 202 indicating that the corresponding variable and restriction nodes are not connected. We say that the constraints are linearly independent if the rows of H are linearly independent vectors on GF [2] (a Galois field of order 2). The numbering of edges by fittings, variables or restrictions, corresponds to the numbering of the 1 in H. The numbering of variable fittings corresponds to the numbering from top to bottom within the columns and proceeding from left to right from column to column, as it is shown in matrix 208. The numbering of constraint fittings corresponds to the numbering from left to right through the columns and proceeding from top to bottom from row to row, as shown in matrix 210.

In the case of an array representation, the transmitted code word X can be represented as a vector 206 that includes bits X1-Xn of the code word to be processed. A sequence of bits X1 - Xn is a code word if and only if the product of matrix 206 and 202 is equal to zero, this is Hx = 0.

In the context of the discussion of the code words associated with the LDPC graphics, it should be appreciated that in some cases the code word may be punctured. Perforation is the act of removing bits from a code word to obtain, in effect, a shorter code word. In the case of LDPC graphs this means that some of the variable nodes in the graph correspond to bits that are not actually transmitted. These variable nodes and the bits associated with them are often referred to as state variables. When drilling is used, the decoder can be used to reconstruct the portion of the code word that is not physically communicated on the communication channel. When a perforated code word is transmitted, the receiving device may initially populate the missing values of the received words (bits) with ones and zeros assigned, for example in an arbitrary way, together with an indication (software bit) that these values are completely unreliable, that is, these values are deleted. In order to explain the invention, we assume that, when used, these values populated by the receiver are part of the received word to be processed.

Consider for example the system 350 shown in Fig. 3. The system 350 includes an encoder 352, a decoder 357, and a communication channel 356. The encoder 352 includes an encoding circuit 353 that processes the input data a to produce an X code word. The X code word includes, for the purpose of detection and / or error correction, some redundancy. The code word X can be transmitted over the communication channel. Alternatively, the code word X may be divided through the data selection device 354 into the first and second portions X ', X' 'respectively by some data selection technique. One of the portions of the code word, for example, the first portion X ', can then be transmitted over the communications channel to a receiver including decoder 357 while the second portion X' 'is perforated. As a result of the distortions produced by the communication channel 356, the portions of the transmitted code word may be lost or corrupted. From the perspective of the decoder, perforated data can be interpreted as lost.

The software bits are inserted into the receiver in the received word to take the place of the lost or perforated bits. The inserted software bits indicate the deleted software bits X and / or the bits lost in the transmission.

Decoder 357 will attempt to rebuild the complete code word X from the received word Y, and any inserted software bits, and then perform a data decoding operation to produce A from the reconstructed code word X.

The decoder 357 includes a channel decoder 358 to reconstruct the complete code word X from the received word Y. It also includes a data decoder 359 to eliminate the redundant information included in the code word to produce the original input data. A from the reconstructed code word X.

It will be appreciated that the received words generated in conjunction with the LDPC encoding can be processed by performing the LDPC decoding operations on them, for example, the correction and error detection operations, to generate a reconstructed version of the original code word. The reconstructed code word can then be subjected to data decoding to retrieve the original data that was encoded. The data decoding process can be, for example, simply selecting a specific subset of bits from the reconstructed code word.

LDPC decoding operations generally comprise message passing algorithms. There are many potentially useful message passing algorithms and the use of such algorithms is not limited to LDPC decoding. The present invention can be applied in the context of virtually any such message passing algorithm and therefore can be used in various message passing systems of which the LDPC decoders are only an example.

To complete we will give a brief mathematical description of an embodiment of one of the best known message passing algorithms, known as a propagation of belief.

The spread of belief for LDPC (binary) codes can be expressed as follows. The messages transmitted along the edges of the graph are interpreted as a log of log probabilities (p0 / p1) with pi being the bit associated with the variable node. At this point (p0, p1) they represent a conditional probability distribution over the associated bit. The software bits provided to the decoder by the receiver are also given in the form of a probability register. Thus, the values received, that is, the elements of the word received are log of probabilities of the associated bits conditioned by the observation of the bits provided by the communications channel. In general, a message m represents the probability log m and a received value and represents a probability log y. For punched bits the received value is set to 0, indicating p0 = p1 = ½.

Consider the message passing rules of the spread of belief. The messages are named by mC2V for messages from the check nodes to the variable nodes and by mV2C for the messages from the variable nodes to the check nodes. Consider a variable node with edges. For each of the edges j = 1,… d, let mC2V (i) be the incoming message on the edge i. Very early in the decoding process we set mC2V = 0 for each edge. Then the outgoing messages will be given by

mV2C (j) = y + Σdi = 1 mC2V (i) - mC2V (j)

In the check nodes it is more convenient to represent the messages using their 'sign' and magnitudes. Thus for the message m, let mp ∊GF [2] denote the 'parity' of the message, that is, mp = 0 if m ≥ 0 and mp = 1 if m <0. Additionally, let mr ∈ [0 , ∞] denoting the magnitude of m. In this way, we have m = -1mpmr. In the check node the updates for mp and mr are separated. We have, for a test node of degree d

mpC2V (j) = (Σdi = 1 mpV2C (I)) - mpV2C (j),

where all the addition is about GF [2], and

mrC2V (j) = F-1 ((Σdi = 1 F (mrV2C (i))) - F (mrV2C (j))),

where we define F (x) = log coth (x / 2). (In both of the previous equations the superscript V2C indicates incoming messages in the check node). We observe that F is equal to its own inverse F-1 (x) = F (x).

Most message passing algorithms can be seen as approximations to the propagation of belief. It will be appreciated that in any practical digital implementation the messages will comprise a finite number of bits and adapted message adaptation standards.

It will be evident that the complexity associated with the representation of LDPC codes for long code words is of enormous proportions, at least for hardware implementations that attempt to exploit the parallelism. In addition, it can be difficult to implement message passing so that it supports processing at high speeds.

To make more practical use of LDPC codes, procedures for representing LDPC codes corresponding to long code words are needed in an efficient and compact manner thereby reducing the amount of information required to represent the code, that is, describing The associated graphic. In addition, there is a need for techniques that allow the passage of messages associated with multiple nodes and multiple edges, for example, four or more nodes or edges, to be performed in parallel in an easily controlled mode, thus allowing even long Code words are decoded effectively in a reasonable amount of time. There is also a need for a decoder architecture that is flexible enough to decode several different LDPC codes. This is because many applications require codes of different lengths and rates. An architecture that allows the specification of a particular LDPC code to be programmable is even more desirable.

Brief Description of the Figures

Figure 1 illustrates a representation of a bipartite graph of an example regular LDPC code of length ten.

Figure 2 is a matrix representation of the code illustrated graphically in Fig. 1.

Figure 3 illustrates the coding, transmission and decoding of data.

Figure 4 illustrates a representation of a bipartite graph of an example irregular LDPC code

Figure 5, comprising the combination of Figs 5a through 5d, illustrates steps performed as part of the LDPC decoding operation in accordance with the LDPC code illustrated in Fig. 4.

Figure 6 is a graphical representation of a small LDPC code that is used as the basis of a much longer LDPC code to present an example according to the present invention.

Figure 7 illustrates the representation of the parity check matrix of the small LDPC code illustrated graphically in Fig. 6.

Figure 8 illustrates how the edges in the code shown in Fig. 6 can be arranged, for example, numbered in order from the side of the variable nodes and how the same edges would appear from the side of the restriction nodes.

Figure 9 illustrates a system for performing a serial LDPC decoding operation.

Figure 10 graphically illustrates the effect of making three copies of the small LDPC chart shown in Fig. 6.

Figure 11 illustrates the representation of the parity check matrix of the LDPC chart shown in Fig. 10.

Figure 12 illustrates how the edges can be arranged in the code shown in Fig. 11, for example numbered in order from the side of the variable nodes and how the same edges will appear from the side of the restriction nodes.

Figure 13 illustrates the effect of replacing the 3x3 identity matrices shown in Fig. 11 with cyclic permutations matrices in accordance with an exemplary embodiment of the present invention.

Figure 14 illustrates how the edges can be numbered in the code shown in Fig. 13 from the side of the variable nodes, and how the same edges will appear from the side of the restriction nodes after undergoing a cyclic permutation of according to the invention.

Figure 15 illustrates an LDPC decoder implemented in accordance with the present invention that converts the decoder of Fig. 9 to vectors.

Figures 16 and 17 illustrate the other LDPC decoders implemented in accordance with the present invention.

The attention of a document by Boutillion E and others is called: "Design of the first code decoder", PROC. OF THE INTERNATIONAL SYMPOSIUM ON TURBO CODES AND RELATED ISSUES, BREST, FRANCE, September 4, 2000, pages 459 - 462, XP08011934 and others. The document describes a decoder architecture for a Low Density Parity Check code. In particular, an architecture is described that uses N distinct memories that are addressed separately. In the system, N elements are selected randomly one at a time from each of the N memories addressed separately and randomly.

Summary of the invention

In accordance with the present invention, as shown in claim 1 there is provided an apparatus for performing message step decoding operations, and methods for performing message step decoding processing, as shown in the claims. 17 and 26. The embodiments of the invention are claimed in the dependent claims.

The present invention is directed to methods and an apparatus for performing word decoding operations using message passing decoding techniques. The techniques of the present invention are particularly well suited for use with long LDPC codes, for example, code words of more than 750 bits in length, but can also be used for shorter lengths. The techniques and apparatus of the present invention can also be used for graphic design and decoding where other types of message passing algorithms are used. For purposes of explaining the invention, however, LDPC decoders and example decoding techniques will be described.

The techniques of the present invention allow the decoding of LDPC graphics that have a certain hierarchical structure in which a complete LDPC graphic appears to be, in large part, made up of multiple copies, say Z, of a smaller times Z chart. The Z copies of the chart may be identical. To be precise, we will refer to a smaller graph as the projected graph. The technique can be better appreciated by first considering a decoder that decodes Z small identical LDPC graphics synchronously and in parallel. Consider a message passing decoder for a single small LDPC graphic. The decoder implements a sequence of operations that correspond to a message passing algorithm. Consider now increasing the same decoder so that it decodes such identical Z LDPC graphics synchronously and in parallel. Each of the operations in the message passing algorithm is repeated Z times. Note that the efficiency of the decoding process will improve because, in total, decoding proceeds Z times faster and because the control mechanisms required to control the message passing process do not need to be replicated for the Z copies but can instead be shared by The Z copies. We can also see that the previous decoder of Z copies in parallel as a vector decoder. We can see the process of making Z copies of the smaller graph as a conversion to vectors of the smaller (projected) graph: Each of the nodes of the smaller graph becomes a vector node, comprising Z nodes, each From the edges of the smaller graphic it becomes a vector edge, consisting of Z edges, each of the messages exchanged in decoding the smaller graphic becomes a vector message, which comprises Z messages.

The present invention obtains the efficiency of the conversion to vectors described above while modifying it so that the decoder of vectors is in fact the decoding of a large graph, Z times greater than the projected graph. This is done by interconnecting the Z copies of the projected graph in a controlled way. Specifically, we allow the Z edges within a vector edge to suffer a permutation, or exchange, between copies of the projected graph as they move forward, for example, from the side of the variable nodes to the side of the restriction nodes. In the process of passing the vector message corresponding to the Z graphics projected in parallel this exchange is implemented by swapping the messages within a vector message as they pass from one side of the vector graphic to the other.

We consider indexing the LDPC graphs projected by 1, j,…, Z. In the strictly parallel decoder, the variable nodes in graph j are connected only with constraint nodes in graph j. In accordance with the present invention, we take an edge of vectors, including the edge corresponding to each of the copies of the graph, and allow a permutation within the Z edges, for example we allow the constraint fittings corresponding to the edges within vector edges permute, that is, reorder. From now on we will often refer to permutations, that is, rearrangements, within vector edges as rotations.

Thus, according to the present invention, a relatively large graph can be represented, that is, described, using relatively little memory. For example, a graph can be represented by storing the information describing the projected graph and the information describing the rotations. Alternatively, the description of the graph can be performed as a circuit that implements a function that describes the connectivity of the graph.

Accordingly, the graphic representation technique of the present invention facilitates the implementations of graphics, for example, converted to vectors. In addition, the graphics representation techniques of the present invention can be used to support decoding of regular or irregular graphics, with or without status variables. Information describing the degrees of the nodes in the projected graph can be stored and provided to a vector node processing element. Note that all nodes that belong to a vector node will have the same degree so that grade information is required only for a projected graph.

In various embodiments, the decoder is made programmable thereby allowing it to be programmed with multiple graphics descriptions, for example, as expressed in terms of stored projected graphics and stored rotation information or in terms of an implemented function. Accordingly, the decoders of the present invention can be programmed to decode a large number of different codes, for example, both regular and irregular. In some particular embodiments the decoder is used for a fixed graph or for fixed degrees and this information. In such embodiments the description information of the graph can be programmed beforehand or implicitly. In such cases the decoder may be less flexible than the programmable embodiments but the resources required to support the programming functionality are saved.

In accordance with an embodiment of the present invention, a message memory is provided that includes rows of memory locations, each row corresponding to the messages associated with a copy of the projected graphic. The messages corresponding to the multiple projected Z graphics are stored to form columns of Z messages per column, so that one column corresponds to a vector message. This memory arrangement allows vector messages, for example, a set of Z messages, corresponding to the edge of vectors to be read or written to memory as a unit, using for example a SIMD instruction to access all Z messages in a column in an operation. In this way memory supports reading and writing vector messages as units. Accordingly, the present invention avoids the need to provide a different read / write address for each of the individual messages in a set of Z messages.

At one or more points in the message passing processing, after reading the memory, the Z messages are subject to a permutation operation, that is, a reordering operation. The rearrangement operation can be a rotation operation, or a rotation to shorten. These rotation operations correspond to the rotations associated with the vector edges that interconnect the Z copies of the projected graph to form the only large graph. This rotation can be applied, for example, before delivering the messages to the corresponding vector node processor (restriction or variable). Alternatively, the rotation can be applied later to the processing by the vector node processor.

The rotation can be implemented using a simple switching device that connects, for example, the message memory with the vector node processing unit and rearranges those messages as they pass from the memory to the vector node processing unit. . In such an exemplary embodiment, one of the messages in each of the vector messages read from the memory is supplied to the corresponding unit of the Z parallel node processing units, within a vector node processor, as determined by the rotation applied to the vector message by the switching device. A rotation operation as implemented by the switching device can also be applied or alternatively to the vector message before it is written to memory and subsequent node processing.

The stored or calculated description of the projected graph may include, for example, information on the order in which the messages in a row corresponding to the projected graph will be read and / or written in memory during the processing of restriction and / or variable nodes. . The messages of the entire large graphic are stored in multiple rows, each of the rows corresponding to a different copy of the small graphic, the rows being arranged to form message columns. Each of the message columns represents a vector message, which can be accessed as a single unit. Thus, information on how to access messages in a row of a projected graphic can be used to determine the order in which vector messages corresponding to multiple copies of the projected graphic are accessed in accordance with the present invention.

The variation of the order in which vector messages are read and / or written to memory according to whether the read / write operation corresponds to a processing of the side of the variable nodes or of the side of the restriction nodes can be described as a first permutation performed on the messages. This permutation corresponds to the interleaver associated with the projected graph. To represent the large decoder graphic from the projected decoder graphic, a second set of permutation information, for example, rotation information, is stored in addition to the information of the order of access to vector messages (for example, the spine). The second permutation information (for example, the rotation information), which represents the switching control information, indicates how the messages in each of the vector messages should be rearranged, for example, the message columns, when, by example are read and / or written to memory. This two-stage permutation divides the larger permutation that describes the entire LDPC chart into two parts implemented through different mechanisms.

In a particular embodiment, a cyclic permutation is used as the second level of permutation due to the ease with which such permutation can be implemented and the compactness of the description. This case motivates the use of terms rotation to describe this second level permutation for the purpose of explanation. However, it will be understood that the second level of permutation does not need to be limited to rotations and can be implemented using other rearrangement schemes.

In various embodiments of the present invention, the decoder generates outputs of multiple software bits with one bit, for example, as a sign bit or parity bit of each of the software outputs, corresponding to a hardware decision output of the decoder, by For example, the original code word in the case where all errors have been corrected or there is no error present in the received word. The decoder output, for example the recovered code word, can then be processed to retrieve the original data that was used at the time of encoding to produce the transmitted code word.

In accordance with a feature of the present invention the hardware and / or software outputs produced after each of the complete iterations of the processing of variable nodes are examined to determine whether the parity check restrictions indicative of a code word are satisfied by the current hardware decisions. This verification process also enjoys the benefits of the permutation structure divided into the two stages of the graph. The iterative decoding process (message passing) can be stopped once the code word retrieval is detected in this way. Therefore, in the case of relatively error-free signals, decoding can be completed and detected immediately, for example, after two or three iterations of the message passing decoding process. However, in the case of received words that include more errors, numerous iterations of the decoding process may occur before the decoding is successful or the process is stopped due to a timing restriction.

The detection of the satisfactory decoding indication, in accordance with the present invention, allows more efficient use of resources compared to systems that allocate a fixed number of decoding iterations for each of the words received.

As the decoding techniques of the present invention allow a large number of decoding operations, for example processing operations of the decoder of restriction and / or variable nodes, to be performed in parallel, the decoders of the present invention can be used to decode words received at high speeds. In addition, given the novel technique of the present invention used to represent large graphics and / or control of message passing for decoding operations associated with such graphics, the storage difficulties of large graphics descriptions and the routing control of their messages are reduced and / or exceeded.

Certain generalizations of the LDPC codes and decoding techniques of the invention include encoding / decoding over larger alphabets, not simply bits, which have two possible values, but a greater number of possibilities. The codes where the restriction nodes represent different restrictions than the parity check restrictions can also be decoded using the methods and apparatus of the present invention. Other relevant generalizations to which the invention can be applied include situations in which a message passing algorithm will be implemented on a graphic and there is the option of designing the graphic. It will be apparent to those skilled in the art, in view of the present patent application, how to apply the techniques of the present invention to these more general situations.

Numerous additional advantages, features and aspects of the decoding techniques and decoders of the present invention will be apparent from the detailed description that follows.

Detailed description of the invention

As discussed above, the decoding procedures and apparatus of the present invention will be described for purposes of explanation in the context of an embodiment of the LDPC decoder. First, the steps involved in decoding an LDPC code will be described with reference to Figs. 4 and 5 followed by a more detailed description of various features of the present invention.

Figure 4 illustrates an example irregular LDPC code using a bipartite graph 400. The graph includes m check nodes 402, n nodes of variables 406, and a plurality of edges 404. The messages between the check nodes and the nodes of variables are exchanged over edges 404. The software input bits y1 to yn correspond to the received word Y, and the software outputs (or hardware) x1 to xn are indicated by the numerical reference 408. The order check node m is identified using numerical reference 402 ', the order variable node n is identified using numerical reference 406' while the software input of order n and n and the software output of order n xn are indicated in Fig. 4 using the reference numbers 410 and 409 respectively.

The variable nodes 406 process the messages of the restriction nodes 402 together with the software input values from the received word y1, ... yn to update the value of the output variables x1, ... xn corresponding to the variable nodes and for generate messages for restriction nodes. A message is generated by a variable node for each of the edges connected to the variable node. The generated message is transmitted along the edge from the variable node to the restriction node connected to the edge. For the purpose of explanation, the messages from the variable nodes to the restriction nodes will be indicated, from time to time, in the present application using the abbreviation V2C while the messages from the variable nodes to the restriction nodes will be indicated using the abbreviation C2V. Indexes can be added to the V and C components of this abbreviation to indicate the particular node of the variable nodes and the restriction nodes that serves as the source / destination of a particular message. Each of the restriction nodes 402 is responsible for processing the messages received from the variable nodes through the edges connected to the particular restriction node. The V2C messages received from the variable nodes are processed by the restriction nodes 402 to generate the C2V messages that are then transmitted back along the edges connected to each of the restriction nodes. Variable nodes 406 then process the C2V messages, together with the software input values, to generate and transmit new V2C messages, and generate the software outputs xi. The sequence of processing in the nodes of variables 406 comprises: the transmission of the messages generated to the check nodes 402, generating in the nodes of software outputs xi and receiving the messages from the check nodes, can be performed repeatedly, that is, iteratively, until the outputs xi from the variable nodes 406 indicate that the code word has been successfully decoded or some other stop criteria, for example, the termination of a fixed number of iterations of step of posts. It should be appreciated that the sequence of operations described above is not necessary to occur strictly in the order described. The processing of nodes can continue asynchronously and the processing of nodes of variables and restrictions can occur simultaneously. However, the logic of the iterative process is as described.

The messages, V2C and C2V, can be one or more bits, for example K bits each, where K is a positive integer value other than zero. Similarly, the xi software outputs can be single or multi-bit. Multi-bit messages and outputs provide the opportunity to pass the trust or reliability information in the message or output. In the case of a multi-bit output (software), the sign of the value of the software output can be used to provide the hardware output of a single bit of the decoding process corresponding to a variable node, for example the bits of the Decoded code word. The software output values can correspond to decoded software values or, alternatively, to an information called extrinsic (excluding the corresponding input information) that can be used in other longer iterative processes within which the LDPC decoder is only one module.

The iterative message passing process associated with decoding an LDPC code will now be discussed further with respect to Figs. 5a through 5d.

When an LDPC code is decoded, the processing in each of the restriction nodes and variable nodes can be performed independently. Therefore, the processing of variable and / or restriction nodes can be performed one node at a time, for example, in sequence, until some or all of the processing of the variable and restriction nodes have been completed for a particular iteration of the process decoding This allows to provide and reuse a single hardware processing unit, if desired, to perform the processing associated with each of the variable and / or restriction nodes. Another significant feature of LDPC decoding is that the V2C and C2V messages used during a particular processing iteration do not need to be generated at the same time, for example during the same process iteration. This allows implementations where the processing of restriction nodes and variables can be performed in parallel without taking into account when the updated messages were last updated. Following a sufficient number of message updates and iterations where all the variable nodes and restrictions process the received messages and generate updated messages, the output (hardware) of the variable nodes will converge assuming that the graphic is properly designed and not There are uncorrected errors in the received word that is being processed.

Since the processing of each of the check nodes and variable nodes can be seen as an independent operation, the iterative processing performed on a single example check node Cn 502 'and the variable node Vn 506' will be treated with more detail with reference to Fig. 5a-5d. For description purposes we will think that the message values, the software input and the output values are numbers. A positive number corresponds to a hardware decision of bit 0 and a negative number corresponds to a hardware decision of bit 1. Higher magnitudes indicate greater reliability. Thus, the number zero indicates a total lack of reliability and the sign (positive or negative) is irrelevant. This convention is consistent with the standardized practice in which software values (messages, received and output values) represent log of associated bit probabilities, that is, software values take the form

log (probability that the bit is 0 / probability that the bit is 1)

in which the probability is conditioned on a random variable, for example, the physical observation of the communications channel bit in the case of a received value.

Fig. 5a illustrates the initial stage in an LDPC decoding process. Initially, the variable node Vn 506 'is supplied with the software input, for example the received values (1 or more bits) and n from the received word to be processed. The C2V messages at the beginning of the decoding operation and the Xn 509 software output are initially set to zero. Based on the inputs received, for example, the zero value C2V messages and the yn input, the variable node Vn 506 'generates a V2C message for each of the check nodes to which it is connected. Typically, in the initial stage, each of these messages will be equal to yn.

The generated V2C messages that are transmitted along each of the edges connected to the variable node Vn 506 'are shown in Figure 5b. Thus, the updated V2C messages are transmitted to each of the check nodes 502 coupled to the variable node Vn506 'including the check node Cm 502'.

In addition to generating the V2C messages, the processing of the variable nodes results in the update of the Xn 509 'software output corresponding to the variable node that performs the processing. The Xn software output is shown updating in Fig. 5c. Although they are shown as different stages, the software output can be an output at the same time that V2C messages are taken.

As will be discussed further below, in accordance with some embodiments of the present invention, software outputs (or their associated hardware decisions) can be used to determine when a code word has been retrieved from the received word, that is, when parity restrictions for exit values have been satisfied. This indicates a satisfactory decoding (although the code word found may be incorrect, that is, not the one that was transmitted) therefore allowing the iterative decoding process to stop in a timely manner, for example before the completion of the maximum set number of message step iterations allowed.

The processing of the check nodes can be performed once the check node, for example the check node Cm 502 ', receives V2C messages along the edges to which it is connected. The received V2C messages are processed in the check node to generate the updated C2V messages, one for each of the edges connected to the particular check node. As a result of the processing of the check node, the C2V message transmitted back to the variable node along an edge will depend on the value of each of the V2C messages received on the other edges connected to the check node but not (usually and preferably but not necessarily) once the V2C message has been received from the particular variable node to which the C2V message is being transmitted. In this way, C2V messages are used to transmit information generated from messages received from nodes of different variables than the node to which the message is being transmitted.

Fig. 5d illustrates the passage of the updated C2V messages to the variable nodes including node 506 '. In particular, in Fig. 5d the restriction node Cm 502 'is shown by taking out two updated C2V messages, the updated Cm2Vn message being supplied to the variable node Vn 506'. Vn 506 'also receives additional updated C2Vn messages from other restriction nodes to which it is connected.

With the reception of updated C2V messages, the processing of variable nodes can be repeated to generate the updated V2C messages and the software outputs. The update of the C2V messages can then be repeated and so on until the decoder stop criterion is satisfied.

Thus, the processing shown in Figs. 5a-5d will be repeated after the first iteration, using updated message values instead of the initial values, until the decoding process is stopped.

The iterative nature of the LDPC decoding process, and the fact that the processing on the individual nodes can be performed independently of the processing of the other nodes provides a high degree of flexibility when an LDPC decoder is implemented. However, as discussed above, the mere complexity of the relationships between the edges and the nodes can make it difficult to store the information of the edges' relationships, that is, the description of the graph. Even more importantly, the complexity of the graphic can make it difficult to implement the passage of messages in parallel implementations where multiple messages are passed at the same time.

Practical implementations of the LDPC decoder often include a memory of edges to store the messages that pass along the edges between restriction nodes and / or variable nodes. They also include a graphics descriptor sometimes referred to as a permutations map which includes specification information of the edge connections, or lace matching, thus defining the decoding graph. This permutations map can be implemented as stored data or as a circuit that calculates or implies permutation. In addition to edge memory, one or more node processing units are necessary to perform the actual processing associated with a node.

The implementations of the LDPC software decoder are possible, in which the software is used to control a CPU to function as a vector processing unit and to control the passage of messages using a memory coupled to the CPU. In software implementations, a single memory can also be used to store the decoder graphic description, edge messages, as well as the decoder routines used to control the CPU.

As will be discussed below, in various implementations of the invention one or more edge memories may be used. In an exemplary embodiment of multiple edge memories, a first edge memory is used for storing and passing the C2V messages and a second edge memory is used for storing and passing the V2C messages. In such embodiments, multiple node processing units can be employed, and often used, for example, one to perform the restriction node processing and another to perform the processing of variable nodes. As will be discussed below, such embodiments allow variable processing operations and restrictions to be carried out in parallel by writing the resulting messages within each of the two message memories to be used during the next iteration of the decoding process.

We will now present a simple example of a small graph of LDPC and its representation that will be used later in the explanation of the invention. The discussion of the LDPC graphic will be followed by a description of an LDPC decoder that can be used to decode the small graphic.

Fig. 6 illustrates an irregular simple LDPC code in the form of a graph 600. The code is of length 5 as indicated by the 5 variable nodes from V1 to V5 602. Four check nodes from C1 to C4 606 are coupled to the nodes of variables 602 for a total of 12 edges 604 over which the messages can be passed.

Fig. 7 illustrates the LDPC code shown in Fig. 6, using matrices 702, 704, in the form of parity checking matrices. As discussed above, the edges are represented in the permutation matrix H 702 using ones. The xi bit is associated with the Vi variable nodes. Matrices 706 and 708 show the ones in matrix H, corresponding to the edges in the graph, indexed according to the order of variable fittings and the order of constraint fittings, respectively.

For the purpose of explanation, the 12 edges will be numbered from the side of the variable nodes, that is, according to their variable fittings, The connections established by the edges between the variable nodes 602 and the check nodes 606 can be seen in Fig. 6. For the purpose of the discussion, the edges connected to the variable V1 that connect it with their check nodes C1, C2 and C3 are assigned labels 1, 2, 3, corresponding to the numbering of variable fittings . Variable node V2 is connected to check nodes C1, C3 and C4 by edges 4, 5, and 6 respectively. Variable node V3 is coupled to check nodes C1 and C4 by edges 7 and 8, respectively. In addition, variable node V4 is coupled to check nodes C2 and C4 by edges 9 and 10, respectively, while variable node V5 is coupled to check nodes C2 and C3 by edges 11 and 12, respectively. This indexation corresponds to matrix 706 of Figure 7, that is, the order of variable fittings.

Figure 8 illustrates the relationships between the 12 edges of Fig. 6, as numbered from the side of the variable nodes, in relation to the variable and check nodes to which they are connected. Row 802 shows the 5 nodes of variables V1 through V5. Below the 802 variables, edges 1 through 12, 804 corresponding to the associated fittings that are connected to a particular variable node are shown. Note that since the edges are sorted from the side of the variable nodes, in row 804 they appear in the order of 1 to 12. Assume that the messages are stored in memory in the order indicated in row 804.

During the processing of variable nodes, the 12 edge messages in the memory are accessed in sequence, for example, in the order shown in 804. Thus, during the processing of the variable nodes, the messages can be read so Simple in order and supplied to a processing unit.

Row 806 illustrates the four restriction nodes from C1 to C4 present in the code of Figs. 6 and 7. Note that the edges are reordered in row 804 'to reflect the order in which they are connected to the restriction nodes , but the indicated indexing is that induced from the side of the variable nodes. Therefore, assuming that the messages of the edges are stored in order from the side of the variable nodes, when the processing of restriction nodes is performed the messages would be read in the order illustrated in row 804 '. That is, during the processing of restriction nodes the messages would be read from the memory in the order 1, 4, 7, 2, 9, 11, 3, 5, 12, 6, 8, 10. An order module can be used of messages to get the correct sequence of access information from edge messages, for example, memory locations, to read data from memory or write data to memory during variable node checking and checking operations .

An LDPC 900 series decoder that performs message processing operations sequentially, one edge at a time, will now be treated in relation to Fig. 9 and decoding will be treated using the example code shown in Fig. 6. The decoder LDPC 900 comprises a decoder control module 902, a message order module (lace permutation memory) 904, a node grade memory 910, a edge memory 906, a node processor 908, a buffer memory of output 916, a hardware decision memory 912 and a parity check verifier 914.

Edge memory 906 includes the memory locations of the LK bits each of the K bit locations corresponding to an edge and where L is the total number of edges in the LDPC graph being used and K is the number of bits per message exchanged along an edge. To specify, we assume that the messages are stored in order according to the order of edges induced by the variable fittings. Thus, for the example graphic 600 the messages corresponding to edges 1, 2,…, 12 are stored in the order indicated. Hardware decision memory 912 includes L 1-bit memory locations, each of the 1-bit locations corresponding to an edge. This memory stores hardware decisions transmitted by the variable nodes along each of its edges so that the parity check restrictions can be verified. The parity check verifier 914 receives the hardware bit decisions as the processor of the check nodes receives messages. Parity checks are verified in the parity check verifier and, in the event that all checks are satisfied, it transmits a convergence signal to the control module of the decoder

902

The message order module 904 can be implemented as a permutations map or a search table that includes information describing the ordering of messages in the edge memory as seen from the side of the variable nodes or as seen from the side of the restriction nodes. Thus, for our example graph 600, the sequence 1, 4, 7, 2, 9, 11, 3, 5, 12, 6, 8, 10 that specifies the order of the edges as seen from the side of The restrictions would be stored, effectively in the message order module. This sequence is used to sort the messages for the processing of the restriction nodes and to sort the hardware decisions read from the Hardware Decision Memory 912 for processing by the parity check verifier 914.

In the decoder of Fig. 9, messages corresponding to an edge are overwritten after they are processed by a node processor. In this way, edge memory will alternate between V2C message storage and C2V message storage. Hardware decision verification occurs during the processing of restriction nodes, for example as V2C messages are read from edge message memory 906.

The decoder control unit 902 is responsible for alternating the operation of the decoder between the modes of operation of the processing of variable nodes and of checking, to determine when the iterative decoding process should stop, for example due to the reception of a signal of convergence or search for a maximum allowable iteration account, to supply and control the supply of grade information to the node processing unit and the parity check verifier, and to control the supply of an edge index to the Module of Message Ordering 904. During operation, the control module of the decoder 902 transmits an edge index to the message ordering module 904. The value of the edge index is increased in time for a sequence through all edges on the chart. A different edge index, for example unique is used for each of the edges in a chart that is being implemented. In response to each of the edge indexes received, the message sorting module will output an edge identifier, for example, the address information of the edge memory, thereby selecting the location of the edge memory to be access, for example, reading or writing at any given time. Assuming the ordering of the variable fittings, the message ordering module 904 will cause the messages to be read or written again in sequential order during the processing of the variable nodes and will cause the messages to be read and written again. in the order corresponding to the order of restriction reserve requirements during the processing of the restriction nodes. Thus, in our previous example, the messages will be read and rewritten in the order 1, 2, 3,…, 12 during the processing of the variable nodes and, at the same time, the hardware decisions will be written into from hardware decision memory 912 in the order 1, 2, 3,…, 12. During the processing of restriction nodes the messages will be read and written again in the order 1, 4, 7, 2, 9, 11, 3, 5, 12, 6, 8, 10 and, at the same time, the message order module 904 will cause the hardware decision bits to be read from the hardware decision memory 912 in the order 1, 4, 7, 2 , 9, 11, 3, 5, 12, 6, 8, 10.

As the messages in the edge memory are read in response to the edge identifier received from the control module of the decoder 902, they are supplied to the node processor 908. The node processor 908 performs the operation of restriction node processing or of appropriate variables, depending on the mode of operation, therefore using the messages received to generate updated messages corresponding to the particular node that is being implemented at any given time. The resulting updated messages are then written back to the edge memory overwriting the messages that have just been read from memory. Messages sent to a particular node arrive at the node processor as contiguous blocks, that is, one after another. The control module of the decoder 902 signals the delineation of nodes to the node processor, for example indicating the last message corresponding to a node thereby providing the node degree information. In the case of example graph 600, the degrees of the variable nodes would be specified, for example as the sequence (3, 3, 2, 2, 2) and the degrees of the restriction nodes would be specified, for example, as the sequence (3, 3, 3, 3). This information can be stored in a memory of node grades 910 which would then be read by the decoder control module 902 as it iterates over the edge indexes. Alternatively, grade information can be programmed within each of the node processing units. This may be preferable, for example when it is known in advance that the degrees of the nodes will be uniform, that is, the graph will be regular.

Parity check verifier 914 works in much the same way as a check node processor except that the incoming messages are simple bits, no outgoing message is calculated, and the internal calculation is simpler.

During the operation of the variable node mode, the calculations of the variable nodes, will be performed one node at a time by the node processing unit until the processing is completed, for example the update of the messages and the generation operations of value of the software output associated with each of the variable nodes. The messages are supplied to the node processor 908 in the order of the side of the variable nodes so that all messages corresponding to a node arrive in sequence to the node processor 908. Once the iteration of the processing of the variable nodes is completed , the control module of the decoder 902 causes the decoder 900 to switch to the restriction node mode of the processing operation. In response to the change of the C / V control signal (Restriction / Variable), the node processing unit 908 switches from the variable node processing mode to the restriction node processing mode. In addition, the message order module 904 switches to a processing mode in which the message identifiers will be supplied to the edge memory in the order of the constraints' fittings. One or more control signals sent on the C / V control line can be used to control the switch between the modes of operation of restriction node and variable processing.

As the decoder control circuit 902 controls the decoder to perform restriction node processing in a sequence of restriction nodes, one node at a time, the messages stored in the edge memory will be updated once again, this time for C2V messages generated by restriction node processing. When the processing associated with the total set of restriction nodes has been completed, the control circuit of the decoder 902 will switch back to the variable node mode of the processing operation. In this way, the decoder 900 alternates between the processing of variable nodes and restriction nodes. As described, the processing is performed sequentially, one node at a time, until the control circuit of the decoder 902 determines that the decoding operation has been completed.

The scalar or sequential LDPC decoding system illustrated in Fig. 9 can be implemented using relatively little hardware. It also tends for itself to software implementation. Unfortunately, the sequential nature of the processing performed tends to result in a relatively slow implementation of the decoder. Therefore, although the scalar architecture shown in Fig. 9 has some notable attributes, it tends to be inappropriate for high bandwidth applications such as optical communications or data storage where high speed decoding and the use of Long code words.

Before presenting the decoders for decoding large LDPC graphics converted to vectors, we will discuss general concepts and techniques related to the characteristics of the conversion of graphics to vectors of the present invention. The discussion of conversion to vectors will be followed by a presentation of

5 example LDPC decoders, converted to vectors performed by the present invention.

In order to obtain the understanding of LDPC graphics converted to vectors, we consider a 'small' LDPC code with the parity checking matrix H. The small graphic in the context of a larger graphic converted to vectors, will be referred to as projected graphics. Let Ψ be a subset of permutation matrices of Z x Z. We assume that the inverses of the permutations in Ψ are also in Ψ. Given the small projected graph, we can form a LDPC Z times larger graph by replacing each of the elements of H with a matrix of Z x Z. Elements 0 of H are replaced with the zero matrix, denoted by 0. Elements 1 of H are each replaced with a matrix of Ψ. In this way we 'raise' the degree of LDPC to another Z times greater. The complexity of the representation comprises approximately the number of bits required to specify permutation matrices, | EH | log | Ψ | plus the complexity required to represent H, where | EH |

15 denotes the number of ones in H and | Ψ | denotes the number of different permutations in Ψ. For example, if Ψ is the cyclic permutations space then | Ψ | = Z. In practice we could have, for example Z = 16 for n = 1000.

image 1

Example: By raising a small parity check matrix, σi for i = 1, ... 16 are elements of Ψ shown at this point indexed in the order of the projected variable fittings.

The subset Ψ can be chosen in general using various criteria. One of the main motivations for the previous structure is to simplify the hardware implementation of the decoders. Therefore, it may be beneficial to restrict per to permutations that can be effectively implemented in hardware, for example in a switching network.

25 The topologies of parallel switching networks is a topic well studied in connection with the architectures of multiprocessors and high-speed switching switches. A practical example of architecture suitable for the subset of permutations Ψ is a class of multilayer switching networks including, for example, omega (perfect shuffled) / delta networks, register shift networks, etc. These networks offer reasonable implementation complexity and sufficient wealth for the subset Ψ. Additionally, multilayer switching networks are well scaled, for example, their complexity is presented as N log N where N is the number of inputs to the network, which makes them especially suitable for massively parallel LDPC decoders. Alternatively, in the decoders of the present invention with relatively low levels of parallelism and small Z, they can implement the subset Ψ of permutations in a single layer.

35 An LDPC chart is said to have "multiple edges" if any pair of nodes is connected by more than one edge. A multiple edge is the set of edges that connect a pair of nodes that are connected by more than one edge. Although it is generally not desirable for an LDPC chart to have multiple edges, in many cases it may be necessary in the construction of graphics converted to vectors, in which the projected chart has multiple edges. The notation of a parity check matrix can be extended to allow matrix entries to denote the number of edges that connect the pair of associated nodes. The definition of the code word is still the same: the code is the set of 0.1 1 x vectors that satisfy that Hx = 0 in module 2. When a projected graph with multiple edges is converted to vectors, according to the invention, each of the edges within a multiple edge is replaced with a permutation matrix from T and these matrices are added to obtain the extended parity check matrix of the total code. Of this

45 mode, a value of j> 1 in the parity check matrix H of the projected graph will be 'raised' to a sum σk

+ σk + 1 +… + σ k + j-1, of the permutation matrices from Ψ. Usually, the elements of the sum will be chosen so that each of the entries σk + σk + i + ... + σ k + j-1 is either zero or one, that is, the total graph has no multiple edges.

The elevation described above seems to have a limitation. Under the previous construction both the code length and the length of the encoded data unit must be multiples of Z. However, this apparent limitation is easily overcome. Assume that the unit of data to be encoded has a length AZ + B where A is a positive integer and B is between 1 and Z inclusive, and the desired code length is CZ + D where C is a positive integer and D is between 0 and Z-1 inclusive. Let E be the smallest positive integer such that EZ ≥ CZ + D + (Z - B). An elevated graph that encodes the length data unit (A + 1) Z can be designed to produce an EZ length code word so that the data unit appears as part of the code word, and uses this to produce the desired code parameters as follows. Given a data unit of length AZ + B, Z-B zeros are concatenated to produce a data unit of length (A + 1) Z. That data unit is encoded to produce a code word of length EZ. Z - B zeros are not transmitted. From the other EZ - (Z - B) bits in the code word, EZ - CZ - D - (Z - B) bits are selected and drilled, note that the number of drilling bits is between 0 and Z-1 inclusive . These bits will not be transmitted, so the actual number of bits transmitted is EZ - (Z - B) - (EZ - CZ - D - (Z - B)) = CZ + D, which is the desired code length . The receiver who has prior knowledge about the additional zeros and the perforated bits replaces the software bits with the perforated bits indicating erase, and replaces the software bits with the known zero bits indicating a zero value with the highest possible reliability. The extended word received, of length EZ can now be decoded to retrieve the original data unit. In practice, these adjustments are usually made by drilling bits of only one vector node and declaring known bits of only one vector node.

We now turn to various implementations of decoders that use the technique discussed above to convert LDPC graphics to vectors.

As previously discussed, the decoding of message passing of the LDPC codes involves the passage of messages along the edges of the graph representing the code and the calculation based on those messages in the nodes of the graph, it is that is, the nodes of variables and restrictions.

Given an LDPC graphic converted to vectors, decoding processes can be converted to vectors as follows. The decoder works as if Z copies of the projected LDPC code are being decoded synchronously and in parallel. The decoding process control corresponds to the projected LDPC chart and can be shared through the Z copies. In this way, we describe the decoder as if it were operating on vector messages crossing the edges of vectors and being received by the vector nodes, each of the vectors Z having elements. Lace also becomes vectors. In particular, a vector node processor could comprise Z processors of Z nodes in parallel and, when a message vector is supplied, (m1, ..., mz) to the vector node processor, the message mi is supplied to the processor of order i. In this way, there is no routing or reordering of messages within the vector node processor, that is, the vector message is aligned with the processor vector in a fixed manner.

A deviation from the purely disjoint parallel execution of the projected Z graphics is that the messages are rearranged within a vector message during the message passing process. We refer to this reordering operation as a rotation. The rotation implements the permutation operations defined by Ψ. Due to the rotations, the processing paths of the Z copies of the mix of projected graphics therefore link them to form a single larger graph. The control information that specifies the rotations is needed in addition to the control information required for the projected graph. Fortunately, the rotation control information can be specified using relatively little memory.

Although various permutations can be used for rotations according to the present invention, the use of cyclic permutations is particularly interesting due to the ease with which such permutations can be implemented. For simplicity we will assume that Ψ includes the group of cyclic permutations. In this case, our large LDPC graphics are restricted to having an almost cyclic structure. For the purposes of this example, let N be the number of variable nodes in the graph and let M be the number of restriction nodes in the graph. First, we assume that both N and M are multiples of Z, N = nZ and M = mZ where Z denotes the order of the cycle.

Let's see that the nodes are doubly indexed. Thus, the variable node vi, j is the order variable node j of the order copy i of the projected graph. Since Ψ is the group of cyclic permutations, the variable node vi, j is connected to a restriction node Ca, b if and only if the variable node vi + k mod z, j is connected to the restriction node ca + k mod Z, b for k = 1,…, Z.

The techniques of the present invention for the representation of a large graph using a much smaller graph representation and the rotation information will now be further explained in reference to Figs. 10 to 16 which refer to the conversion to vectors of the graph. 600. The techniques described with reference to these figures can be applied to much larger LDPC graphics.

In accordance with the present invention, a larger graphic can be generated by replicating, ie, implementing multiple copies, of a small graphic shown in Fig. 6 and then performing rotation operations to interconnect the various copies of the replicated graphic. We refer to the small graph within the structure of the larger graph as the projected graph.

Fig. 10 is a graph 1000 illustrating the result of making 3 parallel copies of the small graph illustrated in Fig. 6. Variable nodes 602 ', 602' 'and 602' '' correspond to the graphs first until the third one, respectively, resulting from the realization of the three copies of the graph of Fig. 6. In addition, the check nodes 606 ', 606' 'and 606' '' correspond to the graphics first to the third, respectively, resulting from the making of all three copies. Note that there are no edges of nodes that connect nodes of one of the three graphics with the nodes of any other of the three graphics. Consequently, this copying process, which "elevates" the basic graphic by a factor of 3, results in three identical disjoint graphics.

Fig. 11 illustrates the result of the copying process discussed above using matrices 1102 and 1104. Note that to make the three copies of the original graphic each of the nonzero elements in matrix 702 is replaced with a 3x3 identity matrix . Thus, each in matrix 702 is replaced by a 3x3 matrix that has ones along the diagonal and zeros in the rest to produce matrix 1102. Note that matrix 1102 has 3 times the number of edges that It has the matrix 702, 12 edges for each of the three copies of the basic graph shown in Fig. 6. At this point, the variable xij corresponds to the node of variables Vij.

Fig. 12 shows the relationships between the 36 edges (3 x 12), the 15 variable nodes (3 x 5) and the 12 restriction nodes (3 x 4) that constitute graph 1000. As in the case of the Fig. 8, the edges are numbered from the side of the variable nodes.

For annotation purposes, the first number used to identify a node, constraint or edge indicates the copy of the graph to which the edge belongs, for example, the first, second or third copy of the graph. The second number is used to identify the item number within the particular specified copy of the basic graphic.

For example, in row 1202 'the value (1, 2) is used to indicate the edge 2 of the first copy of the graph while in row 1202' 'it is used (2,2) to indicate the edge 2 of the Second copy of the chart.

Note that the rows of edges 1202 ', 1202' ', 1202' '' are simply copies of row 804 representing three copies of the row of edges 804, shown in Fig. 8 which refer to the variable nodes . Similarly, the rows of edges 1204 ', 1204' 'and 124' '' represent three copies of the row of edges 804 'shown in Fig. 8 which refer to the restriction nodes.

Let us briefly discuss how to modify the decoder 900 of Fig. 9 to decode the Z = 3 parallel graphics now defined. The 908 node processor will become a vector node processor, capable of processing 3 identical nodes simultaneously in parallel. All outputs from node processor 908 will be converted to vectors, thus transporting 3 times the data previously transported. The hardware decision memory 912 and the edge message memory 906 will be made 3 times wider, each capable of writing or reading 3 units (bits or K bit messages respectively) in parallel using the address of a single SIMD instruction. The outputs from these memories will now be vectors, 3 times wider than before. The parity check verifier 914 and the output buffer 916 will also be suitably converted to vectors with all the processes set in parallel properly.

Consider now the introduction of rotations in our example. This can be illustrated by replacing each of the 3x3 identity matrices shown in Fig. 11 with 3x3 cyclic permutation matrices as shown in Fig. 13. Note that there are three possibilities for the cyclic permutation matrix used in Fig.

13. It is possible to indicate the particular permutation matrix to be replaced by an identity matrix indicating whether the permutation matrix has a "1" located in the first, second or third position in the first row of the permutation matrix. For example, in the case of matrix 1302, starting at the upper left and proceeding to the lower right corner (order of fittings of vector restrictions) the rotations could be specified by the sequence (2, 2, 3, 3 1 , 1, 1, 3, 2, 1, 2, 3).

Fig. 14 illustrates the effect of performing cyclic permutation (rotation) on the side of restriction nodes. As the permutation is carried out from the side of the restriction nodes, the relationship between the edges, for example, the ordering from the side of the variable nodes remains unchanged as shown in rows 1402 ', 1402' 'and 1402 '' ' From the side of the restrictions, however, the permutation results in fittings within a column, for example the edges within a specific vector edge, reordering as shown in rows 1404 ', 1404' ', 1404' ' '. This produces interconnections between nodes corresponding to different copies of the projected graph.

Consider, for example, column 1 of rows 1404 in relation to column 1 of rows 1104 of Fig. 11. Note that as a result of permutating operation of vector edges, restriction node C1,1 is now connected to the edge (2, 1) instead of the edge (1, 1), the restriction node C2,1 is coupled to the edge (3.1) instead of the edge (2,1) and the node of constraint C3,1 is coupled to the edge (1,1) instead of the edge (3,1).

We discussed earlier how to convert decoder 900 to vectors, or decode Z parallel copies of the projected graphic. By introducing commutations within the message paths to perform rotations, we decode the LDPC code defined in Fig. 13.

Figure 15 illustrates a decoder incorporating various features of the present invention. The decoder 1500 converts the decoder 600 into rotational vectors completely. Note that the figure indicates Z = 4 while our example has Z = 3, in general we can have any Z> 1 but in practice Z values will often be preferable in the form of 2k being k an integer. The similarities with the decoder 600 are evident. In particular, the control module of the decoder 1502 and the degree memory of the nodes 1510 function in the same or similar manner as their respective counterparts 902 and 910 in the decoder 900. For example, to decode the LDPC code defined in Fig. 13 and 14 the operation of these components would be exactly the same as that of their counterparts in decoder 900 when the example graphic is decoded

600. Edge message memory 1506 and hardware decision memory 1512 are versions converted to vectors of their counterparts 906 and 912 in decoder 900. While in decoder 900 memories stored single units (bits or k-bit messages) ) the corresponding memories in the decoder 1500 store sets, ie vectors, messages, resulting in, for example, messages of ZxK bits stored. These vectors are written or read as single units using SIMD instructions. In this way the message identifiers sent to these modules from the message ordering module 1504 are equivalent or similar to those of the decoder 900. The message ordering module 1504 has the additional role, beyond that of its counterpart 904 in the decoder 900, for storing and providing the permutation information, for example, of rotation. Recall that in the decoding example 600, the decoder 900 stored the sequence of edges in its message order module 904 (1, 4, 7, 2, 9, 11, 3, 5, 12, 6, 8, 10) . We consider using the decoder 1500, to decode the code of Figs. 13 and 14. The message sorting module 1504 would store the same sequence above for message vector access during the processing of the restriction nodes, and also store the sequence (2, 2, 3, 3, 1, 1, 1, 3, 2, 1, 2, 3) that describes the rotations associated with the same sequence of vector messages. This sequence serves as the basis for generating the decay signal that is used by message ordering module 1504 to cause switches 1520 and 1522 to rotate vector messages and vector hardware decision bits respectively. (Note that hardware decision bits are provided only during variable node processing mode). The vector parity check verifier 1514 is a vector version of its counterpart 914 in the decoder 900. Note that the convergence signal is a scalar, as before. The output buffer 1516 serves the same purpose as the buffer 916, but the output data is written as vectors. The vector node processor 1508, is for example like Z node processors, each as in 908, in parallel. These nodes would share the degree signals and the C / V control signal of the control module of the decoder 1502.

To facilitate the ability to make decisions from the decoder either software or hardware generated by the variable processing unit are supplied to a software decision input of the buffer 1516. Thus, at any time prior to the termination of the decoding, software decisions can be obtained from the output of buffer 1516.

We further consider how decoder 1500 would work by decoding the example of Figs. 13 and 14. Initially the edge message memory 1506 is populated with zeros. The decoder control module 1502 first swings to the mode of processing variable nodes. The vectors of the edge message memory 1506 (all zeros at this point) are read in order and supplied to the vector node processor 1508 for the processing of the variable nodes. The vector node processor 1508 then takes out the values received alone, along each edge from a variable node, we will use and to denote these first messages to indicate this. Thus, the outgoing vectors would be (y1, i, y2, i, y3, i) for i = 1, ..., 12 in increasing order. The decay signal is used to control the reordering of the control messages performed by the switching circuits 1520, 1522. The decay signal of the message ordering module 1504 will cause the messages in the vectors to rotate to produce processed vectors as follows. : (y2.1, y3.1, y1.1), (y3.2, y1.2, y2.2), (y1.3, y2.3, y3.3), (y2.4, y3, 4, y1.4), (y3.5, y1.5, y2.5), (y1.6, y2.6, y3.6), (y3.7, y1.7, y2.7), ( y2.8, y3.8, y1.8), (y1.9, y2.9, y3.9), (y3.10, y1.10, y2.10), (y1.11, y2.11, y3,11), (y2,12, y3,12, y1,12). Once the vectors processed within the edge memory 1506 have been written, in the order indicated, the control module of the decoder 1502 will tilt to the constraint mode. The vector messages stored below will be read in order (1, 4, 7, 2, 9, 11, 3, 5, 12, 6, 8, 10). In this way they will be presented to the vector node processor 1508 in the order (y2.1, y3.1, y1.1), (y2.4, y3.4, y1.4), (y3.7, y1, 7, y2.7), (y3.2, y1.2, y2.2), (y1.9, y2.9, y3.9), (y1.11, y2.11, y3.11), ( y1.3, y2.3, y3.3), (y3.5, y1.5, y2.5), (y2.12, y3.12, y1.12) (y1.6, y2.6, y3 , 6), (y2,8, y3,8, 1,8), (y3,10, y1,10, y2,10). The vector node processor 1508 is implemented as three node processors (Z = 3) in parallel. The first element (message) of each message vector (message set) is supplied to the first node processor, the second message is supplied to the second processor, and the third message is supplied to the third processor, respectively. The degree signal, which indicates the degree of the current node being processed, is supplied by the 1510 degree memory to the three parallel processors of the 1508 vector node processor. At this point the degree signal indicates that the restrictions they are all grade 3 so that the first processor would process y2.1, y2.4, and y3.7 for its first restriction node and y3.2, y1.9, and y1.11 for its second restriction node. Similarly, the second processor would process y3.1, y3.4, and y1.7 for its first restriction node e y1.2, y2.9 and y2.11 for its second.

Let me be, j the outgoing message corresponding to the incoming yi, j. As the vectors emerge from the vector node processor 1508, the decay signal for the switch 1520 will cause the vectors to be rearranged so that the previous rotation is reversed, thus reaching edge memory as (m1, j, m2, j, m3, j), in the order j = 1, 4, 7, 2, 9, 11, 3, 5, 12, 6, 8, 10. The messages are written back into the memory of according to the order of the message identifier with which they were read, so that after writing they appear in the memory as (m1, j, m2, j, m3, j) in the order j = 1, ..., 12. The Message reordering module 1504 now scales within the variable node processing mode in response to the C / V signal supplied by the

5 decoder control module 1502. The message vectors are then read in order j = 1,…, 12 and supplied to the vector node processor 1508 for the processing of the variable nodes. This completes an iteration.

During the processing of the variable nodes, the vector node processor 1508 also outputs decoded software vectors that are stored in the output buffer 1516. It also outputs 10 hardware decisions that are supplied to the switching circuit 1522. The decision vectors One-bit hardware undergo the same rotation operation as the message vectors at the corresponding instants. The rotated hardware decision vectors produced by the switching circuit 1522 are then arranged in the hardware decision memory 1512 where they are stored. As a result of the application of the same rotation applied to the message vectors, the hardware decisions can be read in the same order that the vector messages are read during the processing of the restriction nodes. During the processing of the restriction nodes, the hardware decisions are supplied to the vector parity check verifier 1514 which performs Z parity checks in parallel. If all parity checks are satisfied, then the convergence signal, CON is generated and emitted. In response to the reception of the convergence signal indicating the decoding satisfactory, the control module of the decoder 1502 for the

20 decoding process.

It will be apparent that there are many variations for the decoder 1500 than each of the embodiments of the current invention. For example, the switch 1520 could have instead been located along the data path between the edge message memory 1506 and the vector node processor 1508. Similarly, the switch 1522 could have instead been located at along the data path between the hardware decision memory 1512 and the vector parity check verifier 1514. Such substitution would also involve the appropriate timing adjustment of the decay signal. The hardware decision memory 1512, the vector parity check verifier 1514 and the accompanying data paths do not need to be used and are deleted for decoder embodiments that perform a fixed number of iterations and therefore do not require convergence detection. Many additional variations will be apparent to specialists in

The technique in view of the present invention.

Fig. 16 illustrates a decoder 1600 that is implemented in accordance with another embodiment of the present invention. The decoder 1600 includes many elements that are the same, or similar to the elements of the decoder 1500. Therefore, for the purpose of brevity, such elements will be identified using the same reference numbers as those used in Fig. 15 and not They will be treated again in detail. The decoder 1600 is capable of performing both the processing operations of variable nodes and restriction nodes, for example, message update operations, at the same time, that is, simultaneously and independently. In contrast to Fig. 15, the implementation of the decoder that can be described as a side-by-side decoder due to the way in which it alternates between the processing iterations of the variable nodes and the restriction nodes, the decoder 1600 can be described as an asynchronous iteration decoder since the

40 processing operations of variable nodes and restriction nodes can be performed independently, for example, simultaneously.

The decoder circuit 1600 includes a decoder control module 1602, a message order module 1604, a first switching circuit 1621, an edge message memory V2C 1606, a vector processor of restriction nodes (eg, Z restriction node processors in

45 parallel) 1609, a second switching circuit 1620, the edge message memory C2V 1607, a vector processor of variable nodes 1608 (for example, Z parallel variable node processors), a hardware decision memory 1612 , and a third switch 1622 coupled together as illustrated in Fig. 16.

Various embodiments of individual restriction node processors and node node processors

50 individual variables, Z of which can be used in parallel to implement the restriction node vector processor 1609 and the variable node processor 1608, respectively, are described in US Provisional Patent Application 60 / 328,469, entitled "Node Processors For Use in Parity Check Decoders", which was filed on October 10, 2001. The inventors of the present patent application are also the named inventors of the provisional patent application

55 built-in.

To support independent and / or parallel update of constraint and variable messages in the embodiment of Fig. 16, separate edge message memories 1606, 1607 and switching circuits 1620, 1621 are used to support node processing operations of constraints and variable nodes, respectively. As in the embodiment of Fig. 15, each of the message memories 1606, 1607 are capable of storing L (ZxK bits) vector messages. Each of the vector messages, for example, the columns of Z messages of K bits, in memories 1606, 1607 can be read or written in a simple read or write operation.

Edge message memory V2C 1606 is used to store V2C messages and therefore has a write input coupled to the output of switching circuit 1621 that receives data from the variable node vector processor 1608. Message memory C2V 1607 is used to store C2V edge messages and therefore has a write input coupled to the output of the restriction node vector processor 1609.

Switches 1620 and 1621 are used to couple the variable node vector processor 1608 to the input of the edge message memory V2C and the output of the edge message memory C2V, respectively. In a particular embodiment, message vectors are stored in the order of the vector constraints. The message vectors are written into the edge message memory C2V 1607 and read from the edge message memory V2C 1606 in the order of the vector restriction fittings, that is, linearly, in this way it is not required no external control (the output of edge indexes from the control module of decoder 1602 passes through the message order module 1604 without changes to its output of index of edge restrictions). Message vectors are read from edge message memory C2V 1607 and are written into edge message memory V2C 1606 in the order of vector variable fittings. The message ordering module 1604 generates the signal of indexes of edges of variables indicated by this ordering. Note that this signal controls the reading of the edge message memory of C2V 1607 and is supplied to the edge message memory V2C 106 after being delayed. The delay accounts for the time required for processing performed by switches 1620 and 1621 and the vector variable node processor 1608. This delay may be a function of the degree of node being processed, as indicated in Fig. 16 by the degree signal of the variable nodes.

To avoid the delays of simultaneous execution of the processing due to variable delays, both restriction and variable nodes are ordered so that the nodes of the same degree are processed in a contiguous manner. An additional reduction of the simultaneous execution delays that occur at the border of groups of nodes with different degrees can be achieved by classifying the groups of nodes by the degree of a monotonous form, for example, by increasing or decreasing the order of the degree. For simplicity of implementation, embodiments 900, 1500 and 1600 assume increasing the order of grade.

In the particular embodiment illustrated in Fig. 16 the vectors are stored in the order of rotation of the vector constraints. The switch 1620 rotates the messages in each of the vectors in a variable rotation as each of the vector messages C2V proceeds to the vector processor of variable nodes 1608 and then the switch 1621 applies the reverse rotation to the vector message Outgoing V2C corresponding to the same vector edge. The decay signal supplied to the switch 1620 is supplied to the switch 1621 through the rotation reversing circuit 1624 after a delay equal to the processing time in the vector restriction node processor. This delay may depend on the degree of the restriction nodes, as indicated by the output of the degree signal of the restriction nodes by the 1610 degree memory.

The decoder 1600 includes a decoder control module 1602. The decoder control module operates similarly to the control module discussed above 1502. However, in 1602 no C / V control signal is generated. The edge index generation function can be provided by a counter that circulates through the whole set of vector edges before starting over.

In addition to making the software decisions, hardware decisions are generated, one per edge, for each of the Z variable node processing units in the vector variable node processor 1608 each time a vector V2C message is generated. While vector messages are written into the edge message memory V2C 1606, the hardware decision outputs of Z x 1 bit are written into the hardware decision output memory 1612 after being rotated by the switch 1622. The Switch 1622 and hardware decision memory 1612 operate under the same control signals as Switch 1621 and edge message memory V2C 1606, respectively.

The rotated vectors resulting from Z x 1 are supplied to the vector parity check verifier 1614 which includes Z parity check verifiers connected in parallel. Verifier 1614 determines whether parity checks are satisfied and if all are satisfied then a convergence signal is generated and sent to the control module of the decoder. In response to the reception of the signal indicating convergence, the control module of the decoder for decoding the received code word. In embodiment 1600 the convergence detection signal is available one iteration after a code word has been written in the output buffer since the verification of restrictions for the data from the iteration N is done during the iteration N + 1 and the convergence signal is available after the termination of the N + 1 iteration.

In the decoder 1600 which employs different convergence detection circuitry, Fig. 17 illustrates a similar embodiment for the decoder 1700, the constraint verification is carried out "on the fly" as the output values X of ZxK bits are written in the output buffer 1716. In this case the memory block 1712 follows the state of the restrictions as vector restrictions are updated by the hardware decision output from the variable node processor 1708. Each of the locations of Restriction status memory corresponds to a restriction of checking the parity of the code word. In the last update of any restriction status location, these parity check values are verified. If all verifications are satisfied during iteration N then a convergence signal will be generated and output by vector parity check verifier 1714 immediately after iteration N. This will qualify for decoder control module 1702 that the data in the output buffer 1716 are valid. In the embodiment of Fig. 17, the message rearrangement module 1704 generates an additional signal that defines the index of restriction nodes (as opposed to the edge index) that is not generated in the embodiment of Fig. 16. The Restriction node index defines the destination of the restriction nodes of the current V2C message. This field serves as an index for restriction status memory 1712 to which it is supplied.

Although they require a little more circuitry than the embodiment of Fig. 15, the embodiments of Fig. 16 and Fig. 17 have the advantage of more efficient use of the processors of the restriction vector nodes and variables 1609 / 1709, 1608/1708 since both vector node processors are fully utilized during each of the processing iterations. In addition, the decoding time is reduced compared to the embodiment of Fig. 15 since the processing of the restriction and variable nodes is carried out in parallel, for example simultaneously.

The decoding procedures described above allow decoding of message passing, for example LDPC decoding using general purpose software and computers capable of supporting SIMD operations. In such embodiments, one or more parallel processors serve as vector processing units, or hardware can be used within a single processor to perform processing operations of multiple vectors in parallel. In such embodiments, edge memory, permutations map and information on the number of messages per node can all be stored in a common memory, for example the main memory of the computers. The message passing control logic and the decoder control logic can be implemented as software routines executed on the computer processing unit. In addition, the switching device can be implemented using software and one or more SIMD processing instructions.

The LDPC decoding procedures described above allow the realization of LDPC decoding on various hardware platforms such as Field Programmable Door Arrangements or in a Specific Application Integrated Circuit. The present invention is especially useful in these configurations where simple parallelism can be explicitly exploited.

Numerous additional variations on the decoding procedures and apparatus of the present invention will be apparent to those skilled in the art in view of the foregoing description of the invention. Such variations will be considered within the scope of the invention as defined by the appended claims.

Claims (29)

one.

 An apparatus (1500, 1600, 1700) for performing message step decoding operations using LDPC graphics converted to vectors that represent high parity check matrices so that, in a high parity check matrix the zero elements of a parity check matrix H of a projected LDPC code is replaced with matrices of Z x Z zeros and elements 1 of the parity check matrix H are replaced with permutation matrices of Z x Z comprising the apparatus:

a memory (1506) including a set of memory locations for storing L sets of Z messages of K bits, where Z is a positive integer greater than one and K and L are positive integers other than zero; a node vector processor (1508) including Z parallel node processing units, each of the node processing units (1508) to perform at least one of the restriction node processing operations and a processing operation of variable nodes; and a switching device (1520) coupled to memory (1506) and to the node vector processor (1508), the switching device (1520) for passing sets of Z messages of K bits, passing each set of Z messages of K bits in parallel between said memory and said node vector processor and to reorder the messages in at least one of said message sets in response to the switching control information, a message order module (1504) coupled to said switching device for generating said switching control information used to control the reordering of messages in said at least one set of messages, in which the message reordering module (1504) is further coupled to said memory and generates sequentially sets of indicators, each of the set identifiers controlling the memory to access the memory locations corresponding to one of said sets of messages in a single read or write operation whereby one of said sets of Z messages of K bits is written or read as a single unit accessing all Z messages of said set using a SIMD instruction.

2.

 The apparatus (1500) of claim 1, wherein the switching device (1520) includes circuitry to perform a message rotation operation to reorder the messages included in a set of messages.

3.

 The apparatus (1500) of claim 1, wherein the message reordering module (1504) stores information about the order of the sets of the messages to be read from memory and the information indicating which message reordering will be performed by said switch on the individual sets of messages read from memory.

Four.

 The apparatus (1500) of claim 1, wherein said set identifier is a simple memory address.

5.

 The apparatus (1500) of claim 1, wherein said plurality of node processing units includes Z node processing units arranged in parallel, each of the Z node processing units running in parallel to process a different message in each of the sets of Z messages passed between said memory and said node processor.

6.

 The apparatus (1500) of claim 5, wherein said memory (1506) includes an address entry that allows each of the message sets to be addressed as a unit thereby enabling the reading of a set of messages from said memory in a single SMID read operation.

7.

 The apparatus of claim 5, wherein said memory (1506) includes an address entry that allows each of the message sets to be addressed as said unit thereby enabling a set of messages to be written into said memory in a single SMID write operation.

8.

 The apparatus (1500) of claim 5,

wherein the decoder control device is further coupled to a message passing control device; and in which the message passing control device specifies a different order in which each of the L sets of Z messages will be read from memory during the mode of variable nodes of the processing operation than during the mode of processing. restriction nodes of the processing operation.

9.

 The apparatus (1500) of claim 1, further comprising a decoder control module (1502) coupled to the message order module (1504), including the decoder control module means for supplying information to the ordering module of messages used to control the order in which each of the L sets of Z messages in that memory will be read.

10.

 The apparatus (1500) of claim 9, wherein the decoder control module (1502) further includes

means for supplying an edge index to the message ordering module (1504) that controls the generation of the set identifiers supplied to said memory.

eleven.

 The apparatus (1500) of claim 10, further comprising a degree memory (1510) coupled with the node vector processor (1508) for storing a set of information on the degree of the nodes.

12.

 The apparatus (1500) of claim 11, wherein the control module (1502) further generates an index of nodes used to determine what information of the degree of the nodes in the stored set of information of the degree of the nodes will be applied to the node vector processor at any given time.

13.

 The apparatus (1600) of claim 1, further comprising:

a second node vector processor (1609, 1608) coupled to said memory, including the second node vector processor node processing units, each of the node processing units to perform a restriction node processing operation , wherein said node vector processor is a variable node processor for performing the parity check processing operations of the variable node decoder; wherein said second node processor is a restriction node processor (1609) for carrying out the processing operations of the check box of the parity of restriction nodes.

14.

 The apparatus (1600) of claim 13, further comprising:

the additional memory (1607, 1606) that couples said node vector processor to said second node vector processor, the additional memory including a set of memory locations for storing L sets of Z messages of K bits.

fifteen.

 The apparatus (1600) of claim 14, further comprising:

a second switching device (1620, 1621) that couples said node vector processor to said additional memory, a second switching device for passing sets of Z K bit messages between said node vector processor and said additional memory and for reorder the messages in at least one of the message sets passed by the second switch.

16.

 The apparatus (1600) of claim 13, further comprising:

a parity check verifier (1614), coupled to said node vector processor, to determine from an output of each of the processing units included therein, when the check decoding operation has been successfully completed of parity

17.

 A procedure for performing the decoding processing of the message passing for decoding LDPC graphics converted to vectors representing high parity check matrices so that in a high parity check matrix, the zero elements of a matrix of parity check H of a projected LDPC code is replaced with matrices of Z x Z zeros and elements 1 of the parity check matrix H are replaced with permutation matrices of Z x Z comprising the steps of:

storing L sets of K bit messages in a memory (1506), including each of the K bit message sets first Z messages, where Z is a positive integer greater than one and K and L are positive integers nonzero; read one of said sets of K-bit messages from memory (1506); performing a message reordering operation on said set of K bit messages read to produce a rearranged set of Z messages of K bits; supply, in parallel, the Z messages in the reordered set of messages to a node vector processor (1508); and that the node vector processor (1508) operates to perform the message passing decoder operations using Z messages supplied as input, including said node vector processor (1508) Z parallel processing units, whereby each one of the node processing units performs at least one restriction node processing operation and one variable node processing operation, the procedure further comprising: generating a set identifier indicating the set of Z messages to be read from memory (1506), in which the step of reading one of said K bit message sets includes: performing a single read operation using said set identifier to access with said unique read operation all Z messages of said set as a single unit using a SMID instruction.

18.

 The method of claim 17, wherein said message step decoder operations generate a set of Z decoder messages from the Z messages in the set of rearranged messages supplied.

19.

 The method of claim 17, further comprising:

Perform a second message reordering operation, the second message reordering operation being performed on the generated set of Z messages of the decoder to produce a rearranged set of generated decoder messages.

twenty.

 The method of claim 19, further comprising:

storing the reordered set of decoder messages generated in said memory.

twenty-one.

The method of claim 20, wherein the step of storing the reordered set of generated decoder messages includes performing a SMID write operation to write said reordered set of decoder messages generated in memory.

22

 The method of claim 19, wherein the step of performing a second message reordering operation includes performing the inverse of the message reordering operation performed on said set of K bit messages read from memory.

2. 3.

 The method of claim 17, further comprising:

access the permutation information of the set of stored messages; Y in which the stage of carrying out a message reordering operation includes the stage of: perform said reordering as a function of the permutation information of the message set stored accessed.

24.

 The method of claim 22, wherein said message set permutation information includes cyclic rotation information.

25.

 The method of claim 17, wherein said message passing decoder operations are variable node processing operations, each of the variable node processing operations including a decision value, and wherein the procedure It also includes:

examine the decision values generated by operating the vector processor to determine if a decoding condition has been satisfied.

26.

 A method of performing the message passing decoder processing to decode the LDPC graphics converted to vectors representing the high parity check matrices so that in a high parity check matrix, the zero elements of a check check matrix parity H of a projected LDPC code is replaced with matrices of Z x Z zeros and elements 1 of the parity check matrix H are replaced with permutation matrices of Z x Z, the procedure comprising the steps of:

operate a node vector processor (1508) to generate a set of Z K-bit messages, to be stored in a memory device (1506) to store L sets of Z K-bit messages, where Z is a larger positive integer of one and K and L are non-zero positive integers, said node vector processor (1508) Z parallel processing units, whereby each of the node processing units performs at least one of the operations of restriction node processing and a variable node processing operation; perform a message reordering operation on the generated set of Z K bit messages to produce a reordered set of Z K bit messages; performing a single write operation to store the rearranged set of Z messages of K bits in said memory device (1506), in which the step of performing a single write operation to store the set of Z messages of K bits reordered comprises perform a single write operation using a set identifier to write with said single write operation all Z messages of said reordered set as a single using a SIMD instruction.

27.

 The method of claim 26, wherein the step of operating the node vector processor to generate a set of Z messages of K bits, includes the step of:

Perform, in parallel, the Z node processing operations, each of the node processing operations generating a message in said set of Z K-bit messages.

28.

 The method of claim 26, wherein the Z node processing operations are variable node processing operations.

29.

 The method of claim 28, wherein the Z node processing operations are restriction node processing operations.

The method of claim 28, wherein performing a message reordering operation in the generated set of Z K bit messages includes: rotate the messages in the set of Z messages of K bits performing a switching operation to reorder the messages in the message set. 10