EP3320428A4 - Processor with efficient memory access - Google Patents

Processor with efficient memory access Download PDF

Info

Publication number
EP3320428A4
EP3320428A4 EP16820923.7A EP16820923A EP3320428A4 EP 3320428 A4 EP3320428 A4 EP 3320428A4 EP 16820923 A EP16820923 A EP 16820923A EP 3320428 A4 EP3320428 A4 EP 3320428A4
Authority
EP
European Patent Office
Prior art keywords
processor
memory access
efficient memory
efficient
access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP16820923.7A
Other languages
German (de)
French (fr)
Other versions
EP3320428A1 (en
Inventor
Noam Mizrahi
Jonathan Friedmann
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Centipede Semi Ltd
Original Assignee
Centipede Semi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US14/794,835 external-priority patent/US10185561B2/en
Priority claimed from US14/794,837 external-priority patent/US9575897B2/en
Priority claimed from US14/794,853 external-priority patent/US20170010973A1/en
Priority claimed from US14/794,841 external-priority patent/US20170010972A1/en
Application filed by Centipede Semi Ltd filed Critical Centipede Semi Ltd
Publication of EP3320428A1 publication Critical patent/EP3320428A1/en
Publication of EP3320428A4 publication Critical patent/EP3320428A4/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching
    • G06F9/3832—Value prediction for operands; operand history buffers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/35—Indirect addressing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3826—Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3834—Maintaining memory consistency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G06F9/384—Register renaming

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)
EP16820923.7A 2015-07-09 2016-07-04 Processor with efficient memory access Withdrawn EP3320428A4 (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US14/794,835 US10185561B2 (en) 2015-07-09 2015-07-09 Processor with efficient memory access
US14/794,837 US9575897B2 (en) 2015-07-09 2015-07-09 Processor with efficient processing of recurring load instructions from nearby memory addresses
US14/794,853 US20170010973A1 (en) 2015-07-09 2015-07-09 Processor with efficient processing of load-store instruction pairs
US14/794,841 US20170010972A1 (en) 2015-07-09 2015-07-09 Processor with efficient processing of recurring load instructions
PCT/IB2016/053999 WO2017006235A1 (en) 2015-07-09 2016-07-04 Processor with efficient memory access

Publications (2)

Publication Number Publication Date
EP3320428A1 EP3320428A1 (en) 2018-05-16
EP3320428A4 true EP3320428A4 (en) 2019-07-17

Family

ID=57685264

Family Applications (1)

Application Number Title Priority Date Filing Date
EP16820923.7A Withdrawn EP3320428A4 (en) 2015-07-09 2016-07-04 Processor with efficient memory access

Country Status (3)

Country Link
EP (1) EP3320428A4 (en)
CN (1) CN107710153B (en)
WO (1) WO2017006235A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11249723B2 (en) * 2020-04-02 2022-02-15 Micron Technology, Inc. Posit tensor processing

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005111794A1 (en) * 2004-05-05 2005-11-24 Advanced Micro Devices, Inc. System and method for validating a memory file that links speculative results of load operations to register values
US20140208039A1 (en) * 2013-01-21 2014-07-24 Qualcomm Incorporated Methods and apparatus to reduce cache pollution casued by data prefetching
GB2519644A (en) * 2013-10-24 2015-04-29 Advanced Risc Mach Ltd Prefetch strategy control

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5911057A (en) * 1995-12-19 1999-06-08 Texas Instruments Incorporated Superscalar microprocessor having combined register and memory renaming circuits, systems, and methods
US5926832A (en) * 1996-09-26 1999-07-20 Transmeta Corporation Method and apparatus for aliasing memory data in an advanced microprocessor
JP3841810B2 (en) * 2002-09-30 2006-11-08 株式会社ルネサステクノロジ Data processor
US7024537B2 (en) * 2003-01-21 2006-04-04 Advanced Micro Devices, Inc. Data speculation based on addressing patterns identifying dual-purpose register
US8452946B2 (en) * 2009-12-17 2013-05-28 Intel Corporation Methods and apparatuses for efficient load processing using buffers
US8850166B2 (en) * 2010-02-18 2014-09-30 International Business Machines Corporation Load pair disjoint facility and instruction therefore
US20140189249A1 (en) * 2012-12-28 2014-07-03 Futurewei Technologies, Inc. Software and Hardware Coordinated Prefetch
CN104252425B (en) * 2013-06-28 2017-07-28 华为技术有限公司 The management method and processor of a kind of instruction buffer
US20150134933A1 (en) * 2013-11-14 2015-05-14 Arm Limited Adaptive prefetching in a data processing apparatus

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005111794A1 (en) * 2004-05-05 2005-11-24 Advanced Micro Devices, Inc. System and method for validating a memory file that links speculative results of load operations to register values
US20140208039A1 (en) * 2013-01-21 2014-07-24 Qualcomm Incorporated Methods and apparatus to reduce cache pollution casued by data prefetching
GB2519644A (en) * 2013-10-24 2015-04-29 Advanced Risc Mach Ltd Prefetch strategy control

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO2017006235A1 *

Also Published As

Publication number Publication date
CN107710153A (en) 2018-02-16
EP3320428A1 (en) 2018-05-16
CN107710153B (en) 2022-03-01
WO2017006235A1 (en) 2017-01-12

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