EP3135010A1 - Short-range zigbee compatible receiver with near-threshold digital baseband - Google Patents
Short-range zigbee compatible receiver with near-threshold digital basebandInfo
- Publication number
- EP3135010A1 EP3135010A1 EP15782751.0A EP15782751A EP3135010A1 EP 3135010 A1 EP3135010 A1 EP 3135010A1 EP 15782751 A EP15782751 A EP 15782751A EP 3135010 A1 EP3135010 A1 EP 3135010A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- sampling rate
- receiver
- quality
- digital baseband
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
- H04B1/707—Spread spectrum techniques using direct sequence modulation
- H04B1/7073—Synchronisation aspects
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
- H04L25/40—Transmitting circuits; Receiving circuits
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W24/00—Supervisory, monitoring or testing arrangements
- H04W24/02—Arrangements for optimising operational condition
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W4/00—Services specially adapted for wireless communication networks; Facilities therefor
- H04W4/80—Services using short range communication, e.g. near-field communication [NFC], radio-frequency identification [RFID] or low energy communication
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W52/00—Power management, e.g. TPC [Transmission Power Control], power saving or power classes
- H04W52/02—Power saving arrangements
- H04W52/0209—Power saving arrangements in terminal devices
- H04W52/0225—Power saving arrangements in terminal devices using monitoring of external events, e.g. the presence of a signal
- H04W52/0245—Power saving arrangements in terminal devices using monitoring of external events, e.g. the presence of a signal according to signal strength
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W52/00—Power management, e.g. TPC [Transmission Power Control], power saving or power classes
- H04W52/02—Power saving arrangements
- H04W52/0209—Power saving arrangements in terminal devices
- H04W52/0261—Power saving arrangements in terminal devices managing power supply demand, e.g. depending on battery level
- H04W52/0274—Power saving arrangements in terminal devices managing power supply demand, e.g. depending on battery level by switching on or off the equipment or parts thereof
- H04W52/028—Power saving arrangements in terminal devices managing power supply demand, e.g. depending on battery level by switching on or off the equipment or parts thereof switching on or off only a part of the equipment circuit blocks
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
- H04B1/707—Spread spectrum techniques using direct sequence modulation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W24/00—Supervisory, monitoring or testing arrangements
- H04W24/08—Testing, supervising or monitoring using real traffic
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Definitions
- the present disclosure relates to a short-range wireless receiver with near-threshold digital baseband.
- the sensor density around a person is expected to increase from a few hundreds to thousands, which will correspond to roughly a trillion networked sensors on the planet.
- the microsystems encompassing these sensors will have to have high-energy efficiency for computation, communication and sensing operations. This is mainly because many of these microsystems are expected to operate at the edge of the cloud with a battery lifetime of 10+ years, or batteryless operation from harvested energy. This poses new design challenges and opportunities for circuit designers and especially for wireless communication Integrated Circuits (ICs) as they consume a significant amount of power when active in a miniaturized microsystem.
- ICs Integrated Circuits
- This disclosure presents a fully integrated 2.4 GHz receiver comprising an RF front-end, analog-to-digital converter (ADCs), and digital baseband processor (DBB) that exploit the relationship of sensitivity and power consumption by adapting the sampling and processing rates of signals in the radio baseband processor.
- ADCs analog-to-digital converter
- DBB digital baseband processor
- this receiver provides a short-range O-QPSK DSSS link that is fully compatible with IEEE 802.15.4 packets. While reference is made throughout this disclosure to a particular standard, it is readily understood that the concepts described herein are applicable more generally to short-range wireless receivers.
- a method for operating a short-range receiver with a digital baseband processor includes: receiving a network data packet over a data link of a wireless network; sampling a portion of the network data packet (e.g., header) at a given sampling rate (e.g., Nyquist rate); determining a metric indicative of quality of the data link over which the network data packet was received; lowering the given sampling rate of the network data packet to a reduced sampling rate, where the reduced sampling rate is set inversely to quality of the data link and with a value lower than the given sampling rate; and processing remainder of the network data packet at the reduced sampling rate.
- a sampling rate e.g., Nyquist rate
- the metric is compared to a threshold, the given sampling rate is reduced to the reduced sampling rate and the remainder of the network data packet is processed when the metric is above a threshold; whereas, the remainder of the data unit is processed at the given sampling rate when the metric is below the threshold.
- Lowering the given sampling rate may be implemented by disabling one of the digital baseband process, an analog-to-digital converter or another active circuit in the receiver for a period of time within the sampling interval.
- lowering the given sampling rate includes ranking samples from the portion of the network data packet according to energy level; selecting a subset of the samples having highest energy level, where the number of selected samples correlates to the reduced sampling rate; and sampling the remainder of the network data packet in accordance with the selected subset of samples.
- the metric indicative of quality of the data link may be selected from a group comprised of a signal-to-noise ratio, a received signal strength index and a link quality indicator.
- the method for operating a short-range receiver can be further defined as follows.
- the method includes: receiving, by the receiver, a protocol data unit over a channel in a wireless network; sampling, by the receiver, a portion of the data unit at a given sampling rate; determining, by the receiver, a metric indicative of quality the channel over which the data unit was received; comparing, by the receiver, the metric to a threshold; processing the remainder of the data unit at a reduced sampling rate when the metric is above the threshold; and processing the remainder of the data unit at the given sampling rate when the metric is below the threshold.
- Processing of the data unit further includes ranking samples from the portion of the data unit according to energy level; selecting a subset of the samples having highest energy level, where the number of selected samples correlates to the reduced sampling rate; and sampling the remainder of the network data packet in accordance with the selected subset of samples.
- a short-range receiver includes: an RF front-end circuit, and analog-to-digital converter and a digital baseband processor.
- the RF front-end circuit is configured to receive an RF analog signal from an antenna and operates to shift the RF analog signal to an intermediate signal having a different frequency.
- the analog-to-digital converter is configured to receive the intermediate signal from the RF front-end circuit and convert the intermediate signal to a digital signal.
- the digital baseband processor is configured to receive the digital signal from the analog-to-digital converter and processes the digital signal at a prescribed sampling rate.
- the baseband processor includes a link quality module that determines a metric indicative of quality of data link over which the RF analog signal was received and set the prescribed sampling rate to a value that is inversely related to the quality of the data link; and a decoder that samples the digital signal at the prescribed sampling rate and outputs a sequence of data bits derived from the digital signal.
- Figure 1 is a diagram showing a signal propagation through a generic radio front-end
- Figure 2 is a graph showing theoretical noise figures vs. power tradeoff in an LNA
- Figure 3 is a graph showing theoretical short-channel NFET linearity vs. power tradeoff in 65 nm CMOS;
- Figure 4 is a flowchart illustrating a proposed adaptive sampling technique
- Figure 5 is a diagram further illustrating the adaptive sampling technique
- Figure 6 is a graph depicting a simulated probability of chip error rate
- Figure 7 is system block diagram of 2.4 GHz O-QPSK DSSS receiver with near-threshold digital baseband
- Figure 8 is graph showing a simulated Matlab model for flash
- Figure 9 is a block diagram of a simplified digital baseband implementing adaptive signal processing
- Figure 10 is a schematic of an example RF front-end circuit
- Figures 1 1 A-1 1 D are schematics of a buffer driving ADC circuit, comparator circuit, reference ladder circuit and SR latch circuit, respectively;
- Figures 12A-12C are graphs showing the transmitted O- QPSK data on I channel, the down converted baseband signal at the output of the PGA and the flash ADC output for I channel for a -40 dBm RF input signal;
- Figures 13A-13D are graphs showing measured gain, NF, IIP3, IIP2, of the receiver front-end and flash ADC spectrum, respectively;
- Figure 14 is a graph showing measured received RF packets compliant with the IEEE 802.15.4 packet format, each packet is of duration 2ms;
- Figures 15A-15D are graphs showing measured energy per bit profile along with simulated energy efficiency breakdown of the radio, Bit Error Rate and the radar plot of the system, respectively;
- Figure 16 is a graph showing measured S1 1 (without impedance matching) at the RF input.
- NF Receive Noise Figure
- PLNA is the power consumed by a low-noise amplifier and a is the proportionality constant that depends on the given technology and the circuit topology.
- Figure 2 plots the Noise Figure (1 0log 10 F) from (1 ) for an LNA designed in 90 nm CMOS, which consumes 3 mW power and achieves a NF of 3 dB.
- a similar relationship between noise and power is expected for an LNA implemented in 65 nm CMOS and in fact for any signal-processing element trying to optimize noise and power.
- the rate of change of n o i se f i g u re with respect to power is decreasing (decreasing gradient) suggesting lower returns in noise figure for increasing power.
- the overall linearity of the RF front-end is dictated by the baseband gain stages.
- a three-point method is adopted to estimate the linearity of a short-channel NFET in 65 nm CMOS.
- IIP2 IIP3 are the second and third order input intercept points respectively
- g is the incremental device gain evaluated at three input voltages 0, V and -V
- Rs is the source resistance.
- the incremental gain of a short- channel MOSFET is given by,
- V od is the over-drive voltage and p takes velocity saturation into account.
- the V od depends only on the current density therefore both IIP3 and IIP2 are plotted vs. current density, to estimate power in 65 nm CMOS as s h ow n i n Figure 3.
- the linearity improves as the power increases logarithmically. Therefore the baseband gain stages in the proposed receiver are biased with a current density ⁇ 50 ⁇ / ⁇ to keep the total power consumption low while achieving decent linearity.
- incoming data is processed on a packet- by-packet basis by the receiver.
- a portion of the data packet is sampled at 42 at a standard sampling rate, such as twice Nyquist rate.
- the header of the data packet is sampled at the standard sampling rate although other portions of the packet may be used in lieu of the header. It is understood that the standard sampling rate may differ depending on the target or desired link performance.
- a quality metric is determined at 43, where the quality metric is indicative of quality of the data link over which the network data packet was received.
- the quality metric is indicative of quality of the data link over which the network data packet was received.
- signal-to-noise ratio is used as the quality metric.
- Other types of quality metrics are contemplated by this disclosure including a received signal strength index and a link quality indicator.
- the receiver can be operated at a lower sampling rate while maintaining link performance.
- the quality metric is compared at 45 to a threshold.
- the sampling rate can be lowered at 46, thereby reducing power consumption.
- the sampling rate can be set at 50% or 25 % of the standard rate. In other words, the sampling rate is set inversely to the quality of the data link.
- the remainder of the data packet is then processed at the reduced sampling rate as indicated at 27.
- the reduced sampling rate can be implemented in different ways as further described below.
- the sampling rate remains the same and the remainder of the data packet is processed at the standard sampling rate. Upon receiving another data packet, the process is repeated as indicated at 48. In this way, adaptive sampling is performed on a packet- by- packet basis. It is to be understood that only the relevant steps of the methodology are discussed in relation to Figure 4, but that other functions may be needed to control and manage the overall operation of the receiver.
- processing of additional data packets continues at the reduced sampling rate until the quality of the data link changes. That is, the quality of the data link is monitored by the receiver. Upon detecting a change in the quality of the data link, the sampling rate is set in the manner set forth above.
- FIG. 5 conceptually illustrates this method for an IEEE 802.15.4 standard compliant packet.
- the chips are half-sine shaped pulses.
- the channel pulse template is learned by averaging the received known pulses in the synchronization header of a protocol data unit (PPDU).
- PPDU protocol data unit
- the receiver is run at 2x the Nyquist rate while if the SNR is high, the receiver is run at 1 x the Nyquist sampling rate.
- the receiver maintains a fixed system link performance quantified by a target bit-error-rate (BER).
- BER bit-error-rate
- the sensitivity of the receiver is adapted to the time-varying characteristic of the communication channel on a per-packet basis.
- samples are selected in a particular manner.
- samples are ranked with respect to energy level and this information is later used for adapting the average sampling rate. More specifically, a subset of samples (having the highest energy level) is selected and the remainder of the data packet is sampled in accordance with the subset of samples.
- a 50% sampling rate two of four samples are chosen from each pulse.
- the second and third pulses have the highest energy value and thus are chosen while lowest two energy samples are not taken into account for further digital processing. It is noted that the reduced sampling rate remains uniform. For a 25% sampling rate, only the third pulse would be used for subsequent processing. In this case, the reduced sampling rate is nonuniform.
- the digital baseband processor will only process the selected samples and cease operating for the other samples. In the case of the 25% sampling rate, the digital baseband processor would process the third pulse but not the other three pulses.
- other components of the receiver can be disabled for a period of time within a sampling interval according the reduced sampling rate.
- an analog-to-digital converter can be disabled except to process the third pulse in the case of a 25% sampling rate.
- One or more other active circuits, such as amplifiers, filter, oscillators, etc. can also be disabled for a period of time within the sampling interval on a per-sample basis according to the reduced sampling rate. It is also understood one or more of these steps can be taken in combination to reduce power consumption.
- Figure 6 shows the waterfall curves for four different sampling rates: 25%, 50%, 75% and th e standard sampling rate.
- the receiver is run at a standard sampling rate of 2x the Nyquist rate for acquisition, synchronization and channel pulse template estimation. If the input E b /N 0 is > 9 dB, then the receiver can switch to 50% sampling rate and if the E b /N 0 is > 1 1 dB, then the receiver can switch to 25% sampling rate. In each case, the reduced sampling rate maintains the 10 ⁇ 3 BER link performance as shown in the figure.
- the 25% sampling rate would correspond to one out of four samples per pulse for the prototype chip. Once the sampling rate is selected, the receiver determines the highest energy samples on the channel pulse template, and these same time samples are used for processing the entire PHY payload (PSDU) in the PPDU packet.
- PSDU PHY payload
- FIG. 7 is a system block diagram for an example receiver 70.
- the receiver 70 is comprised generally of an RF front-end circuit 72, an analog-to-digital converter 78, and a digital baseband processor 79.
- the receiver is compatible with IEEE 802.15.4 RF packets apart from sensitivity and outputs the raw binary bits transmitted.
- the coherent direct-conversion RF front-end circuit 72 is configured to receive an RF analog signal from an antenna 71 and operates to shift the RF analog signal to an intermediate signal having a different frequency.
- the analog-to-digital converter 78 in turn receives the intermediate signal from the RF front-end circuit 72 and convert the intermediate signal to a digital signal.
- the RF front-end circuit 72 and two 5-bit flash ADCs operate at a 1 V analog supply while dissipating 0.87 mW and 0.57 mW, respectively.
- the digital baseband processor is configured to receive the digital signal from the analog-to-digital converter 78 and processes the digital signal at a prescribed sampling rate.
- the digital baseband processor typically comprises the signal processing required to acquire, synchronize, and demodulate information from the received signals, and perform further processing on the received packet according to the structure of the packet often defined by a standard. This includes feedback control signals to the analog front-end circuits.
- the digital baseband processor could also be described as a modem, a digital signal processor, or a radio controller such as a simple state machine.
- the digital baseband processor operates at a scaled supply voltage of 0.75 V, slightly above the device threshold voltage, while dissipating only 0.58 mW.
- the digital baseband processor power can be further reduced by 8% by implementing the adaptive sampling method described above.
- an RF signal at 2.45 GHz is directly fed into an active Gilbert cell based mixer 73 and quadrature down- converted to baseband.
- Channel selection is performed by a third-order Butterworth gm-C active low-pass filter 74 with a corner frequency of 1 .5 MHz.
- the filtered baseband signal is then amplified by three Programmable Gain Amplifiers (PGAs) 75 and followed by a buffer 76 which drives the input of the flash ADC.
- the 5-bit flash ADC 78 samples the incoming I & Q baseband signals at 4 MHz (2x the required Nyquist rate).
- Open loop digital DC-offset calibration is distributed across the front-end by using current DACs (Digital to Analog Converters) in the active filter and PGAs.
- the I & Q baseband chips are then processed by the digital baseband processor 79.
- the 5-bit resolution of the flash ADC is determined to have negligible impact on the link performance.
- the comparator offset in a flash ADC is reduced to be less than LSB/4 by sizing the transistors of the input stage.
- a MATLAB model has been developed to evaluate the ENOB (Effective Number Of Bits) of the flash ADC for the comparator offset measured from Monte Carlo simulations.
- Figure 8 shows that 4.8 bit ENOB is achievable for the flash ADC for the given comparator offset computed from simulations.
- the proposed receiver is intended for short-range wireless communication so to extend the communication range the wireless nodes are expected to operate in a mesh network.
- Friis equation (6) can be used to calculate the maximum line-of-sight communication range between two sensor nodes.
- the measured receiver sensitivity from RF-to-bits at 10 "3 BER is - 52.5 dBm.
- the communication range corresponding to -52.5 dBm RX sensitivity is found to be 9.2 m.
- the Packet Error Rate (PER) is related to the Symbol Error Rate (SER) if acquisition effects are ignored by the relation.
- DSSS Direct Sequence Spread Spectrum
- CG Coding Gain
- PG Processing Gain
- the coding CG is related to the degree of orthogonality for the code set, which for the DSSS code is calculated from the mean Hamming distance of the code set, d.
- the coding gain is approximately given by CG * 101og 10 fc (9)
- n is the length of the code.
- the CG is approximately 2 dB which reduces the required (E b /N 0 ) m i n to 6.8 dB.
- the Processing Gain is calculated by the ratio of the chip rate to the data rate.
- the chip rate is 2 Mcps and data rate is 250 Kbps that corresponds to PG of about 9 dB.
- the PG doesn't reduce the energy per bit required in contrast to CG but it's rather a measure of how much more energy is used to detect a bit as compared to the energy per chip (Es).
- Es/No energy per chip
- the ADC reference voltage is 300 mV
- reference impedance is 50 Ohms
- insertion loss for the RF band select filter is assumed to be 2 dB
- the link margin is 1 0 dB.
- the N F of the receiver front-end is calculated by where BW is assumed to be 1 .5 MHz.
- NF max Rss - SNR min - Margin + 174 ( ⁇ ) - 101og 10 BW (1 1 ) where Rss is the target receiver sensitivity.
- I EEE 802.1 5.4 standard doesn't specify the linearity requirements of the receiver front-end. Hence the linearity requirements can be derived from the interferer profile. IIP3, IIP2 and SFDR are calculated as follows,
- Pint is the power of the interferer and P S i g is the power of the desired signal.
- F is the receiver noise factor
- G max REF ADC - 6N ADC + SNR min - RSS + Margin (1 5)
- Gmin REFADC ⁇ ⁇ max ⁇ BO (1 6)
- R max is the maximum received power that is -20 dBm
- REF ADC is the ADC reference voltage power relative to 50 Ohm.
- the theoretical link budget along with measured performance is shown in Table 1 .
- Figure 9 illustrates a simplified digital baseband.
- the digital baseband waits in the idle state with an energy detection module 91 continuously computing the energy of the incoming baseband I & Q symbols.
- the digital baseband enters the acquisition and timing-synchronization state.
- the ideal square header template is used by the synchronization module 93 in correlations for achieving timing synchronization.
- the channel pulse template is computed by averaging 8- chips from the synchronization header. The averaged pulse template is then used to correlate the input I & Q data stream.
- the receiver LO is frequency locked but not phase-locked with the transmitted 2.45 GHz RF carrier and thus the RF carrier phase offset is estimated and corrected from the received O-QPSK symbols by the pahse correction module 95.
- This phase offset is calculated by computing the phase of the received O-QPSK symbols and comparing it with the known data transmitted in the synchronization header.
- a lookup table is used to calculate the phase angles and its corresponding correction factor.
- the link quality module 96 implements the adaptive sampling technique set forth above. That is, the link quality module 96 determines a metric indicative of quality of data link over which the RF analog signal was received and sets the prescribed sampling rate to a value that is inversely related to the quality of the data link.
- the 4 MHz sampling rate corresponds to four samples per I & Q symbol. From the computed channel pulse response, the link quality module 96 ranks the four samples with respect to energy. This is conceptually illustrated in Figure 9. By lowering the samples in the case of high SNR, some energy per symbol is traded off with reduced computational power in the following stages.
- digital clock gating is used in the digital baseband at the module level to save computational power.
- the digital clock is enabled for a module if it needs to process the current time sample from the ADC.
- the time samples are ranked in energy from the learned channel pulse template.
- the clock is enabled for a module only for the time samples corresponding to the highest energy samples consistent with the selected average sampling rate. In this way by reducing the average frequency of the digital processing unit, the total average power is reduced
- a decoding module 97 uses a matched-filter to perform hard decision decoding (HDD). HDD is used for lower computational complexity as compared to soft-decision decoding (SDD), with roughly a 2 dB penalty in link performance.
- the de-spreader module 98 despreads the received chips and outputs the raw binary data transmitted. For BER testing, the digital baseband enters into a state where it demodulates the data infinitely. Module level clock gating is used in the digital baseband to save power.
- module may refer to, be part of, or include: an Application Specific Integrated Circuit (ASIC); a digital, analog, or mixed analog/digital discrete circuit; a digital, analog, or mixed analog/digital integrated circuit; a combinational logic circuit; a field programmable gate array (FPGA); a processor circuit (shared, dedicated, or group) that executes code; a memory circuit (shared, dedicated, or group) that stores code executed by the processor circuit; other suitable hardware components that provide the described functionality; or a combination of some or all of the above, such as in a system-on-chip.
- ASIC Application Specific Integrated Circuit
- FPGA field programmable gate array
- Figure 10 is a detailed schematic of the l/Q channel for an example RF front end with external LO and may be used in the received described above.
- Single-to-differential conversion of the LO signal is achieved using an on-chip LO buffer, the output of which is then AC coupled to a single- balanced gilbert-cell active mixer.
- the LO buffer is a resistive loaded differential amplifier cascaded with a source follower for a DC level shift.
- the receiver doesn't use an LNA and instead relies on an active mixer to provide RF gain. Since the baseband modulated signal has significant low-frequency content, the devices in the active mixer are sized to reduce the flicker-noise corner frequency to ⁇ 1 00 KHz.
- the IEEE 802.15.4 PHY requires 0 dB rejection at the adjacent channel ( ⁇ 5 MHz) and 30 dB rejection at the alternate channel ( ⁇ 10 MHz). Assuming 10 dB margins, 40 dB rejection at the alternate channel can be achieved through the third-order Butterworth-type filter with corner frequency of 1 .5 MHz. The filter will provide 50 dB rejection at 10 MHz apart from the wanted signal and thus can be used as the channel selection anti-aliasing filter. To adjust the corner frequency of the filter over process corners, the capacitors are made tunable by a 3-bit binary control word to vary capacitance by ⁇ 20%. The differential output of the mixer is converted into single-ended by the input stage of the gm-C filter.
- the entire baseband is implemented single-ended to save power.
- the baseband gain is distributed between the active filter and the PGAs.
- Programmable gain (PG) is implemented by switchable fixed gain-stages.
- the gain stage is implemented as a modified first order gm-C stage.
- a transmission gate is used which when enabled allows the input signal to bypass the gain stage which is being disabled by a footer.
- Each PG stage provides a gain of about 8 dB for a total PGAs' gain of roughly 24 dB.
- the current DACs are designed to reduce the DC- offset to within LSB/2 of the flash ADC.
- the output of the PG stages is fed into a buffer that drives the input capacitance of the flash ADC. S/H circuit is avoided at the input of the flash ADC considering that 1 MHz baseband signal isn't fast enough relative to the comparator speed in 65 nm CMOS to cause aperture errors.
- the LSB size is 9.4 mV for a reference voltage of 300 mV, generated off- chip.
- no pre-amplifier is used in the comparator that makes the flash converter susceptible to comparator kickback.
- decoupling capacitors of 2 pF are added to the reference ladder as shown in Fig. 10.
- the output of the comparator is fed into an SR latch, also shown in Fig. 10.
- the digital baseband converts the thermometer code into binary and uses a simple adding encoders' technique to reduce bubble and sparkle errors of the flash ADC.
- FIG. 12A-12C show the transmitted I channel modulated data, measured I channel analog baseband waveform along with the digitized output from the I channel ADC for a -40 dBm RF input signal. The transmitted and the received data waveforms are time-delayed and 180° out of phase. Since a coherent receiver is implemented, this phase shift is corrected in the digital baseband processor.
- Figures 13A-13D show the measured performance of the RF front-end along with the flash ADC spectrum.
- the flash ADC achieves an ENOB of 4.3 at the input frequency of 1 MHz.
- the total average gain over the IF bandwidth of 1 MHz is 37 dB while the average NF is 28 dB.
- the measured average NF is about 10 dB lower than the simulated value. This is because the receiver noise is dominated by 1/f flicker noise, which is not accurately modeled in simulations.
- a two-tone test at (LO ⁇ 50 KHz) shows the measured IIP3 at high-gain and low-gain setting as -35 dBm and -14 dBm, respectively, and the measured IIP2 at high-gain and low-gain setting as -25 dBm and -13.5 dBm respectively.
- Figure 14 shows the received RF packets for -40 dBm RF input signal.
- a dummy PHY payload of binary data 10012 is used for the test.
- the IEEE 802.15.4 standard compliant packet is also shown in the figure.
- SFD is the start-of-frame delimiter, which is used for frame synchronization.
- Figures 15A-15D shows the measured energy efficiency profile of the entire system along with simulated energy efficiency breakdown of the radio, the BER curve and the radar plot of the most desirable RX metrics for comparison.
- a bigger star represents a superior design. This plot highlights how communication distance has been traded-off for improved energy efficiency and battery life.
- the measured energy efficiency of the RF- frontend alone is 3.5 nJ/bit while it is 2.3 nJ/bit for the ADC and the DBB.
- the digital baseband enters into a state where it receives the data infinitely.
- the measured sensitivity of the RX is -52.5 dBm at 10 "3 BER. From the measured BER performance, it is observed that if the input SNR is about 3 dB higher at 2x the Nyquist sampling than for the same link performance of 10 "3 the DBB can be operated at 25% samples with an energy efficiency of 2.1 nJ/bit.
- the receiver would require an on- chip LO.
- a 2.4 GHz LO generated using a PLL consumed 1 .6 mW including the PLL, LC-VCO and VCO buffer and 1 .2 mW for an entire QVCO [23]. This corresponds to roughly total power of 3 mW for a complete receiver, including this work.
- This receiver has 2x better energy efficiency for the radio front-end (3.5 nJ/bit) than previous approaches, while reporting 8.1 nJ/bit energy efficiency for an O-QPSK DSSS coherent receiver with near-threshold digital baseband.
- Radio energy efficiency is going to play a key role in extending the battery life of future loT devices.
- Different design tradeoffs can be made for these emerging applications as compared to the conventional high performance radios.
- the radio receiver also adapts its average sampling rate for high input SNR while still maintaining the target link
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- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
- Circuits Of Receivers In General (AREA)
Abstract
Description
Claims
Applications Claiming Priority (2)
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US201461984316P | 2014-04-25 | 2014-04-25 | |
PCT/US2015/027505 WO2015164735A1 (en) | 2014-04-25 | 2015-04-24 | Short-range zigbee compatible receiver with near-threshold digital baseband |
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EP3135010A1 true EP3135010A1 (en) | 2017-03-01 |
EP3135010A4 EP3135010A4 (en) | 2017-11-22 |
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EP15782751.0A Withdrawn EP3135010A4 (en) | 2014-04-25 | 2015-04-24 | Short-range zigbee compatible receiver with near-threshold digital baseband |
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EP (1) | EP3135010A4 (en) |
CN (1) | CN106537860A (en) |
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CN110120817B (en) * | 2018-02-05 | 2024-04-26 | 长沙泰科阳微电子有限公司 | Automatic output power adjustable RF digital-to-analog converter |
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JP3967472B2 (en) * | 1998-09-07 | 2007-08-29 | 富士通株式会社 | CDMA receiver |
US7656970B1 (en) * | 2006-09-01 | 2010-02-02 | Redpine Signals, Inc. | Apparatus for a wireless communications system using signal energy to control sample resolution and rate |
JP4304632B2 (en) * | 2006-10-12 | 2009-07-29 | ソニー株式会社 | Receiving device, receiving method, program, and recording medium |
CN102577289B (en) * | 2009-08-13 | 2014-12-17 | 卡斯寇达有限公司 | Wireless receiver |
US9356774B2 (en) * | 2012-06-22 | 2016-05-31 | Blackberry Limited | Apparatus and associated method for providing communication bandwidth in communication system |
-
2015
- 2015-04-24 CN CN201580032014.4A patent/CN106537860A/en active Pending
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EP3135010A4 (en) | 2017-11-22 |
CN106537860A (en) | 2017-03-22 |
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