EP2973197B1 - Programmable device personalization - Google Patents
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- EP2973197B1 EP2973197B1 EP14711371.6A EP14711371A EP2973197B1 EP 2973197 B1 EP2973197 B1 EP 2973197B1 EP 14711371 A EP14711371 A EP 14711371A EP 2973197 B1 EP2973197 B1 EP 2973197B1
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- 230000015654 memory Effects 0.000 claims description 55
- 239000004065 semiconductor Substances 0.000 claims description 30
- 230000006870 function Effects 0.000 claims description 23
- 238000012360 testing method Methods 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 15
- 230000002093 peripheral effect Effects 0.000 claims description 6
- 238000013507 mapping Methods 0.000 claims description 5
- 125000004122 cyclic group Chemical group 0.000 claims description 3
- 238000013459 approach Methods 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000001419 dependent effect Effects 0.000 description 1
- 238000007519 figuring Methods 0.000 description 1
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- 230000010076 replication Effects 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/78—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
- G06F21/79—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/30—Authentication, i.e. establishing the identity or authorisation of security principals
- G06F21/44—Program or device authentication
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
- G06F21/73—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by creating or determining hardware identification, e.g. serial numbers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
- G06F21/76—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
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- Microelectronics & Electronic Packaging (AREA)
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- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
- The present disclosure relates to a programmable device personalization, in particular for semiconductor devices.
- One security concern of customers today is protection against replication of a product. For example, in an automotive key fob, part of the security of the system relies on the fact that the actual application specific integrated circuit (ASIC) or system on a chip (SoC) is unique for the customer. This means a semiconductor manufacturer must produce a new mask set with some different underlying characteristics (memory map, pinout, functions, etc.) than that of the corresponding general purpose device mask set.
- Hence, there is a need to provide for a programmable device personalization which provides for a scheme to allow end customers and/or manufacturer to create unique devices from general purpose products. This and other objects can be achieved by a semiconductor device and method as defined in the independent claims. Further enhancements are characterized in the dependent claims.
- For example, one embodiment provides a semiconductor device may include a secure memory configured to store a programmable key, also referred to herein as a "device personalization key," an interface for programming the programmable key in the secure memory, and a plurality of configurable features of the semiconductor device that are associated with the programmable key, each configurable feature having a set of multiple selectable configurations, wherein a value of the key defines a selection of one of the multiple configurations for each of the configurable features. For example, the key may include multiple sub-keys, each associated with one of the configurable features, wherein a value of each sub-key defines a selection of one of the multiple configurations for the configurable feature associated with that sub-key. In addition, the full programmable key may enable an additional functionality of the semiconductor device.
- Another embodiment provides a method for configuring a semiconductor device having an accessible memory, a secure memory, a configuration interface, and a plurality of configurable features, each configurable feature having a set of multiple selectable configurations. The method may include programming a key into the secure memory using the configuration interface provided on the semiconductor device, wherein a value of the key defines a selection of one of the multiple configurations for each of the configurable features.
- Thus, according to various embodiments, a programmable "device personalization key" can be built into a general purpose device. In a situation in which a semiconductor device manufacturer supplies devices to multiple customers, each customer can have a unique device based on the device personalization key programmed into the respective device, either by the manufacturer, by the customer itself, or by another party. As mentioned above, each programmable key may include multiple sub-keys (each sub-key comprising a sub-set of bits of the full key), with each sub-key being used to configure a particular aspect or feature of the device, such as a memory map for a device memory, a test entry code, an identify or availability of a peripheral set, a pinout configuration, an interrupt vector table location, program address scrambling/mapping configurations, etc. Each configurable feature of the device may have multiple different possible configurations, and value of each sub-key may define the selection of a particular one of the multiple possible configurations for the configurable feature associated with that configurable feature.
- In some embodiments, the decoding of these sub-keys may be designed such that multiple values of each sub-key (or at least some sub-keys) will result in the feature selection. For example, for the test entry code sub-key,
values values 4, 6 result in test entry code 'C'. This increases the difficultly to reverse engineer a device personalization key in the event that the feature set of the device (i.e., the selected configurations for the various configurable features) can itself be reverse engineered. For example, with reference to the example above, knowledge that a particular device is using test entry code 'A' instead of 'B' or 'C' does not indicate the exact test entry code sub-key value of the device personalization key, but rather only the possible set of sub-keys values on the device corresponding to that test entry code (e.g., knowledge that the device is using test entry code 'A' indicates only that the entry code sub-key value is 1, 3, or 7. A particular advantage of this scheme, for further deterring copying or reverse engineering of a device, is understood in view of the additional device feature enabled by the full device personalization key, as discussed below. - In some embodiments, the full device personalization key can be used to compute an additional value, or "sub-key," that can be used to configure or personalize an additional feature, such as program address scrambling/mapping, for example. In some embodiments, an existing CRC peripheral or a hash function could be used to generate a code number from a long device personalization key. Thus, for a particular device, even if one were to determine a suitable sub-key to correctly configure each sub-feature of the device, the additional feature enabled by the full device personalization key cannot be provided without exact knowledge of the full device personalization key.
- In some embodiments, the device is designed to allow the key to be programmed by either the manufacturer or by the customer itself. Allowing the customer to program its own key provides the additional benefit of placing the entire supply chain in the hands of the customer themselves. That is, it becomes impossible for the manufacturer to sell a first customer's "custom" device to a second customer, as the manufacturer does not know the device personalization key used by the first customer. Alternatively, programming the key by the manufacturer allows the manufacturer to provide personalized devices without having to form multiple masks per product, as in conventional personalization schemes. In other words, personalization can be done after the device is packaged.
- In some embodiments, according to the inventive features discussed above, in order to clone a product, one must possess the original program code (or image), the knowledge of which general purpose part is being used, and the exact and full device personalization key.
- Thus, a device and method are available according to various embodiments that provide device personalization services to a broader customer base for a lower cost.
- Example embodiments are discussed below with reference to the drawings, in which:
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FIGURE 1 shows a block diagram of an example semiconductor device, e.g., microcontroller, which can be personalized using a device personalization key, according to various embodiments; -
FIGURE 2 shows an example n-bit programmable key, having multiple sub-keys, that can be programmed into the device ofFIGURE 1 , according to an example embodiment; -
FIGURE 3 illustrates the concept of assigning multiple sub-key values to each selectable configuration for a particular configurable feature; and -
FIGURE 4 illustrates the generation of a "signature" value from the programmable key, which may be used to enable or configure another feature of the personalized device. -
FIGURE 1 shows a block diagram of an example semiconductor device 10, e.g., microcontroller, which can be personalized according to various features of the present disclosure. Device 10 may include aprocessor 12, adata memory 14, a program memory 16 storing one ormore programs 17 for providing various functionality of device 10, an optionaladditional memory 18, and asecure memory 20, a personalization key storage anddecoding unit 22, and a number of configurable features 24. In this example, configurable features 24 include a configurablememory address scrambler 24A, pinout tables 24B, interrupt vector table(s) 24C, and aninternal test unit 24D, for example.Secure memory 20 may store adevice personalization key 30 that includes a plurality ofsub-keys 32.Device personalization key 30 may include any suitable number ofsub-keys 32. -
Processor 12 may, for example, be a processor core MCU which has access todata memory 14 through the configurablememory address scrambler 24A, which performs address scrambling according to one or more methods defined by one of thesub-keys 32 of thedevice personalization key 30 stored insecure memory 20. In some embodiments, additional data memory 16, which typically is not accessible in a general purpose device, can be activated by one of thesub-keys 32. In addition to thememory address scrambler 24A, various other configurable features 24 of the microcontroller 10 may be defined by thepersonalization key 30, such as the configuration of a specific pinout (defined by pinout tables 24B), address(es) of interrupt vector tables) 24C, internal test entry sequences defined byinternal test unit 24D, and other configurable functions as explained above. -
Data memory 14, program memory 16,additional memory 18, andsecure memory 20 may be formed as discrete memory structures, or any two or more (or all) of such memories may comprise specified areas of an integrated memory structure. For example,secure memory 20 may be a physically distinct memory structure fromdata memory 14, additional memory 16, and/or program memory 16, or may comprise an assigned area of an integrated memory device. - Personalization key storage and
decoding unit 22 may provide an interface for, or otherwise facilitate, writingkey 30 into secure memory 20 (i.e., programming the key into secure memory 20), and may also be configured to decodekey 30. In some embodiments, the decoding may be performed by simple logic, such as comparators, as multiple sub-key values may be assigned to the same function configuration, e.g., as discussed below regardingFIGURE 3 . - Thus, customer-specific devices 10 can be produced by merely programming the
personalization key 30 with a unique code. Such devices can otherwise be produced as a single version. According to some embodiments, at end of a manufacturing line, such device may be provided with different device numbers on the housing of the device or optionally with no markings at all. However, they could also simply comprise the same markings as a general purpose device. Thus, it would be unknown to a third person that the device is actually differently configured than a general purpose device. -
FIGURES 2-4 illustrate various aspects of thedevice personalization key 30, according to certain embodiments. -
FIGURE 2 shows an example of an n-bitprogrammable key 30 that can be programmed into device 10, for example into an associated register ofsecure memory 20.Secure memory 20 may be provided which provides for non-volatile storage of the key which cannot be read by a user. In some embodiments,memory 20 is configured such that it can be written to only once and is inaccessible a user will have no access to this memory once it is programmed. - As shown, the
personalization key 30 may include several "sub-keys" 32. In this example,key 30 includes sixsub-keys 32, labeled A-F. However, key 30 may include any other suitable number ofsub-keys 32. Further, eachsub-key 32 of akey 30 may have any suitable length (e.g., number of bits). Further, thesub-keys 32 of aparticular key 30 may have the same length or different lengths. Eachsub-key 32 may be assigned to a particular configurable features or aspect of the device 10. In the example shown infigure 2 , sub-keys A-F are assigned to the following six configurable aspects of the device 10: (A) the start location of an SRAM (static random-access memory) area, e.g., withindata memory 14; (B) the address of an interrupt vector table 24C, e.g., within program memory 16; (C) the availability or enabled state of a peripheral set associated with the device 10; (D) an internal test entry sequence (e.g., as defined byinternal test unit 24D); (E) an SFR (special function register) memory map (e.g., utilized bymemory address scrambler 24A; and (F) a pinout configuration (e.g., as defined by pinout tables 24B). - Each of such configurable features may have multiple different possible configurations. Each sub-key A-F has a n-bit value that defines the selection of a particular one of the multiple possible configurations for the corresponding configurable feature. For example, the value of sub-key D may define a particular test entry sequence selected from three different possible test entry sequences. As another example, the value of sub-key F may define a particular pinout configuration selected from six possible pinout configurations.
- Thus, various configurations or functionalities of the device 10 can be defined in various ways using the
multiple sub-keys 32. For example, a configurable programmable pin assignment (defined by sub-key F) may allow to assign external pins of a semiconductor device 10, for example a microcontroller, to be connected to a specific peripheral device. Without the correct code, this function may not be activated rendering the device inoperable when using copied firmware. - Each configurable feature may have any suitable number of possible selectable configurations. Further, each sub-key may have any suitable length (in bits), thus allowing for any number of possible values. In one example embodiment, a sub-key 32 may be 4 bits long, thus defining 16 possible values.
- In some embodiments, each sub-key may have more possible values than possible selectable configurations for the associated configurable feature, thus allowing the assignment of multiple sub-key values to each selectable configuration for the feature, which may provide additional protection against copying or reverse engineering the device.
- For example,
FIGURE 3 highlights sub-key "D" corresponding to the configurable test entry sequence. The test entry sequence may have four selectable sequences,Sequence # 1,Sequence # 2,Sequence # 3, andSequence # 4. Sub-key D may have a 4-bit value, thus defining 16 possible sub-key values. Thus, as shown, four different 4-bit sub-key values are mapped to each of the four sequences. - This mapping arrangement may help prevent reverse-engineering of
key 30 from knowledge of feature sets/configurations. Moreover, figuring out the configured test entry sequence (e.g., Sequence #3) may only indicate of one possible sub-key value (out of the four sub-key values assigned to Sequence #3), which may not be the correct value key (e.g., theSequence # 3 sub-value "1000" may be identified, while theactual Sequence # 3 sub-key value in the key 30 is "1010"). This incorrect identification may prevent a copier from accessing a function that is enabled only by the full,correct key 30, as explained below with reference toFIGURE 4 - Internally, the sub-key decoding provided by decoding
unit 22 merely needs simple logic, such as comparators, as multiple sub-key values may be assigned to the same function configuration. If each sub-key value generates a unique function configuration, then a simple decoder can be used. A general purpose device may comprise this additional personalization feature and a predefined key 30 may be stored. In addition, device 10 may include logic that prevents accidental programming of the key 30. Thus, device 10 may include a specific programming sequence to allow a one-time-only programming of the key 30 to prevent accidental overwriting, e.g., for users that do not need this functionality. - Moreover, in some embodiments, the functionality may not be documented for general purpose devices. Only customers that require this functionality would be provided with the associated personalization function. For example, in embodiments where the manufacturer programs the key 30 individually for a customer, a dedicated data sheet may be provided for this customer that explains the specific functions as set by the
specific key 30. However, a more complex data sheet could be provided that explains the various setting that respective keys would generate. - As discussed above, in some embodiments, the full
device personalization key 30 can be used to compute an additional value, or "signature," to enable, configure, or personalize a particular feature or function of device 10.FIGURE 4 illustrates an example of this aspect. As shown, an algorithm orfunction 40 can be applied to the full personalization key 30 (including all sub-keys) to generate akey signature value 42 that may be used to enable, configure, or personalize a particular feature of the device 10. For example, thekey signature value 42 may define a selection of a configurable feature, in a similar manner as each sub-key 24. Alternatively, thekey signature value 42 itself may be used to provide a function. For instance, thekey signature value 42 itself may be used as an encryption key, e.g., for internal device communications or for communications with external devices. - The algorithm or
function 40 may include any algorithm or function to transform or convert the key 30 into akey signature value 42. For example, a cyclic redundancy check (CRC), or a one-way function such as a hash function, could be used to generate a code number (key signature value 42) from a longdevice personalization key 30. - Thus, in order to enable, configure, or personalize a particular feature or function of device 10, the full exact key 30, including all sub-keys 24, must be known. Thus, for a particular device, even if one were to determine a suitable sub-key to correctly configure each feature of the device, the additional feature enabled or configured by the full device personalization key 30 (e.g., by the
key signature value 42 generated from the full key 30) cannot be provided without exact knowledge of the fulldevice personalization key 30. - In other embodiments, the
key signature value 42 may be generated based on multiple sub-keys 24 of a key, but less than theentire key 30. For example, thekey signature value 42 may be generated based on a subset of the sub-key values, or based on a portion of every sub-key value. - Thus, according to the above, in some embodiments, in order to clone a product, one must possess the original program code (or image), the knowledge of which general purpose part is being used, and the exact and full device personalization key.
- For decoding the
personalization key 30, any encryption key procedure may be used, according to various embodiments. The disclosed method allows the addition of device personalization to any semiconductor device that comprises a programming interface, without the need to apply a different mask set during manufacturing. Separate personalization key storage ensures that if a customer's program code is copied, and someone knows which manufacturer device is being used, they can not clone the device without significant effort. In some embodiments, a base approach for the manufacturer could be to program a personalization key, and then give out a custom datasheet to match the device as stated above. An extended approach in other embodiments is to allow the customer to program their own personalization key, which allows the customer to have total control over their own supply chain. The customer may inform the manufacturer of a set of desired configuration for various device features (e.g., a desired set of features, desired memory map, desired pinout, etc.) and the manufacturer may then provide a list of sub-key value corresponding to the selected configuration for each feature (as each configuration may have multiple assigned sub-key values, as discussed above regardingFIGURE 3 ). The customer may then assembles a personalization key from any of these sub-key values, and program the resulting key into their device, thereby giving the customer a personalization key that is unknown to the manufacturer.
Claims (15)
- A semiconductor device, comprising:a secure memory (20) configured to store a programmable key (30) comprising a plurality of sub-keys (32);an interface (22) for programming the programmable key (30) in the secure memory (20); anda plurality of configurable features (24A, 24B, 24C, 24D) of the semiconductor device each being associated with one of said plurality of sub-keys (32) of the programmable key (30), each configurable feature (24A, 24B, 24C, 24D) having a set of multiple selectable configurations;wherein a value of each sub-key (32) defines a selection of one of the multiple configurations for a respective one of the configurable features (24A, 24B, 24C, 24D) associated with that sub-key (32),wherein the plurality of configurable features (24A, 24B, 24C, 24D) comprises at last one of a pinout configuration, a memory mapping of a memory of the semiconductor device, a test entry sequence, a peripheral set availability, an interrupt vector table location, and an SRAM start location.
- The semiconductor device according to claim 1, wherein the full programmable key (30) enables an additional functionality of the semiconductor device.
- The semiconductor device according to claim 2, wherein the additional functionality of the semiconductor device is enabled by a value resulting from an application of a logical algorithm to the full programmable key.
- The semiconductor device according to claim 3, wherein the logical algorithm is a cyclic redundancy check or a hash function.
- The semiconductor device according to claim 2, wherein the additional functionality enabled by the full programmable key is a memory address or code scrambling function (24A).
- The semiconductor device according to one of the preceding claims, comprising electronics that allow the programmable key(30) to be programmed only once.
- The semiconductor device according to claim 6, comprising an access device for writing said key (30) and configured to prevent accidental overwriting of the key (30).
- The semiconductor device according to one of the preceding claims, with the programmable key (30) programmed and stored in the secure memory (20).
- A method for configuring a semiconductor device having an accessible memory (15; 1; 18), a secure memory (20), a configuration interface (22), and a plurality of configurable features (24A, 24B, 24C, 24D), each configurable feature (24A, 24B, 24C, 24D) having a set of multiple selectable configurations, the method comprising:programming a key (30) into the secure memory (20) using the configuration interface (22) provided on the semiconductor device, wherein the key (30) comprises a plurality of sub-keys (32);wherein a value of each sub-key (32) defines a selection of one of the multiple configurations for a respective one of the configurable features (24A, 24B, 24C, 24D) associated with that sub-key (32),wherein the plurality of configurable features (24A, 24B, 24C, 24D) comprises at last one of a pinout configuration, a memory mapping of a memory of the semiconductor device, a test entry sequence, a peripheral set availability, an interrupt vector table location, and an SRAM start location.
- The method according to claim 9, wherein the full key enables an additional functionality of the semiconductor device.
- The method according to claim 10, comprising applying a logical algorithm to the full key (30) to generate a value that enables the additional functionality of the semiconductor device.
- The method according to claim 11, wherein the logical algorithm is a cyclic redundancy check or a hash function.
- The method according to claim 11 or 12, wherein the additional functionality enabled by the full key (30) is a memory address or code scrambling function.
- The method according to one of the preceding claims 9-12, wherein the device prevents the key from being programmed more than once.
- The method according to claim 14, wherein the device prevents the key from being programmed more than once by using an access device for writing the key and preventing an accidental overwriting of the key (30).
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201361780994P | 2013-03-14 | 2013-03-14 | |
US14/181,971 US9754133B2 (en) | 2013-03-14 | 2014-02-17 | Programmable device personalization |
PCT/US2014/019316 WO2014158692A1 (en) | 2013-03-14 | 2014-02-28 | Programmable device personalization |
Publications (2)
Publication Number | Publication Date |
---|---|
EP2973197A1 EP2973197A1 (en) | 2016-01-20 |
EP2973197B1 true EP2973197B1 (en) | 2020-04-01 |
Family
ID=50336529
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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EP14711371.6A Active EP2973197B1 (en) | 2013-03-14 | 2014-02-28 | Programmable device personalization |
Country Status (6)
Country | Link |
---|---|
US (1) | US9754133B2 (en) |
EP (1) | EP2973197B1 (en) |
KR (1) | KR20150129694A (en) |
CN (1) | CN105190642B (en) |
TW (1) | TWI641967B (en) |
WO (1) | WO2014158692A1 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
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US10959635B2 (en) * | 2017-10-02 | 2021-03-30 | Biosense Webster (Israel) Ltd. | Random pinout catheter |
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2014
- 2014-02-17 US US14/181,971 patent/US9754133B2/en active Active
- 2014-02-28 WO PCT/US2014/019316 patent/WO2014158692A1/en active Application Filing
- 2014-02-28 CN CN201480011541.2A patent/CN105190642B/en active Active
- 2014-02-28 EP EP14711371.6A patent/EP2973197B1/en active Active
- 2014-02-28 KR KR1020157023688A patent/KR20150129694A/en not_active Application Discontinuation
- 2014-03-11 TW TW103108286A patent/TWI641967B/en active
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Also Published As
Publication number | Publication date |
---|---|
WO2014158692A1 (en) | 2014-10-02 |
US20150235057A1 (en) | 2015-08-20 |
TW201443691A (en) | 2014-11-16 |
US20160085997A9 (en) | 2016-03-24 |
US9754133B2 (en) | 2017-09-05 |
TWI641967B (en) | 2018-11-21 |
KR20150129694A (en) | 2015-11-20 |
CN105190642B (en) | 2018-11-02 |
EP2973197A1 (en) | 2016-01-20 |
CN105190642A (en) | 2015-12-23 |
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