EP2162922A1 - Contact structure for a semiconductor component and a method for production thereof - Google Patents

Contact structure for a semiconductor component and a method for production thereof

Info

Publication number
EP2162922A1
EP2162922A1 EP08759295A EP08759295A EP2162922A1 EP 2162922 A1 EP2162922 A1 EP 2162922A1 EP 08759295 A EP08759295 A EP 08759295A EP 08759295 A EP08759295 A EP 08759295A EP 2162922 A1 EP2162922 A1 EP 2162922A1
Authority
EP
European Patent Office
Prior art keywords
substrate
barrier layer
layer
contact structure
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP08759295A
Other languages
German (de)
French (fr)
Inventor
Andreas Krause
Bernd Bitnar
Holger Neuhaus
Martin Kutzer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Deutsche Cell GmbH
Original Assignee
Deutsche Cell GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Deutsche Cell GmbH filed Critical Deutsche Cell GmbH
Publication of EP2162922A1 publication Critical patent/EP2162922A1/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C28/00—Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D
    • C23C28/02—Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D only coatings only including layers of metallic material
    • C23C28/023—Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D only coatings only including layers of metallic material only coatings of metal elements only
    • C—CHEMISTRY; METALLURGY
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    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C28/00—Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D
    • C23C28/30—Coatings combining at least one metallic layer and at least one inorganic non-metallic layer
    • C23C28/32—Coatings combining at least one metallic layer and at least one inorganic non-metallic layer including at least one pure metallic layer
    • C23C28/321—Coatings combining at least one metallic layer and at least one inorganic non-metallic layer including at least one pure metallic layer with at least one metal alloy layer
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    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
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    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
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Definitions

  • the invention relates to a semiconductor device and a method for producing such a semiconductor device.
  • solar cells have a frontal contact of screen printed silver fingers. These have a typical width of 100 to 120 microns and are about 10 to 15 microns thick. Since screen printing does not allow for significantly higher aspect ratios than about 0.1, the finger width can not be reduced without simultaneously increasing the line resistance of the fingers. On the other hand, the losses caused by the shadowing of the front side are the greater the wider the front contacts are. Another disadvantage is the high material costs of the silver contacts.
  • EP 1 182 709 A1 discloses a method for the production of metal contacts, in which trenches are arranged on the front side of a silicon substrate, which receive a metal contact from a nickel-copper layer system.
  • a disadvantage of this method is the necessary annealing step after the nickel deposition.
  • DE 43 33 426 C l a method for light-induced electroplating of silicon sub-tract contacts is described.
  • the back contact of the silicon substrate serves as a sacrificial cathode.
  • the chemicals used are cyanide-containing.
  • DE 43 11 173 Al describes a method for direct electroplating on silicon surfaces.
  • the deposition of a palladium seed layer is first necessary. This is followed by a nickel coating on which the actual current-carrying contact layer is deposited.
  • DE 10 2004 034 435 B4 describes a method for light-induced deposition of a metal contact along an edge of a trench introduced into the surface of a semiconductor component.
  • US Pat. No. 4,320,250 discloses a silicon substrate having a multiplicity of closely spaced electrodes, which consist of a plurality of successive layers which are first deposited on the contact surfaces of the silicon substrate by means of conventional vacuum coating technology and then, in a further process step, by a GaI process. vanik process be increased. This process is very expensive.
  • DE 198 31 529 A1 relates to a method for producing an electrode which is applied to tip-shaped or edge-shaped projections on a substrate surface by electroforming or electrostatic powder coating. After that, a series of chemical reactions and process steps are needed to complete the electrode.
  • the invention is therefore based on the object to provide a cost-effective method for producing a contact structure with a high aspect ratio and a Hableiter component with such a contact structure.
  • the gist of the invention is to provide a barrier layer between a semiconductor substrate and a conductor layer for preventing the diffusion of defect-causing ions from the conductor layer into the semiconductor substrate. This greatly expands the choice of materials available to form the conductor layer. In addition, this makes it possible to achieve a contact structure with a high aspect ratio, which reduces the losses due to the shading of the front side by the contact structure. Further advantages emerge from the subclaims.
  • FIG. 1 shows a schematic, not to scale cross-section through a semiconductor device with applied conductor tracks before the application of a barrier layer
  • FIG. 2 shows a cross section according to FIG. 1 after applying a barrier layer but before applying a conductor layer
  • F ig. 3 shows a cross section according to FIG. 2 after application of a conductor layer but before application of a protective layer
  • FIG. 4 shows a cross section according to FIG. 3, however, after application of a protective layer, FIG.
  • Fig. 5 is a schematic representation of the method for producing a semiconductor device according to FIGS. 1 to 4 and
  • Fig. 6 is a schematic, not to scale cross section through a further Ausfi the application of printed conductors.
  • a semiconductor component 1 has a substrate 2.
  • a substrate 2 is used in particular a silicon substrate.
  • substrate 2 another semiconductor substrate may serve as well.
  • the substrate 2 is substantially flat with a first side and a second side opposite thereto.
  • the first side forms a front side 3, while the second side forms a back side 4 of the substrate 2.
  • the substrate 2 consists at least partially of silicon.
  • the angle b is in particular greater than 90 °, in particular greater than 100 °.
  • the flanks 16 of the conductor track 5 are thus preferably designed to converge, which leads to a particularly low shading.
  • the conductor tracks 5 can also be arranged on the back 4.
  • the conductor tracks 5 are in electrical contact with the substrate 2.
  • the conductor tracks 5 are made of an electrically conductive material, in particular a metal, which has an extremely low diffusion coefficient with respect to the material of the substrate 2.
  • the interconnects 5 have in particular a high silver content. They can also be made entirely of pure silver.
  • the interconnects 5 have a width B parallel to the front side 3 of the silicon substrate 2, which is as small as possible in order to reduce shading of the front side 3 by the interconnects 5.
  • the interconnects 5 have a height H perpendicular to the front side 3, which is as large as possible in order to reduce the line resistance of the interconnects 5.
  • the conductor tracks 5 are thus projected by the height H from the front side 3.
  • the lateral flanks 16 are thus exposed over their entire extent.
  • the width B of the conductor tracks 5 is in the range of 10 .mu.m to 200 .mu.m, in particular in the range of 100 .mu.m to 120 .mu.m.
  • the height H of the conductor tracks 5 is usually in the range of 1 .mu.m to 50 .mu.m, in particular in the range of 5 .mu.m to 15 .mu.m.
  • Such interconnects 5 usually have a line resistance R
  • the line resistance Ri f can also be significantly higher.
  • the semiconductor component 1 has a blocking layer 6, as shown in FIG. 2.
  • the barrier layer 6 in particular surrounds the conductor track 5.
  • the thickness of the barrier layer 6 is 0.1 to 5 ⁇ m, in particular 0.2 to 1 ⁇ m.
  • the barrier layer 6 is made of a material, in particular a metal, which has a negligible diffusion coefficient or a negligible miscibility with respect to the material of the conductor tracks 5 and the conductor layer 7.
  • the barrier layer 6 is in particular made of electrolytically or chemically applied cobalt. It can also consist of nickel, the electrolytic is applied. Other materials are also conceivable.
  • the barrier layer 6 advantageously has a high electrical conductivity.
  • the metal of the barrier layer can be well electrochemically stripped to clean the contact rollers. This applies in particular to Cobalt.
  • the semiconductor component 1 has a conductor layer 7, as shown in FIG. 3.
  • the conductor layer 7 is made of copper.
  • the conductor layer 7 can also consist at least partially of another material with high electrical conductivity.
  • the conductor layer 7 is formed in particular from a material which has a very small partial diffusion coefficient with respect to the material of the barrier layer 6.
  • the semiconductor component 1, as shown in FIG. 4, also has a protective layer 8.
  • the protective layer 8 surrounds the conductor layer 7.
  • the protective layer 8 is in particular made of silver. It can also be made of tin.
  • the protective layer 8 is corrosion-protective.
  • the interconnects 5, the barrier layer 6, the conductor layer 7 and the protective layer 8 form a multilayer contact structure 9.
  • the contact structure 9 is thus formed in particular four-layered.
  • the individual layers of the contact structure 9 have substantially the same width B as the conductor tracks 5.
  • the height of the contact structure 9 is the sum of the heights of the interconnects 5, the barrier layer 6, the conductor layer 7 and the protective layer 8.
  • Structure 9 thus has an aspect ratio AV KS , which is greater than the aspect ratio AV Lb of the interconnects 5.
  • the line resistance R KS of the individual tracks of the contact structure 9 is lower: this applies in particular as the line resistance R f of the conductor tracks 5.
  • the substrate 2 is provided and provided by means of a screen printing process on the front side 3 with the conductor tracks 5.
  • the conductor tracks 5 can also be arranged on the rear side 4 or on both sides 3, 4 of the substrate 2.
  • a first electrolytic deposition 11, the substrate 2, in particular the conductor tracks 5, is coated with the barrier layer 6.
  • electrolytically cobalt or nickel is deposited on the substrate 2 and the conductor tracks 5.
  • the galvanic coating achieves good adhesion of the barrier layer 6 on the substrate 2 and the printed conductors 5, without the wet-chemical process having to be interrupted by an annealing step. This allows a particularly cost-effective method.
  • the electrolytic deposition of the barrier layer 6 takes place in particular in Wattstype- baths which have a moderately acidic pH, in particular pH 3 to 5. These baths do not attack the printed conductors 5. Other baths with a pH greater than pH 3 may be used.
  • the Electrical potential for the electrolytic deposition of the barrier layer 6 can be generated by irradiating the substrate 2 with light of a suitable wavelength and intensity. Likewise, by this measure, the electrical resistance of the substrate can be reduced.
  • a second electrolytic deposition 12 the conductor layer 7 is applied to the barrier layer 6.
  • the semiconductor component 1 is immersed in a potential-controlled manner in an acid copper bath, that is to say the application of the potential already takes place before the wafers are immersed in the bath.
  • the second electrolytic deposition 12 the approximately 10 microns thick conductor layer 7 on the interconnects 5, but separated by the barrier layer 6 of these, deposited.
  • the electrolytic application of the conductor layer 7 in the second electrolytic deposition 12 is effected in particular by means of a pulse-plating process. This periodically switches between anodic and cathodic potentials. As a result, a periodic change of electrolytic deposition and dissolution takes place on the interconnects.
  • the pulse-plating method allows the deposition of very low-stress layers. Since higher field strengths prevail at the edges of the conductor tracks 5, the resolution rate is likewise increased there, which counteracts broadening of the conductor tracks 5.
  • the electrolytic deposition can be assisted by irradiation with light of suitable intensity and wavelength.
  • a protective coating 13 the semiconductor component 1 is immersed briefly in a silver bath, around the applied in the second electrodeposition 12 on the conductor tracks 5 conductor layer 7 with the anti-corrosive protective layer 8 from To coat silver.
  • the protective coating 13 may also be provided cheaper by means of electrolytic deposition of tin.
  • the contact structures 9 produced according to the invention have stable layers. Withdrawal tests have shown a very good adhesion of the contact structures 9 on the silicon substrate 2. The electrical losses in the individual tracks of the contact structure 9 are greatly reduced compared to those in the tracks 5. Overall, the inventive method leads to an increased aspect ratio AV K s of the individual tracks of the contact structure 9, which in turn leads to an increase of the
  • the process steps 11, 12 and 13 can be realized as a continuous process, that is, the wet-chemical or electrochemical process steps 11, 12 and 13 do not have to be interrupted by a temperature step. As a result, the method is particularly time-consuming and inexpensive.
  • the substrate 2 is first provided with an insulating layer 14.
  • the insulating layer 14 is made of, for example, silicon nitride or silicon dioxide.
  • the insulating layer 14 is selectively provided with contact openings 15.
  • the application of conductor tracks 5 can be omitted.
  • the barrier layer 6 and the conductor layer 7 according to the first embodiment can be applied.
  • the barrier layer 6 is in this embodiment in direct contact with the substrate 2. It prevents the diffusion of metal from the conductor layer 7 in the substrate 2. It also ensures good adhesion of the conductor layer 7 on the substrate second
  • a palladium seed layer having a thickness of a few nanometers is applied to the substrate at the locations where the barrier layer 6 and the conductor layer 7 are to be arranged.
  • the nucleation work is reduced in such a way that a homogeneous barrier layer 6 of nickel, cobalt or a nickel-cobalt alloy can be applied galvanically directly and without light support.
  • the barrier layer 6 in each case consists of ferromagnetic metals, it is provided according to the invention to reduce the nucleation work for the electrocrystallization by superposition of an inhomogeneous magnetic field and thus a homogeneous barrier layer 6 directly into the openings 15 of the insulating layer 14 galvanic deposit.

Abstract

A semiconductor component (1) comprises a substrate (2) having a first side (3) and a second side (4) and a multilayer contact structure (9) which is arranged on at least one side (3, 4) of the substrate (2), wherein the contact structure (9) has a barrier layer (6) for preventing the diffusion of ions from that side of the barrier layer (6) which is opposite the substrate (2) into the substrate (2).

Description

Kontakt-Struktur für ein Halbleiter-Bauelement sowie Verfahren zur Herstellung desselben Contact structure for a semiconductor device and method for producing the same
Die Erfindung betrifft ein Halbleiter-Bauelement sowie ein Verfahren zur Herstellung eines derartigen Halbleiter-Bauelements.The invention relates to a semiconductor device and a method for producing such a semiconductor device.
Üblicherweise haben Solarzellen einen frontseitigen Kontakt aus siebgedruckten Silber-Fingern. Diese haben eine typische Breite von 100 bis 120 μm und sind etwa 10 bis 15 μm dick. Da sich mit Siebdruck keine wesent- lieh höheren Aspektverhältnisse als etwa 0,1 erreichen lassen, kann die Fingerbreite nicht reduziert werden, ohne gleichzeitig den Linienwiderstand der Finger zu erhöhen. Andererseits sind die durch die Abschattung der Frontseite verursachten Verluste um so größer je breiter die frontseitigen Kontakte sind. Ein weiterer Nachteil sind die hohen Materialkosten der Silber-Kontakte.Typically, solar cells have a frontal contact of screen printed silver fingers. These have a typical width of 100 to 120 microns and are about 10 to 15 microns thick. Since screen printing does not allow for significantly higher aspect ratios than about 0.1, the finger width can not be reduced without simultaneously increasing the line resistance of the fingers. On the other hand, the losses caused by the shadowing of the front side are the greater the wider the front contacts are. Another disadvantage is the high material costs of the silver contacts.
Es wurden bereits unterschiedliche Methoden zur Verbesserung der Kontakttechnologie für Silizium-Substrat-Frontkontakte beschrieben.Various methods for improving the contact technology for silicon substrate front contacts have already been described.
Die EP 1 182 709 Al offenbart ein Verfahren zur Herstellung von Metallkontakten, bei welchem auf der Vorderseite eines Silizium-Substrats Gräben angeordnet werden, welche einen Metallkontakt aus einem Nickel- Kupfer-Schichtsystem aufnehmen. Ein Nachteil dieses Verfahrens ist der nötige Temperschritt nach der Nickel- Abscheidung.EP 1 182 709 A1 discloses a method for the production of metal contacts, in which trenches are arranged on the front side of a silicon substrate, which receive a metal contact from a nickel-copper layer system. A disadvantage of this method is the necessary annealing step after the nickel deposition.
In der DE 43 33 426 C l ist ein Verfahren zur lichtinduzierten Galvanik von Silizium-Substrakt-Kontakten beschrieben. Hierbei dient der Rückkontakt des Silizium-Substrats als Opferkathode. Die eingesetzten Chemikalien sind zyanid-haltig. DE 43 11 173 Al beschreibt ein Verfahren zur direkten Galvanik auf Siliziumoberflächen. Hierbei ist zunächst das Abscheiden einer Palladium- Keimschicht notwendig. Auf dieser erfolgt eine Nickel-Beschichtung, auf welche die eigentlich stromführende Kontaktschicht abgeschieden wird.In DE 43 33 426 C l a method for light-induced electroplating of silicon sub-tract contacts is described. Here, the back contact of the silicon substrate serves as a sacrificial cathode. The chemicals used are cyanide-containing. DE 43 11 173 Al describes a method for direct electroplating on silicon surfaces. Here, the deposition of a palladium seed layer is first necessary. This is followed by a nickel coating on which the actual current-carrying contact layer is deposited.
DE 10 2004 034 435 B4 beschreibt ein Verfahren zur lichtinduzierten Abscheidung eines Metallkontakts entlang einer Kante eines in die Oberfläche eines Halbleiter-Bauelementes eingebrachten Grabens.DE 10 2004 034 435 B4 describes a method for light-induced deposition of a metal contact along an edge of a trench introduced into the surface of a semiconductor component.
Die US 4,320,250 offenbart ein Silizium-Substrat mit einer Vielzahl von dicht aneinanderliegenden Elektroden, welche aus mehreren aufeinanderfolgenden Schichten bestehen, die zuerst mittels konventioneller Vakuum- beschichtungstechnik auf den Kontaktflächen des Silizium-Substrats abge- schieden und sodann in einem weiteren Verfahrensschritt durch einen GaI- vanik-Prozess erhöht werden. Dieses Verfahren ist sehr aufwendig.US Pat. No. 4,320,250 discloses a silicon substrate having a multiplicity of closely spaced electrodes, which consist of a plurality of successive layers which are first deposited on the contact surfaces of the silicon substrate by means of conventional vacuum coating technology and then, in a further process step, by a GaI process. vanik process be increased. This process is very expensive.
Die DE 198 31 529 Al betrifft ein Verfahren zum Herstellen einer Elektrode, welche durch Galvanoformung oder elektrostatische Pulverbeschich- tung auf spitzen- oder kantenförmige Vorsprünge auf einer Substratoberfläche aufgetragen wird. Daran anschließend sind eine Reihe chemischer Reaktionen und Prozess-Schritte notwendig, um die Elektrode fertig zu stellen.DE 198 31 529 A1 relates to a method for producing an electrode which is applied to tip-shaped or edge-shaped projections on a substrate surface by electroforming or electrostatic powder coating. After that, a series of chemical reactions and process steps are needed to complete the electrode.
Die DE 195 36 019 B4 beschreibt ein Verfahren zur Herstellung von feinen, diskreten Metallstrukturen, welche mittels photochemisch unterstützter Metallabscheidung auf einem photovoltaisch aktiven Halbleitermaterial erzeugt und anschließend vom Substrat abgelöst werden. Die bekannten Verfahren sind aufwendig und teuer.DE 195 36 019 B4 describes a method for the production of fine, discrete metal structures, which are produced by means of photochemically assisted metal deposition on a photovoltaically active semiconductor material and subsequently removed from the substrate. The known methods are complicated and expensive.
Der Erfindung liegt daher die Aufgabe zugrund, ein kostengünstiges Verfahren zur Herstellung einer Kontakt-Struktur mit einem hohen Aspekt- Verhältnis sowie ein Hableiter-Bauteil mit einer derartigen Kontakt- Struktur zu schaffen.The invention is therefore based on the object to provide a cost-effective method for producing a contact structure with a high aspect ratio and a Hableiter component with such a contact structure.
Diese Aufgabe wird durch die Merkmale der Ansprüche 1 und 7 gelöst. Der Kern der Erfindung besteht darin, zwischen ein Halbleiter- Substrat und eine Leiter-Schicht eine Sperr-Schicht zur Verhinderung der Diffusion von defekt-verursachenden Ionen aus der Leiter-Schicht in das Halbleiter- Substrat anzuordnen. Hierdurch wird die Auswahl für die zur Ausbildung der Leiter-Schicht zur Verfügung stehenden Materialien sehr erweitert. Außerdem lässt sich dadurch eine Kontakt- Struktur mit einem hohen As- pektverhältnis erreichen, wodurch sich die Verluste aufgrund der Abschattung der Frontseite durch die Kontakt- Struktur reduzieren. Weitere Vorteile ergeben sich aus den Unteransprüchen.This object is solved by the features of claims 1 and 7. The gist of the invention is to provide a barrier layer between a semiconductor substrate and a conductor layer for preventing the diffusion of defect-causing ions from the conductor layer into the semiconductor substrate. This greatly expands the choice of materials available to form the conductor layer. In addition, this makes it possible to achieve a contact structure with a high aspect ratio, which reduces the losses due to the shading of the front side by the contact structure. Further advantages emerge from the subclaims.
Merkmale und Einzelheiten der Erfindung ergeben sich aus der Beschrei- bung von Ausführungsbeispielen anhand der Zeichnungen. Es zeigen:Features and details of the invention will become apparent from the description of embodiments with reference to the drawings. Show it:
Fig. 1 einen schematischen, nicht maßstabgerechten Querschnitt durch ein Halbleiter-Bauelement mit aufgebrachten Leiterbahnen vor dem Aufbringen einer Sperr-Schicht,1 shows a schematic, not to scale cross-section through a semiconductor device with applied conductor tracks before the application of a barrier layer,
Fig. 2 einen Querschnitt gemäß Fig. 1 nach Aufbringen einer Sperr-Schicht jedoch vor Aufbringen einer Leiter- Schicht, - A -2 shows a cross section according to FIG. 1 after applying a barrier layer but before applying a conductor layer, FIG. - A -
F ig. 3 einen Querschnitt gemäß Fig. 2 nach Aufbringen einer Leiter- Schicht jedoch vor Aufbringen einer Schutz- Schicht,F ig. 3 shows a cross section according to FIG. 2 after application of a conductor layer but before application of a protective layer, FIG.
Fig. 4 einen Querschnitt gemäß Fig. 3 jedoch nach Aufbringen einer Schutz-Schicht,4 shows a cross section according to FIG. 3, however, after application of a protective layer, FIG.
Fig. 5 eine schematische Darstellung des Verfahrens zur Herstellung eines Halbleiter-Bauelements gemäß den Fig. 1 bis 4 undFig. 5 is a schematic representation of the method for producing a semiconductor device according to FIGS. 1 to 4 and
Fig. 6 einen schematischen, nicht maßstabgerechten Querschnitt durch eine weitere Ausfi dem Aufbringen von Leiterbahnen.Fig. 6 is a schematic, not to scale cross section through a further Ausfi the application of printed conductors.
Im Folgenden wird unter Bezugnahme auf die Fig. 1 bis 4 ein erfindungsgemäßes Halbleiter-Bauelement beschrieben. Als Ausgangspunkt weist ein Halbleiter-Bauelement 1 ein Substrat 2 auf. Als Substrat 2 dient insbesondere ein Silizium-Substrat. Als Substrat 2 kann jedoch ebenso ein anderes Halbleiter-Substrat dienen. Das Substrat 2 ist im Wesentlichen flächig ausgebildet mit einer ersten Seite und einer dieser gegenüberliegenden zweiten Seite. Die erste Seite bildet hierbei eine Vorderseite 3, während die zweite Seite eine Rückseite 4 des Substrats 2 bildet. Das Substrat 2 besteht zumindest teilweise aus Silizium. Auf der Vorderseite 3 des Substrats 2 ist eine Vielzahl von Leiterbahnen 5 vorgesehen. Die Leiterbahnen 5 haben seitliche Flanken 16, welche einen Winkel b mit der Vorderseite 3 des Substrats 2 einschließen. Der Winkel b beträgt mindestens 90°. Der Winkel b ist ins- besondere größer als 90°, insbesondere größer als 100°. Die Flanken 16 der Leiterbahn 5 sind somit vorzugsweise aufeinander zulaufend ausgebildet, was zu einer besonders geringen Abschattung führt. Die Leiterbahnen 5 können jedoch ebenso auf der Rückseite 4 angeordnet sein. Die Leiterbahnen 5 stehen in elektrischem Kontakt mit dem Substrat 2. Die Leiterbahnen 5 sind aus einem elektrisch leitenden Material, insbesondere einem Metall, welches einen äußerst geringen Diffusionskoeffizienten in Bezug auf das Material des Substrats 2 aufweist. Die Leiterbahnen 5 weisen insbesondere einen hohen Silberanteil auf. Sie können auch vollständig aus reinem Silber bestehen. Die Leiterbahnen 5 haben eine Breite B parallel zur Vorderseite 3 des Silizium-Substrats 2, welche möglichst klein ist, um eine Abschattung der Vorderseite 3 durch die Leiterbahnen 5 zu reduzieren. Die Leiterbahnen 5 haben eine Höhe H senkrecht zur Vorderseite 3, welche möglichst groß ist, um den Linienwiderstand der Leiterbahnen 5 zu reduzieren. Die Leiterbahnen 5 stehen somit um die Höhe H von der Vorderseite 3 vor. Die seitlichen Flanken 16 sind somit über ihre gesamte Erstreckung freiliegend. Üblicherweise liegt die Breite B der Leiterbahnen 5 im Bereich von 10 μm bis 200 μm, insbesondere im Bereich von 100 μm bis 120 μm. Die Höhe H der Leiterbahnen 5 liegt üblicherweise im Bereich von 1 μm bis 50 μm, insbesondere im Bereich von 5 μm bis 15 μm. Das als Höhe zu Breite definierte Aspektverhältnis AVLb = H/B der siebgedruckten Leiterbahnen 5 beträgt etwa 0, 1. Derartige Leiterbahnen 5 haben üblicherweise einen Linienwiderstand R|f von etwa 40 Ω/m. Der Linienwiderstand Rif kann jedoch auch deutlich höher sein.In the following, a semiconductor device according to the invention will be described with reference to FIGS. As a starting point, a semiconductor component 1 has a substrate 2. As a substrate 2 is used in particular a silicon substrate. As substrate 2, however, another semiconductor substrate may serve as well. The substrate 2 is substantially flat with a first side and a second side opposite thereto. The first side forms a front side 3, while the second side forms a back side 4 of the substrate 2. The substrate 2 consists at least partially of silicon. On the front side 3 of the substrate 2, a plurality of conductor tracks 5 is provided. The conductor tracks 5 have lateral flanks 16, which enclose an angle b with the front side 3 of the substrate 2. The angle b is at least 90 °. The angle b is in particular greater than 90 °, in particular greater than 100 °. The flanks 16 of the conductor track 5 are thus preferably designed to converge, which leads to a particularly low shading. However, the conductor tracks 5 can also be arranged on the back 4. The conductor tracks 5 are in electrical contact with the substrate 2. The conductor tracks 5 are made of an electrically conductive material, in particular a metal, which has an extremely low diffusion coefficient with respect to the material of the substrate 2. The interconnects 5 have in particular a high silver content. They can also be made entirely of pure silver. The interconnects 5 have a width B parallel to the front side 3 of the silicon substrate 2, which is as small as possible in order to reduce shading of the front side 3 by the interconnects 5. The interconnects 5 have a height H perpendicular to the front side 3, which is as large as possible in order to reduce the line resistance of the interconnects 5. The conductor tracks 5 are thus projected by the height H from the front side 3. The lateral flanks 16 are thus exposed over their entire extent. Usually, the width B of the conductor tracks 5 is in the range of 10 .mu.m to 200 .mu.m, in particular in the range of 100 .mu.m to 120 .mu.m. The height H of the conductor tracks 5 is usually in the range of 1 .mu.m to 50 .mu.m, in particular in the range of 5 .mu.m to 15 .mu.m. The aspect ratio ΔV Lb = H / B of the screen-printed interconnects 5 defined as the height-to-width is approximately 0, 1. Such interconnects 5 usually have a line resistance R | f of about 40 Ω / m. However, the line resistance Ri f can also be significantly higher.
Nach einem ersten Prozess-Schritt weist das Halbleiter-Bauelement 1 wie in Fig. 2 dargestellt eine Sperr-Schicht 6 auf. Die Sperr-Schicht 6 umgibt insbesondere die Leiterbahn 5. Die Dicke der Sperr-Schicht 6 beträgt 0,1 bis 5 μm, insbesondere 0,2 bis 1 μm. Die Sperr-Schicht 6 ist aus einem Material, insbesondere einem Metall, welches einen vernachlässigbaren Diffusionskoeffizienten bzw. eine vernachlässigbare Mischbarkeit in Bezug auf das Material der Leiterbahnen 5 und der Leiter-Schicht 7 besitzt. Die Sperr-Schicht 6 ist insbesondere aus elektrolytisch oder chemisch aufgebrachtem Kobalt. Sie kann auch aus Nickel bestehen, das elektrolytisch aufgebracht ist. Andere Materialien sind ebenfalls denkbar. Die Sperr- Schicht 6 hat vorteilhafterweise eine hohe elektrische Leitfähigkeit. Vorteilhafterweise lässt sich das Metall der Sperr-Schicht zum Reinigen der Kontaktrollen gut elektrochemisch strippen. Dies gilt insbesondere für Ko- balt.After a first process step, the semiconductor component 1 has a blocking layer 6, as shown in FIG. 2. The barrier layer 6 in particular surrounds the conductor track 5. The thickness of the barrier layer 6 is 0.1 to 5 μm, in particular 0.2 to 1 μm. The barrier layer 6 is made of a material, in particular a metal, which has a negligible diffusion coefficient or a negligible miscibility with respect to the material of the conductor tracks 5 and the conductor layer 7. The barrier layer 6 is in particular made of electrolytically or chemically applied cobalt. It can also consist of nickel, the electrolytic is applied. Other materials are also conceivable. The barrier layer 6 advantageously has a high electrical conductivity. Advantageously, the metal of the barrier layer can be well electrochemically stripped to clean the contact rollers. This applies in particular to Cobalt.
Nach einem weiteren Prozess-Schritt weist das Halbleiter-Bauelement 1 wie in Fig. 3 gezeigt eine Leiter- Schicht 7 auf. Die Leiter- Schicht 7 ist aus Kupfer. Die Leiter- Schicht 7 kann auch zumindest teilweise aus einem an- deren Material mit hoher elektrischer Leitfähigkeit bestehen. Die Leiter- Schicht 7 ist insbesondere aus einem Material ausgebildet, welches einen sehr kleinen partiellen Diffusionskoeffizienten in Bezug auf das Material der Sperr-Schicht 6 aufweist. Vorteilhafterweise besteht zwischen dem Material der Sperr-Schicht 6 einerseits und dem Material der Leiter-Schicht 7 andererseits nur eine sehr geringe Mischbarkeit.After a further process step, the semiconductor component 1 has a conductor layer 7, as shown in FIG. 3. The conductor layer 7 is made of copper. The conductor layer 7 can also consist at least partially of another material with high electrical conductivity. The conductor layer 7 is formed in particular from a material which has a very small partial diffusion coefficient with respect to the material of the barrier layer 6. Advantageously, there is only a very low miscibility between the material of the barrier layer 6 on the one hand and the material of the conductor layer 7 on the other hand.
Nach einem weiteren Prozess-Schritt weist das Halbleiter-Bauelement 1 wie in Fig. 4 dargestellt außerdem eine Schutz-Schicht 8 auf. Die Schutz- Schicht 8 umgibt die Leiter-Schicht 7. Die Schutz- Schicht 8 ist insbesonde- re aus Silber. Sie kann auch aus Zinn sein. Die Schutz-Schicht 8 ist korro- sions-schützend.After a further process step, the semiconductor component 1, as shown in FIG. 4, also has a protective layer 8. The protective layer 8 surrounds the conductor layer 7. The protective layer 8 is in particular made of silver. It can also be made of tin. The protective layer 8 is corrosion-protective.
Insgesamt bilden die Leiterbahnen 5, die Sperr-Schicht 6, die Leiter- Schicht 7 und die Schutz-Schicht 8 eine mehrschichtige Kontakt- Struktur 9. Die Kontakt-Struktur 9 ist somit insbesondere vierschichtig ausgebildet. Die einzelnen Schichten der Kontakt-Struktur 9 weisen im Wesentlichen die gleiche Breite B wie die Leiterbahnen 5 auf. Die Höhe der Kontakt- Struktur 9 ist jedoch die Summe der Höhen der Leiterbahnen 5, der Sperr- Schicht 6, der Leiter-Schicht 7 und der Schutz-Schicht 8. Die Kontakt- Struktur 9 weist somit ein Aspektverhältnis AVKS auf, welches größer als das Aspektverhältnis AVLb der Leiterbahnen 5 ist. Hierbei gilt insbesondere: AVKs/AVLb > 1,5, insbesondere AVKs/AVLb > 2, insbesondere AVκs/AVLb ≥ 4. Dementsprechend ist der Linienwiderstand RKS der ein- zelnen Bahnen der Kontakt- Struktur 9 niedriger als der Linienwiderstand Rif der Leiterbahnen 5. Hierbei gilt insbesondere RKs/Rif ≤ 0,5, insbesondere RKs/Rif ≤ 0,3, insbesondere RKs/Rif ≤ 0,2.Overall, the interconnects 5, the barrier layer 6, the conductor layer 7 and the protective layer 8 form a multilayer contact structure 9. The contact structure 9 is thus formed in particular four-layered. The individual layers of the contact structure 9 have substantially the same width B as the conductor tracks 5. However, the height of the contact structure 9 is the sum of the heights of the interconnects 5, the barrier layer 6, the conductor layer 7 and the protective layer 8. Structure 9 thus has an aspect ratio AV KS , which is greater than the aspect ratio AV Lb of the interconnects 5. / K s AV AV Lb> 1.5, in particular AV K s / AV Lb> 2, in particular AVκs / AV Lb ≥ 4. Accordingly, the line resistance R KS of the individual tracks of the contact structure 9 is lower: this applies in particular as the line resistance R f of the conductor tracks 5. This applies in particular R K s / Ri f ≤ 0.5, in particular R K s / Ri f ≤ 0.3, in particular R K s / Ri f ≤ 0.2.
Im Folgenden wird unter Bezugnahme auf die Fig. 5 das Verfahren zur Herstellung des Halbleiter-Bauelementes 1, insbesondere zur Herstellung der Kontakt-Struktur 9 beschrieben. In einem ersten Verfahrensschritt 10 wird das Substrat 2 bereitgestellt und mittels eines Siebdruck- Verfahrens auf der Vorderseite 3 mit den Leiterbahnen 5 versehen. Die Leiterbahnen 5 können auch auf der Rückseite 4 oder auf beiden Seiten 3, 4 des Substrats 2 angeordnet werden.The method for producing the semiconductor component 1, in particular for producing the contact structure 9, will be described below with reference to FIG. 5. In a first method step 10, the substrate 2 is provided and provided by means of a screen printing process on the front side 3 with the conductor tracks 5. The conductor tracks 5 can also be arranged on the rear side 4 or on both sides 3, 4 of the substrate 2.
In einem weiteren Verfahrensschritt, einer ersten elektrolytischen Abscheidung 11, wird das Substrat 2, insbesondere die Leiterbahnen 5, mit der Sperr-Schicht 6 überzogen. Hierzu wird elektrolytisch Kobalt oder Nickel auf dem Substrat 2 und den Leiterbahnen 5 abgeschieden. Durch die galvanische Beschichtung wird eine gute Haftung der Sperr-Schicht 6 auf dem Substrat 2 und den Leiterbahnen 5 erreicht, ohne dass das nass-chemische Verfahren durch einen Temperschritt unterbrochen werden müsste. Dies ermöglicht ein besonders kostengünstiges Verfahren. Die elektrolytische Abscheidung der Sperr-Schicht 6 erfolgt insbesondere in Wattstype- Bädern, die einen moderat sauren pH- Wert, insbesondere pH 3 bis 5 aufweisen. Diese Bäder greifen die Leiterbahnen 5 nicht an. Es können auch andere Bäder mit einem pH- Wert größer pH 3 verwendet werden. Das elektrische Potenzial für die elektrolytische Abscheidung der Sperr-Schicht 6 kann durch Bestrahlung des Substrats 2 mit Licht einer geeigneten Wellenlänge und Intensität erzeugt werden. Ebenso kann durch diese Maßnahme der elektrische Widerstand des Substrates reduziert werden.In a further method step, a first electrolytic deposition 11, the substrate 2, in particular the conductor tracks 5, is coated with the barrier layer 6. For this purpose, electrolytically cobalt or nickel is deposited on the substrate 2 and the conductor tracks 5. The galvanic coating achieves good adhesion of the barrier layer 6 on the substrate 2 and the printed conductors 5, without the wet-chemical process having to be interrupted by an annealing step. This allows a particularly cost-effective method. The electrolytic deposition of the barrier layer 6 takes place in particular in Wattstype- baths which have a moderately acidic pH, in particular pH 3 to 5. These baths do not attack the printed conductors 5. Other baths with a pH greater than pH 3 may be used. The Electrical potential for the electrolytic deposition of the barrier layer 6 can be generated by irradiating the substrate 2 with light of a suitable wavelength and intensity. Likewise, by this measure, the electrical resistance of the substrate can be reduced.
In einem weiteren Verfahrensschritt, einer zweiten elektrolytischen Abscheidung 12, wird die Leiter-Schicht 7 auf die Sperr-Schicht 6 aufgebracht. Hierzu wird das Halbleiter-Bauelement 1 potentialkontrolliert in ein saures Kupfer-Bad eingetaucht, das heißt das Anlegen des Potentials ge- schieht bereits vor Eintauchen der Wafer in das Bad. Bei der zweiten elektrolytischen Abscheidung 12 wird die ca. 10 μm dicke Leiter-Schicht 7 auf den Leiterbahnen 5, jedoch durch die Sperr-Schicht 6 von diesen getrennt, abgeschieden. Das elektrolytische Aufbringen der Leiter- Schicht 7 bei der zweiten elektrolytischen Abscheidung 12 geschieht insbesondere mittels eines Pulse-Plating- Verfahrens. Hierbei wird periodisch zwischen anodischen und kathodischen Potentialen gewechselt. Hierdurch findet ein periodischer Wechsel von elektrolytischer Abscheidung und Auflösung an den Leiterbahnen statt. Außerdem erlaubt das Pulse-Plating-V erfahren die Abscheidung sehr spannungsarmer Schichten. Da an den Kanten der Leiter- bahnen 5 höhere Feldstärken herrschen, ist dort die Auflöserate ebenfalls erhöht, was einer Verbreiterung der Leiterbahnen 5 entgegenwirkt. Die elektrolytische Abscheidung ist durch Bestrahlung mit Licht geeigneter Intensität und Wellenlänge unterstützbar.In a further method step, a second electrolytic deposition 12, the conductor layer 7 is applied to the barrier layer 6. For this purpose, the semiconductor component 1 is immersed in a potential-controlled manner in an acid copper bath, that is to say the application of the potential already takes place before the wafers are immersed in the bath. In the second electrolytic deposition 12, the approximately 10 microns thick conductor layer 7 on the interconnects 5, but separated by the barrier layer 6 of these, deposited. The electrolytic application of the conductor layer 7 in the second electrolytic deposition 12 is effected in particular by means of a pulse-plating process. This periodically switches between anodic and cathodic potentials. As a result, a periodic change of electrolytic deposition and dissolution takes place on the interconnects. In addition, the pulse-plating method allows the deposition of very low-stress layers. Since higher field strengths prevail at the edges of the conductor tracks 5, the resolution rate is likewise increased there, which counteracts broadening of the conductor tracks 5. The electrolytic deposition can be assisted by irradiation with light of suitable intensity and wavelength.
In einem weiteren Verfahrensschritt, einer Schutz-Beschichtung 13, wird das Halbleiter-Bauelement 1 kurz in ein Silber-Bad eingetaucht, um die in der zweiten elektrolytischen Abscheidung 12 auf den Leiterbahnen 5 aufgebrachte Leiter- Schicht 7 mit der korrosionsschützenden Schutz- Schicht 8 aus Silber zu überziehen. Alternativ hierzu kann die Schutz-Beschichtung 13 auch kostengünstiger mittels elektrolytischer Abscheidung von Zinn vorgesehen sein.In a further method step, a protective coating 13, the semiconductor component 1 is immersed briefly in a silver bath, around the applied in the second electrodeposition 12 on the conductor tracks 5 conductor layer 7 with the anti-corrosive protective layer 8 from To coat silver. Alternatively, the protective coating 13 may also be provided cheaper by means of electrolytic deposition of tin.
Die erfindungsgemäß hergestellten Kontakt- Strukturen 9 haben stabile Schichten. Abzugstests haben eine sehr gute Haftfestigkeit der Kontakt- Strukturen 9 auf dem Silizium-Substrat 2 ergeben. Die elektrischen Verluste in den einzelnen Bahnen der Kontakt-Struktur 9 sind gegenüber denen in den Leiterbahnen 5 stark reduziert. Insgesamt fuhrt das erfindungsgemäße Verfahren zu einem vergrößerten Aspektverhältnis AVKs der einzelnen Bahnen der Kontakt- Struktur 9, was wiederum zu einer Steigerung desThe contact structures 9 produced according to the invention have stable layers. Withdrawal tests have shown a very good adhesion of the contact structures 9 on the silicon substrate 2. The electrical losses in the individual tracks of the contact structure 9 are greatly reduced compared to those in the tracks 5. Overall, the inventive method leads to an increased aspect ratio AV K s of the individual tracks of the contact structure 9, which in turn leads to an increase of the
Wirkungsgrades einer Solarzelle mit derartigen Kontakt-Strukturen 9 führt. Die Verfahrensschritte 11, 12 und 13 lassen sich als kontinuierliches Verfahren verwirklichen, das heißt die nasschemischen bzw. elektrochemischen Verfahrensschritte 11,12 und 13 müssen nicht durch einen Tem- perschritt unterbrochen werden. Hierdurch ist das Verfahren besonders zeit- und kostengünstig.Efficiency of a solar cell with such contact structures 9 leads. The process steps 11, 12 and 13 can be realized as a continuous process, that is, the wet-chemical or electrochemical process steps 11, 12 and 13 do not have to be interrupted by a temperature step. As a result, the method is particularly time-consuming and inexpensive.
Im Folgenden wird unter Bezugnahme auf die Fig. 6 eine weitere Ausführungsform des Halbleiter-Bauelements Ia beschrieben. Identische Teile erhalten dieselben Bezugszeichen wie bei dem ersten Ausführungsbeispiel, auf dessen Beschreibung hiermit verwiesen wird. Der zentrale Unterschied gegenüber dem ersten Ausführungsbeispiel besteht darin, dass das Substrat 2 zunächst mit einer isolierenden Schicht 14 versehen wird. Die isolierende Schicht 14 ist beispielsweise aus Siliziumnitrid oder Siliziumdioxid. An den Stellen, an welchen die Sperr-Schicht 6 und die Leiter-Schicht 7 angeordnet werden sollen, wird die isolierende Schicht 14 selektiv mit Kontakt- Öffnungen 15 versehen. Das Aufbringen von Leiterbahnen 5 kann entfallen. Zum Herstellen der Kontakt-Öffnungen 15 in der isolierenden SchichtIn the following, a further embodiment of the semiconductor device Ia will be described with reference to FIG. Identical parts are given the same reference numerals as in the first embodiment, to the description of which reference is hereby made. The main difference with respect to the first embodiment is that the substrate 2 is first provided with an insulating layer 14. The insulating layer 14 is made of, for example, silicon nitride or silicon dioxide. At the locations where the barrier layer 6 and the conductor layer 7 are to be arranged, the insulating layer 14 is selectively provided with contact openings 15. The application of conductor tracks 5 can be omitted. For producing the contact openings 15 in the insulating layer
14 ist ein Laser-, Plasma- oder ein nasschemischer oder ein Pasten- Ätzprozess vorgesehen. Nach dem Öffnen der isolierenden Schicht 14 können die Sperr-Schicht 6 und die Leiter- Schicht 7 gemäß dem ersten Ausführungsbeispiel aufgebracht werden.14 is a laser, plasma or wet-chemical or paste Etching process provided. After opening the insulating layer 14, the barrier layer 6 and the conductor layer 7 according to the first embodiment can be applied.
Die Sperr-Schicht 6 ist bei diesem Ausführungsbeispiel in direktem Kontakt mit dem Substrat 2. Sie verhindert die Diffusion von Metall aus der Leiter-Schicht 7 in das Substrat 2. Sie sorgt darüber hinaus für eine gute Haftung der Leiter-Schicht 7 auf dem Substrat 2.The barrier layer 6 is in this embodiment in direct contact with the substrate 2. It prevents the diffusion of metal from the conductor layer 7 in the substrate 2. It also ensures good adhesion of the conductor layer 7 on the substrate second
In einem weiteren Ausführungsbeispiel wird eine Palladiumkeimschicht mit einer Dicke von wenigen Nanometern an den Stellen, an welchen die Sperr-Schicht 6 und die Leiter-Schicht 7 angeordnet werden sollen, auf das Substrat aufgebracht. Hierdurch wird die Keimbildungsarbeit dergestalt verringert, dass eine homogene Sperr-Schicht 6 aus Nickel, Kobalt oder einer Nickel-Kobalt-Legierung direkt und ohne Lichtunterstützung galvanisch aufgebracht werden kann. Selbstverständlich kann auch auf die PaI- ladiumbekeimung verzichtet werden, wenn die galvanische Abscheidung der Sperr-Schicht 6 mit Lichtunterstützung durchgeführt wird. Da die Sperr-Schicht 6 in jedem Falle aus ferromagnetischen Metallen besteht, ist erfindungsgemäß vorgesehen, die Keimbildungsarbeit für die Elektrokris- tallisation durch Überlagern eines inhomogenen Magnetfeldes zu reduzieren und somit eine homogene Sperr-Schicht 6 direkt in die Öffnungen 15 der isolierenden Schicht 14 galvanisch abzuscheiden. In another embodiment, a palladium seed layer having a thickness of a few nanometers is applied to the substrate at the locations where the barrier layer 6 and the conductor layer 7 are to be arranged. As a result, the nucleation work is reduced in such a way that a homogeneous barrier layer 6 of nickel, cobalt or a nickel-cobalt alloy can be applied galvanically directly and without light support. Of course, it is also possible to dispense with palladium nucleation if the galvanic deposition of the barrier layer 6 is carried out with light assistance. Since the barrier layer 6 in each case consists of ferromagnetic metals, it is provided according to the invention to reduce the nucleation work for the electrocrystallization by superposition of an inhomogeneous magnetic field and thus a homogeneous barrier layer 6 directly into the openings 15 of the insulating layer 14 galvanic deposit.

Claims

Patentansprüche claims
1. Halbleiter-Bauelement ( 1 ) umfassend a) ein Substrat (2) mit einer ersten Seite (3) und einer zweiten Seite (4) und b) einer auf mindestens einer Seite (3, 4) des Substrats (2) angeordneten mehrschichtigen Kontakt- Struktur (9), c) wobei die Kontakt- Struktur (9) eine Sperr-Schicht (6) zur Verhinderung der Diffusion von Ionen von der dem Substrat (2) abgewand- ten Seite der Sperr-Schicht (6) in das Substrat (2) aufweist.A semiconductor device (1) comprising a) a substrate (2) having a first side (3) and a second side (4) and b) a multilayered one disposed on at least one side (3, 4) of the substrate (2) Contact structure (9), c) wherein the contact structure (9) has a barrier layer (6) for preventing the diffusion of ions from the side of the barrier layer (6) facing away from the substrate (2) Substrate (2).
2. Halbleiter-Bauelement (1) gemäß Anspruch 1, dadurch gekennzeichnet, dass die Kontakt- Struktur (9) eine Vielzahl von Leiterbahnen (5), welche um eine Höhe H von der ersten Seite (3) des Substrats (2) vor- stehen, aufweist.2. Semiconductor component (1) according to claim 1, characterized in that the contact structure (9) has a multiplicity of conductor tracks (5), which are projected by a height H from the first side (3) of the substrate (2). standing, has.
3. Halbleiter-Bauelement (1) gemäß Anspruch 2, dadurch gekennzeichnet, dass die Höhe H der Leiterbahnen (5) im Bereich von 1 μm bis 50 μm, insbesondere im Bereich von 5 μm bis 15 μm liegt.3. semiconductor device (1) according to claim 2, characterized in that the height H of the conductor tracks (5) in the range of 1 .mu.m to 50 .mu.m, in particular in the range of 5 microns to 15 microns.
4. Halbleiter-Bauelement (1) gemäß einem der vorangehenden Ansprüche, dadurch gekennzeichnet, dass die Sperr-Schicht (6) zumindest teilweise aus Kobalt und/oder Nickel ausgebildet ist.4. Semiconductor component (1) according to one of the preceding claims, characterized in that the barrier layer (6) is formed at least partially of cobalt and / or nickel.
5. Halbleiter-Bauelement (1) gemäß einem der vorangehenden Ansprüche, dadurch gekennzeichnet, dass die Sperr-Schicht (6) eine Dicke von 0,1 μm bis 5 μm, insbesondere von 0,2 μm bis 1 μm aufweist. 5. semiconductor device (1) according to one of the preceding claims, characterized in that the barrier layer (6) has a thickness of 0.1 .mu.m to 5 .mu.m, in particular from 0.2 .mu.m to 1 .mu.m.
6. Halbleiter-Bauelement (1) gemäß einem der vorangehenden Ansprüche, dadurch gekennzeichnet, dass die Kontakt-Struktur (9) eine auf der Sperr-Schicht (6) angeordnete Leiter-Schicht (7) umfasst.6. Semiconductor component (1) according to one of the preceding claims, characterized in that the contact structure (9) on the barrier layer (6) arranged conductor layer (7).
7. Halbleiter-Bauelement (1) gemäß Anspruch 6, dadurch gekennzeichnet, dass die Leiter- Schicht (7) zumindest teilweise aus Kupfer ausgebildet ist.7. Semiconductor component (1) according to claim 6, characterized in that the conductor layer (7) is at least partially formed from copper.
8. Halbleiter-Bauelement (1) gemäß einem der vorangehenden Ansprü- che, dadurch gekennzeichnet, dass die Kontakt- Struktur (9) ein Aspektverhältnis A VKS von mindestens 0,1, insbesondere mindestens 0,2, insbesondere mindestens 0,4, aufweist.8. Semiconductor component (1) according to one of the preceding claims, characterized in that the contact structure (9) has an aspect ratio AV KS of at least 0.1, in particular at least 0.2, in particular at least 0.4 ,
9. Halbleiter-Bauelement (1) gemäß einem der Ansprüche 2 bis 8, da- durch gekennzeichnet, dass die Leiterbahnen (5) ein Aspektverhältnis9. The semiconductor device (1) according to any one of claims 2 to 8, character- ized in that the conductor tracks (5) has an aspect ratio
AVLb aufweisen, und die Kontakt- Struktur (9) ein Aspektverhältnis AVKs aufweist, wobei gilt AVKs/AVLb > 1, 5, insbesondere AVKs/AVLb > 2, insbesondere AVKs/AVLb > 4.AV Lb , and the contact structure (9) has an aspect ratio AV K s, where AV K s / AV Lb > 1, 5, in particular AV K s / AV Lb > 2, in particular AV K s / AV Lb > 4th
10. Verfahren zur Herstellung eines Halbleiter-Bauelements (1) gemäß einem der vorangehenden Ansprüche umfassend die folgenden Schritte:10. A method for producing a semiconductor device (1) according to one of the preceding claims comprising the following steps:
- Bereitstellen eines Substrats (2),Providing a substrate (2),
- Aufbringen einer Sperr-Schicht (6) auf das Substrat (2) und - Aufbringen einer Leiter-Schicht (7) auf die Sperr-Schicht (6).- Applying a barrier layer (6) on the substrate (2) and - applying a conductor layer (7) on the barrier layer (6).
11. Verfahren gemäß Anspruch 10, dadurch gekennzeichnet, dass das Substrat (2) in einem ersten Verfahrensschritt (10) mit Leiterbahnen (5) versehen wird. 11. The method according to claim 10, characterized in that the substrate (2) in a first method step (10) is provided with conductor tracks (5).
12. Verfahren gemäß einem der Ansprüche 10 bis 11, dadurch gekennzeichnet, dass das Aufbringen mindestens einer der Schichten (6, 7) mittels elektrolytischer Abscheidung geschieht.12. The method according to any one of claims 10 to 11, characterized in that the application of at least one of the layers (6, 7) takes place by means of electrolytic deposition.
B.Verfahren gemäß einem der Ansprüche 10 bis 12, dadurch gekennzeichnet, dass das Aufbringen mindestens einer der Schichten (6, 7) mittels lichtinduzierter Galvanik erfolgt.B.Verfahren according to one of claims 10 to 12, characterized in that the application of at least one of the layers (6, 7) takes place by means of light-induced electroplating.
H.Verfahren gemäß Anspruch 13, dadurch gekennzeichnet, dass das Aufbringen der Sperr-Schicht (6) auf das Substrat (2), das Aufbringen der Leiter-Schicht (7) auf die Sperr-Schicht (6) und das Aufbringen einer Schutz-Schicht (8) als kontinuierliches, von Temperschritten ununterbrochenes Verfahren verwirklicht ist.H. Method according to claim 13, characterized in that the application of the barrier layer (6) to the substrate (2), the application of the conductor layer (7) to the barrier layer (6) and the application of a protective Layer (8) is implemented as a continuous, uninterrupted by Temperschritten process.
15. Verfahren gemäß einem der Ansprüche 10 bis 14, dadurch gekennzeichnet, dass das Aufbringen der Sperr-Schicht (6) durch Überlagerung eines inhomogenen Magnetfeldes unterstützt wird. 15. The method according to any one of claims 10 to 14, characterized in that the application of the barrier layer (6) is supported by superposition of an inhomogeneous magnetic field.
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US20100181670A1 (en) 2010-07-22
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JP5377478B2 (en) 2013-12-25
CN101743639A (en) 2010-06-16
WO2009006988A1 (en) 2009-01-15
DE102007031958A1 (en) 2009-01-15

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