EP2162914A2 - Hf-leistungstransistorgehäuse mit interner oberschwingungsfrequenzverringerung und verfahren zur herstellung von hf-leistungstransistorgehäusen mit interner oberschwingungsfrequenzverringerung - Google Patents

Hf-leistungstransistorgehäuse mit interner oberschwingungsfrequenzverringerung und verfahren zur herstellung von hf-leistungstransistorgehäusen mit interner oberschwingungsfrequenzverringerung

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Publication number
EP2162914A2
EP2162914A2 EP08767893A EP08767893A EP2162914A2 EP 2162914 A2 EP2162914 A2 EP 2162914A2 EP 08767893 A EP08767893 A EP 08767893A EP 08767893 A EP08767893 A EP 08767893A EP 2162914 A2 EP2162914 A2 EP 2162914A2
Authority
EP
European Patent Office
Prior art keywords
transistor
harmonic
output
packaged
output terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP08767893A
Other languages
English (en)
French (fr)
Inventor
Donald Farrell
Simon Wood
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wolfspeed Inc
Original Assignee
Cree Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cree Inc filed Critical Cree Inc
Publication of EP2162914A2 publication Critical patent/EP2162914A2/de
Ceased legal-status Critical Current

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Definitions

  • This invention relates generally to RF and microwave transistors, and more particularly the invention relates to methods for improving linearity of packaged RF power transistors, and packaged RF power transistors having improved linearity.
  • a packaged RF power device includes a transistor including a control terminal and an output terminal and configured to operate at a fundamental operating frequency, an RF signal input lead coupled to the control terminal of the transistor, and an RF signal output lead coupled to the output terminal of the transistor.
  • the packaged device further includes a harmonic reducer coupled to the control terminal and/or the output terminal of the transistor and configured to provide a short circuit or low impedance path from the control terminal and/or the output terminal to ground for signals at a harmonic frequency of the fundamental operating frequency.
  • the device further includes a package that houses the transistor and the harmonic reducer, with the RF signal input lead and the RF signal output lead extending from the package.
  • the harmonic frequency may, for example, include a second harmonic frequency.
  • the harmonic reducer may be coupled to the control terminal, and the packaged RF power device may further include an output-side harmonic reducer connected to the output terminal of the transistor.
  • the harmonic reducer may include a first capacitor having a first capacitance
  • the output-side harmonic reducer may include a second capacitor having a second capacitance that is different from the first capacitance.
  • the packaged RF power device may further include an input matching circuit between the RF signal input lead and the control terminal of the transistor.
  • the harmonic reducer may be coupled between the input matching circuit and the control terminal of the transistor.
  • the harmonic reducer may include a series resonant circuit including an inductive element and a shunt capacitor connected in series to a ground terminal.
  • the packaged RF power device may further include a base.
  • the transistor is on the base and the shunt capacitor may be on the base between the transistor and the RF output lead.
  • the inductive element may include a bond wire extending from the transistor to the shunt capacitor.
  • the packaged RF power device may further include a second bond wire extending over the shunt capacitor from the transistor to the RF output lead.
  • the harmonic reducer may include an open circuit quarter- wave transmission line stub.
  • the open circuit quarter- wave transmission line stub may have a length selected to provide a short circuit or low impedance path to ground for signals at the harmonic frequency of the fundamental operating frequency.
  • a packaged RF power device includes a transistor including a control terminal and an output terminal and configured to operate at a fundamental operating frequency, an RF signal input lead coupled to the control terminal of the transistor, and an RF signal output lead coupled to the output terminal of the transistor.
  • a harmonic reducer is coupled to the control terminal and/or the output terminal of the transistor and is configured to provide a short circuit or low impedance path from the control terminal and/or the output terminal to ground for signals at an Nth harmonic frequency of the fundamental operating frequency, where N>1.
  • the device further includes a package that houses the transistor, the ground terminal and the harmonic reducer, with the input lead and the output lead extending from the package.
  • the packaged RF power device may further include a further harmonic reducer housed in the package and coupled to the control terminal and/or the output terminal of the transistor.
  • the further harmonic reducer is configured to provide a second short circuit or low impedance path from the control terminal and/or the second output terminal to ground for signals at an Mth harmonic frequency of the fundamental operating frequency, where M>1 and M ⁇ N.
  • the harmonic reducer and the further harmonic reducer can each include a series resonant circuit including an inductive element and a capacitor.
  • at least one of the harmonic reducer and the further harmonic reducer may include an open circuit quarter-wave transmission line stub.
  • Some embodiments of the invention provide methods of forming a packaged RF power device.
  • the methods include mounting a transistor on a base, the transistor including a control terminal and an output terminal and being configured to operate at a fundamental operating frequency, forming a harmonic signal reducer on the base and connecting the harmonic signal reducer to the control terminal and/or the output terminal of the transistor.
  • the harmonic signal reducer is configured to provide a short circuit or low impedance path from the control terminal and/or the second output terminal to ground for signals at an Nth harmonic frequency of the fundamental operating frequency, where N > 1.
  • the methods further include providing an RF signal input lead and an RF signal output lead on opposite sides of the base, connecting the RF signal input lead to the control terminal and connecting the RF signal output lead to the output terminal, and forming a package housing on the transistor and the harmonic reducer, with the RF signal input lead and the RF signal output lead extending from the package.
  • Forming the harmonic signal reducer may include providing a capacitor on the base and forming a wire bond connection between the capacitor and the transistor.
  • Providing the capacitor on the base may include providing the capacitor on the base between the output terminal of the transistor and the RF signal output lead, and forming the wire bond connection may include forming the wire bond connection between the capacitor and the output terminal of the transistor.
  • Connecting the RF signal output lead to the output terminal may include forming a second wire bond connection, the second wire bond connection including a bond wire extending over the capacitor from the output terminal to the RF signal output lead.
  • Figure IA is a perspective view of a packaged RF power transistor.
  • Figure IB is a functional block diagram of a conventional RF power transistor.
  • Figures 2A-2L are functional block diagrams of packaged RF power transistors according to some embodiments of the invention.
  • Figure 3 is a schematic circuit diagram of a packaged RF power transistor according to some embodiments of the invention.
  • Figure 4 is a plan view of a layout of a packaged RF power transistor according to some embodiments of the invention.
  • Figures 5-8 are schematic circuit diagrams of packaged RF power transistors according to some embodiments of the invention.
  • Figures 9A-9B are functional block diagrams of packaged multi-chip RF power transistors according to some embodiments of the invention.
  • Figure 10 is a schematic circuit diagram of a packaged multi-chip RF power transistor according to some embodiments of the invention.
  • RF power transistors typically include a plurality of transistor cells operating in parallel.
  • Transistors that can be included in packages according to embodiments of the invention can include laterally diffused MOSFETS (LDMOSFET) or other semiconductor devices, such as bipolar devices, MESFET devices, HBTs and HEMT devices.
  • the transistors can be made using narrow or wide bandgap semiconductors.
  • the transistors can include silicon LDMOS and/or bipolar transistors, and/or III-V devices such as GaAs MESFETs, InGaP HBTs, GaN HEMT devices, GaN bipolar transistors, etc.
  • RF power transistors providing 10 watts or more of power can be packaged as discrete devices, as shown generally at 10 in Figure IA and schematically in Figure IB.
  • the packaged transistor 15 (which may include a FET or bipolar device, for example) normally includes an input matching circuit 12 connecting an RF signal input lead 14 to a control electrode of a transistor 15 (e.g., a gate G of a FET or a base of a bipolar transistor).
  • An RF signal output lead 18 is connected to an output electrode of the transistor 15 (e.g., the drain D of a FET or the collector or emitter of a bipolar transistor).
  • the RF signal input lead 14 and the RF signal output lead 18 extend outside the package 10, as shown in Figure IA.
  • the source S of a FET 15 may be grounded.
  • a packaged transistor 10 may be mounted on a printed circuit board (not shown).
  • An external output matching circuit 22 may also be mounted on the printed circuit board.
  • a bias/RF diplexer (not shown) may be connected to the external output matching circuit to connect the transistor output to an RF output.
  • a DC power supply (not shown) may be connected to the transistor output lead 18.
  • Internal matching networks have been provided within RF power transistor packages. However, such internal matching networks are typically provided to match the fundamental operating frequency of the device, rather than a harmonic frequency.
  • the external output matching circuit 22 can include a harmonic short that is intended to reduce the energy in the output signal of signals at the second harmonic frequency of the fundamental operating frequency of the transistor 15.
  • a harmonic short that is intended to reduce the energy in the output signal of signals at the second harmonic frequency of the fundamental operating frequency of the transistor 15.
  • a harmonic reducer can be provided inside the device package, so that harmonic reduction can occur before the signal reaches the RF signal output lead 18.
  • some embodiments of the invention may improve linearity of a packaged RF power transistor by reducing second and/or higher order harmonics within the device package itself. Placing the harmonic reducer inside the package may improve the performance of the harmonic reducer across a broad range of frequencies and/or output power levels. Furthermore, design of an external output matching circuit may be simplified, since the signal output from the package may have lower energy at harmonic frequencies.
  • a harmonic reducer 116 can be included within a package IOOA including an RF power transistor 15 at the output (drain) of the transistor 15.
  • the harmonic reducer 116 is configured to reduce the energy at a harmonic frequency, such as the second harmonic frequency, in the output signal.
  • a package IOOB including an RF power transistor 15 can include an input matching circuit 212 including a harmonic reducer that is connected to a control electrode (e.g., the gate G) of the transistor 15.
  • the harmonic reducer in the input matching circuit 212 with harmonic reducer is configured to reduce the energy at a harmonic frequency, such as the second harmonic frequency, in the input signal.
  • a package IOOC including an RF power transistor 15 can include an input matching circuit 212 including a harmonic reducer that is connected to a control electrode of the transistor 15, as well as a harmonic reducer 116 at the output of the transistor 15.
  • a package including an RF transistor may not include an input matching circuit.
  • a package IOOD including an RF transistor 15 may include a harmonic reducer 112 that is connected to a control electrode (e.g., the gate G) of the transistor 15 and a harmonic reducer 116 at the output (drain) of the transistor 15.
  • a package 10OE including an RF transistor 15 may include a harmonic reducer 112 that is connected to the control electrode of the transistor 15, with no harmonic reducer at the output.
  • a package IOOF including an RF transistor 15 may include a harmonic reducer 116 that is connected to the output of the transistor 15, with no harmonic reducer at the input.
  • Some embodiments of the invention may include an output matching circuit connected to the output of the transistor 15.
  • a package IOOG including an RF transistor 15 includes an output matching circuit 216 including a harmonic reducer connected at an output of the transistor 15.
  • a package 10OH including an RF transistor 15 may include a harmonic reducer 112 that is connected to the control electrode of the transistor 15, and an output matching circuit 16 connected at the output.
  • a package 1001 including an RF transistor 15 may include a harmonic reducer 112 that is connected to the input of the transistor 15, and an output matching circuit 216 with a harmonic reducer connected at the output of the transistor 15.
  • Some embodiments of the invention may include an output matching circuit connected to the output of the transistor 15 as well as an input matching circuit connected to the input of transistor.
  • a package 10OJ including an RF transistor 15 includes an input matching circuit 14 and an output matching circuit 216 including a harmonic reducer connected at an output of the transistor 15.
  • a package IOOK including an RF transistor 15 may include an input matching circuit 212 including a harmonic reducer that is connected to the control electrode of the transistor 15, and an output matching circuit 16 connected at the output.
  • a package IOOL including an RF transistor 15 may include an input matching circuit 212 including a harmonic reducer that is connected to the input of the transistor 15, and an output matching circuit 216 with a harmonic reducer connected at the output of the transistor 15.
  • FIG. 3 A schematic circuit diagram for a package IOOA including an RF power transistor 15 including a harmonic reducer 116 according to embodiments of the invention is illustrated in Figure 3, and a physical layout of a package 100 according to embodiments of the invention is illustrated in Figure 4.
  • an input matching circuit 12 is connected between an RF signal input lead 14 and a gate G of the transistor 15.
  • the input matching circuit 12 may include an inductive wire bond connection including a bond wire 32 extending between the RF signal input lead 14 and a capacitor 36, and an inductive wire bond connection including a bond wire 34 extending from the capacitor 36 to the gate G of the transistor 15.
  • the source S of the transistor 15 is grounded, and an RF signal output lead 18 is connected to the drain D of the transistor 15 via an inductive wire bond connection including a bond wire 38 extending from the drain D of the transistor to the RF signal output lead 18.
  • the harmonic reducer 116 includes an inductive element 120 in series with a shunt capacitor 122.
  • the shunt capacitor 122 may be mounted on the base 140 of the package IOOA adjacent the transistor 15, and the inductive element 120 may include a bond wire extending from the transistor 15 to the shunt capacitor 122.
  • the shunt capacitor 122 may be formed on the base 140 of the package IOOA between the transistor 15 and the RF signal output lead 18. The inductive bond wire 38 may pass over the shunt capacitor 122.
  • the base of the package 100 can refer to any structural member on which the transistor 15 is mounted, and accordingly can correspond to a substrate, flange, die carrier, or the like.
  • the inductance of the inductive element 120 and the capacitance of the capacitor 122 may be selected so as to provide a short circuit and/or low impedance path to ground for signals at the harmonic frequency relative to the fundamental operating frequency of the transistor 15.
  • the vales of capacitance and inductance may be selected to provide a short circuit at a frequency of 5 GHz.
  • the selection of such values is known in the art.
  • the actual values used may depend on the configuration and/or physical layout of the circuit. As an example and not by way of limitation, for a transistor designed to operate at a fundamental operating frequency/ the capacitance and inductance of the capacitor 122 and the inductive element 120, respectively, may be chosen to satisfy the equation:
  • the capacitor 122 may have a capacitance of about 4 pF, and the inductor may have an inductance of about 0.25 nH.
  • the presence of the capacitor 122 may degrade the performance of the packaged device IOOA in terms of power and/or efficiency, but such reduction in performance may be offset by the improvement in linearity over a wide frequency range that can be obtained according to some embodiments.
  • Figure 5 is a schematic circuit diagram of a packaged RF power device IOOB including a harmonic reducer 216 connected to the control terminal (gate G) of the transistor 15.
  • the harmonic reducer 216 includes an inductive element 220 in series with a shunt capacitor 222.
  • the inductance of the inductive element 220 and the capacitance of the capacitor 222 may be selected so as to provide a short circuit and/or low impedance path to ground for signals at a harmonic frequency, such as the second harmonic frequency, relative to the fundamental operating frequency of the transistor 15 at the input to the transistor 15.
  • Figure 6 is a schematic circuit diagram of a packaged RF power device IOOC including a harmonic reducer 116 coupled to an output terminal (drain D) of the transistor 15 and a harmonic reducer 216 connected to the control terminal (gate G) of the transistor 15.
  • the harmonic reducer 116 includes an inductive element 120 in series with a shunt capacitor 122
  • the harmonic reducer 216 includes an inductive element 220 in series with a shunt capacitor 222.
  • the inductances of the inductive elements 120, 220 and the capacitances of the capacitors 122, 222 may be selected so as to provide short circuits and/or low impedance paths to ground for signals at a harmonic frequency, such as the second harmonic frequency, relative to the fundamental operating frequency of the transistor 15 at both the input and the output of the transistor 15.
  • a harmonic frequency such as the second harmonic frequency
  • the particular values selected for, e.g., the capacitors 122, 222 may be different due to the differing locations of the harmonic reducers 1 16, 216 relative to the transistor 15.
  • the capacitance of the capacitor 222 may be greater than the capacitance of the capacitor 122.
  • the harmonic reducer may include a resonant structure, such as an open circuit quarter wave transmission line stub, which may be formed on the base 140 on which the transistor 15 is mounted.
  • the quarter wave open transmission line stub has a length that is equal to one quarter of the wavelength of a harmonic frequency, and can present a short, circuit to signals at the harmonic frequency.
  • Figure 7 is an exemplary schematic circuit diagram for a packaged RF transistor IOOA including a harmonic reducer 116 implemented using an open circuit quarter-wave transmission line stub 316 connected at the output (drain D) of the transistor 15.
  • Figure 8 is a schematic circuit diagram of a package 10OJ for an RF transistor including an output matching circuit 16 that is connected between an output terminal of the transistor 15 and the RF output lead 18.
  • the output matching circuit 16 includes series inductances 76, 76 and a shunt capacitor 78.
  • FIG. 9 A and 9B are functional block diagrams of packaged multi-chip RF power transistors according to some embodiments of the invention
  • Figure 10 is a schematic circuit diagram of a packaged multi-chip RF power transistor according to some embodiments of the invention.
  • a multi-chip package 300A includes an input network 312 including a harmonic reducer that is connected between an RF input lead 14 and control electrodes of first and second transistors 15 A, 15B.
  • the outputs of the transistors 15A, 15B are connected to an RF output lead 18.
  • a multi-chip package 300B includes an input network 314 that is connected between an RF input lead 14 and control electrodes of first and second transistors 15 A, 15B.
  • a first harmonic reducer 316A is connected between an output terminal of the first transistor 15A and the RF output lead 18, and a second harmonic reducer 316B is connected between an output terminal of the second transistor 15B and the RF output lead 18.
  • FIG. 10 A schematic circuit diagram of a packaged multi-chip RF power transistor 300B according to some embodiments of the invention is illustrated in Figure 10.
  • a multi-chip package 300B includes an input network 314 that is connected between an RF input lead 14 and control electrodes of first and second transistors 15 A, 15B.
  • the input network 314 includes series inductors 32 A, 34A and a shunt capacitor 36A connected between the RF input lead 14 and the control terminal of the first transistor 15 A. and series inductors 32B, 34B and a shunt capacitor 36B connected between the RF input lead 14 and the control terminal of the second transistor 15B.
  • a first harmonic reducer 316A including an inductance 320A and a capacitor 322 A is connected to an output terminal of the first transistor 15 A
  • a second harmonic reducer 316B including an inductance 320B and a capacitor 322B is connected to an output terminal of the second transistor 15B.
  • Other configurations of multi-chip packages within the scope of the present invention will be apparent in view of the present application, including packages with input matching networks, output matching networks, input-side harmonic reducers and/or output-side harmonic reducers.
  • a packaged RF power transistor according to embodiments of the invention may be useful in a wide range of applications in which linearity is important.
  • a packaged power transistor according to embodiments of the invention may have application in systems, such as WiMAX, WCDMA, CDMA, and/or other systems, including future (4th generation) systems.
  • embodiments of the invention may be useful in any application in which linear performance is desired from a power transistor.
  • a harmonic reducer may be configured, through appropriate selection of reactance values, to reduce signals at higher order harmonic frequencies.
  • a harmonic reducer according to some embodiments of the invention may be configured to reduce signals at Nth-order harmonic frequencies, where N > 1.
  • multiple harmonic reducers may be provided according to some embodiments to reduce signals at various different harmonic frequencies.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Amplifiers (AREA)
  • Transmitters (AREA)
EP08767893A 2007-06-22 2008-05-28 Hf-leistungstransistorgehäuse mit interner oberschwingungsfrequenzverringerung und verfahren zur herstellung von hf-leistungstransistorgehäusen mit interner oberschwingungsfrequenzverringerung Ceased EP2162914A2 (de)

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US11/767,161 US8076994B2 (en) 2007-06-22 2007-06-22 RF power transistor packages with internal harmonic frequency reduction and methods of forming RF power transistor packages with internal harmonic frequency reduction
PCT/US2008/006722 WO2009002387A2 (en) 2007-06-22 2008-05-28 Rf power transistor packages with internal harmonic frequency reduction and methods of forming rf power transistor packages with internal harmonic frequency reduction

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WO2009002387A2 (en) 2008-12-31
CN101785110B (zh) 2012-07-04
US20080315392A1 (en) 2008-12-25
JP2013141291A (ja) 2013-07-18
WO2009002387A3 (en) 2009-02-19
US8076994B2 (en) 2011-12-13
KR101487570B1 (ko) 2015-01-29
JP2010531060A (ja) 2010-09-16
JP5850868B2 (ja) 2016-02-03
CN101785110A (zh) 2010-07-21
KR20100024496A (ko) 2010-03-05

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