EP2013968A1

EP2013968A1 - Operational amplifier

Info

Publication number: EP2013968A1
Application number: EP07724519A
Authority: EP
Inventors: Odile Dequiedt; Wolfram Kluge
Original assignee: Atmel Germany GmbH
Current assignee: Atmel Germany GmbH
Priority date: 2006-04-28
Filing date: 2007-04-24
Publication date: 2009-01-14
Also published as: US20080084245A1; US7535300B2; CN101432964A; DE102006020485B4; WO2007124895A1; DE102006020485A1; CN101432964B

Abstract

An operational amplifier and use of an operational amplifier with a difference amplifier (A1, A2, A3, A4) which is linked to a first input (In11, In12, In13, In14) and to a second input (In21 , In22, In23, In24), and with a differential output stage (D1, D2, D3, D4) which is linked to the difference amplifier (A1, A2, A3, A4) and to a first output (O21, O22, O23, O24) and a second output (O11, O12, O13, O14), in which the differential output stage (D1, D2, D3, D4) has a first branch with two first transistors ([MP211, MN211], [MP221, MN221], [QP231, QN231], [QP241, QN241]), the drain and/or collector of which are linked to each other and to the first output (O21, O22, O23, O24), the differential output stage (D1, D2, D3, D4) has a second branch with two second transistors ([MP212, MN212], [MP222, MN222], [QP232, QN232], [QP242, QN242]), the drain and/or collector of which are linked to each other and to the second output (O11, O12, O13, O14), the first gates and/or the first bases of the two first transistors ([MP211, MN211], [MP221, MN221], [QP231, QN231], [QP241, QN241]) in the first branch are linked to each other and to a first output (OD11, OD12, OD13, OD24) of the difference amplifier (A1, A2, A3, A4), the second gates and/or the second bases of the two second transistors ([MP212, MN212], [MP222, MN222], [QP232, QN232], [QP242, QN242]) in the second branch are linked to each other and to a second output (OD21, OD22, OD23, OD14) of the difference amplifier (A1, A2, A3, A4), the differential output stage (D1, D2, D3, D4) has a constant-current source (CS21, CS22, CS23, CS24), which is linked to each branch in order to supply a current (I21, I22, I23, I24) through the branches.

Description

operational amplifiers

The present invention relates to an operational amplifier, in particular for a battery-operated radio system.

Amplifiers are needed for a variety of applications. Thus, amplifiers are used for filter circuits or for amplifying measuring signals, for example in sensor systems. A known amplifier circuit is, for example, the operational amplifier. For a wide range of applications, amplifiers may advantageously amplify a wide frequency band. For some applications, it is also sufficient that the amplifier amplifies as a selective amplifier only a narrow frequency band in the range of an operating frequency.

An operational amplifier may include an input differential amplifier and an output stage. An operational amplifier is disclosed, for example, in "Analog Circuits", Seifart, 4th ed., Verlag Technik Berlin, 1994, pages 276 to 286. The input stage of an operational amplifier is, for example, a differential amplifier. Seifart; 4th edition; Verlag Technik Berlin; 1994; Pages 107 et seq. Disclosed. The output voltage of the differential amplifier is proportional to the difference voltage between both input terminals. Common mode voltages acting on both inputs in the same amplitude and phase are not amplified by the ideal differential amplifier. The advantageous properties of the differential amplifier receives by its largely symmetrical structure. The Emitters of the two input transistors may be connected together and to an input constant current source.

In IEEE Journal of Solid State Circuits, Vol. 38, NO. 2, Feb. 2003; Pages 176 ff., A low power 2.4 GHz transmitter / receiver CMOS IC with a differential amplifier is known. From IEEE Journal of Solid State Circuits, Vol. 38, NO. 4, April 2003, a 5.2 GHz low-noise amplifier in 0.35 μm CMOS technology with a differential amplifier is known.

In IEEE International's Solid-State Circuits Conference, 1994, Paper FA 14.1, a 3V CMOS Rail-to-Rail Input / Output Operational Amplifier for VLSI Cell Libraries is disclosed. In IEEE Journal of Solid State Circuits, Vol. 35, NO. 4, APRIL 2000 discloses a 1.2V CMOS Operational Amplifier with Dynamically Biased Output Stage.

From WO 01/73943 A1 an electronic output stage for CMOS LVDS level (LVDS-Iow voltage differential signaling) for use in analog and digital radio frequency circuits is known. The output stage includes a first and a second transistor connected to a first terminal to a power source and a control terminal to input terminals. A third and a fourth transistor are connected with a first terminal to a supply potential with a second terminal to a second terminal of the first and the second transistor and to an output terminal and with a control terminal to converted input signals. For the conversion of the input signals, a differential amplifier is provided, which is connected to the control terminal of the third and fourth transistors. The differential amplifier is used to amplify the input signals, to invert and to provide a voltage offset. It is also possible to set the desired output voltage at the output of the output stage via the high and low level from the differential amplifier. The invention is based on the object to develop the simplest possible operational amplifier for the highest possible Stromtreiberfähigkeit.

This object is achieved by an operational amplifier having the features of patent claim 1. Advantageous developments of the invention are the subject of dependent claims.

Accordingly, an operational amplifier is provided with at least one input differential amplifier and at least one output stage. The input differential amplifier is connected to a first input and to a second input. The output stage is differentially formed, so that it is connected to a first output and a second output of the operational amplifier. A useful signal amplified by the operational amplifier is in antiphase at the first output and at the second output.

The output stage may be connected to the input differential amplifier indirectly via another stage. Preferably, however, the output stage is directly connected to the input differential amplifier. The output stage has bipolar transistors or field-effect transistors.

The differential output stage has a first branch with two first transistors whose drain and collector are connected to each other and to the first output. The differential output stage further has a second branch with two second transistors whose drain and collector are connected to each other and to the second output. Preferably, the first branch and the second branch are formed symmetrically. Preferably, the first branch and the second branch have identical transistors. Be under the same transistors This understood transistors, which may have small differences from each other due to tolerances of the manufacturing process.

The first gates or the first bases of the two first transistors in the first branch are connected to one another and to a first one

Output of the input differential amplifier connected. The second gates or the second bases of the two second transistors are in the second branch with each other and with a second output of

Input differential amplifier connected. The thus connected two first transistors and two second transistors are hereinafter referred to as

Full bridge called.

Therefore, always the same voltage is applied to both gate terminals or to both base terminals of the transistors of a branch. There are no stages for setting a different bias voltage for the two gates or two bases of a branch.

The two transistors of a branch are preferably connected as a so-called push-pull stage. Preferably, each branch comprises an N-channel field effect transistor (NMOS, N-JFET) and a P-channel field effect transistor (PMOS, P-JFET). In the case of the push-pull stage, the source of the N-channel field-effect transistor is advantageously connected to ground or to a negative supply voltage terminal. Alternatively, the source of the P-channel field-effect transistor is preferably connected to a positive supply voltage terminal.

Alternatively, each branch has an npn bipolar transistor and a pnp bipolar transistor. In the case of the push-pull stage, the emitter of the npn transistor is advantageously connected to ground or to a negative supply voltage terminal. Alternatively, preferably, the emitter of the PNP transistor is connected to a positive supply voltage terminal. The full bridge is thus preferably formed of two push-pull stages (push-pull amplifier). The two branches are advantageously formed equal within the scope of manufacturing tolerances. The drain or collector of each transistor of a branch is connected to an output of the operational amplifier. Thus, the load terminals are formed on the full bridge in the bridge diagonal.

Furthermore, the differential output stage has a constant current source. The constant current source is connected to each branch for supplying a current. For this purpose, the constant current source is connected to a source or an emitter of a transistor of the first transistors of the first branch and to a source or an emitter of a transistor of the second transistors of the second branch. A source or an emitter of the other transistor of the first transistors of the first branch is preferably connected to a supply voltage terminal. In addition, a source or an emitter of the other transistor of the second transistors of the second branch is preferably connected to the supply voltage terminal. Consequently, the push-pull stages formed by the transistors are connected to the constant current source, or the constant current source is connected to the full bridge for supplying a current through the full bridge.

For example, if field effect transistors are used in the differential output stage, the constant current flows through the feed by means of the constant current source via drain-source paths of the transistors. In addition, at high frequencies, a small proportion flows or changes as a displacement current via the gate capacitances and the gate terminals. For example, if bipolar transistors are used in the differential output stage, the constant current flows through the supply by means of the constant current source via collector-emitter paths of the Transistors. A small proportion also flows as a base current through the base terminals of the bipolar transistors or to. Under a constant current source is depending on the direction of flow of the current to understand a power source or a current sink.

According to a first embodiment variant, the two first transistors are complementary bipolar transistors and the two second transistors are complementary bipolar transistors. According to a second embodiment variant, the two first transistors are complementary field effect transistors and the two second transistors are complementary field effect transistors.

In a preferred embodiment of the invention it is provided that the operating point of the output stage is set such that at the operating point of the constant current of the constant current source flows to the one half through the two first transistors of the first branch and the other half through the two second transistors of the second branch. Under half of the current is understood not a mathematical half but a halfway division of the current within the manufacturing tolerances of the operational amplifier. The output current or the output voltage of the operational amplifier usually has a low offset due to these manufacturing tolerances.

Preferably, the input differential amplifier has a first input transistor and a second input transistor. In addition, a first source terminal or a first emitter terminal of the first input transistor and a second source terminal or a second emitter terminal of the second input transistor are preferably connected to an input constant current source. According to an advantageous embodiment of the invention, the constant current source of the differential output stage and the input constant current source of the input differential amplifier connected to the same supply voltage terminal of the operational amplifier.

Another aspect of the invention is a use of an operational amplifier for a battery operated radio system. In this case, the operational amplifier has an input differential amplifier and a differential output stage, which is connected to the input differential amplifier. The differential output stage has a first branch with a push-pull stage with two first transistors and a second branch with a push-pull stage with two second transistors. The differential output stage further includes a constant current source connected to each push-pull stage for supplying a current through the push-pull stages.

The further development variants described above are particularly advantageous both individually and in combination. All training variants can be combined with each other. Some possible combinations are explained in the description of the embodiments of the figures. However, these possibilities of combinations of further development variants presented there are not exhaustive.

In the following the invention will be explained in more detail in exemplary embodiments with reference to drawings.

Show

Fig. 1 is a first schematic circuit diagram of a first

Embodiment of an operational amplifier;

Fig. 2 is a second schematic circuit diagram of a second

Embodiment of an operational amplifier; Fig. 3 is a third schematic circuit diagram of a third

Embodiment of an operational amplifier; and

4 shows a fourth schematic circuit diagram of a fourth

Embodiment of an operational amplifier.

Fig. 1 shows a preferred embodiment of an operational amplifier. The aim of this embodiment of the operational amplifier is to achieve the lowest possible power consumption or the highest possible Stromtreiberfähigkeit given operating current. The operational amplifier has an input differential amplifier A1, which is connected to a first input In-π and to a second input In _{2I of} the operational amplifier. Furthermore, the operational amplifier has a differential output stage D1, which is connected to the input differential amplifier A1 and a first output On and a second output O ₂ i. The supply voltage V + in the embodiment of FIG. 1 is 1, 8 V.

The differential output stage D1 has two NMOS field effect transistors Mp2n, MN2H and two PMOS field effect transistors MP212 and MN ₂ 1 ₂ . In the embodiment of Fig. 1 are used as transistors Mp ₂ n, M _N 2n, M _P2 12, and M _N 2i ₂ MOSFETs a CMOS technology. Alternatively, junction field effect transistors may also be used.

The output stage can be two push-pull stages. One of the two transistors of each push-pull stage, in the embodiment of FIG. 1, this is the PMOS field-effect transistor of a branch is not connected to the source terminal at the operating voltage V +, but to a constant current source CS21. A first branch of the differential output stage D1 has a PMOS transistor M _P2 n and an NMOS transistor M _N2 n, which are preferably complementary. The gate terminals of both transistors M _P2 n and M _N 211 are directly connected together. Furthermore, the gate terminals of both transistors Mp ₂ n and M _N2 n are connected to an output ODH of the input differential amplifier A1.

Also, the drain terminals of both transistors Mp ₂ n and MN2H are directly connected to each other and to an output O ₂ i of the output stage D1. The source at the end of the NMOS transistor M _N2 n is connected to a supply voltage connection - in this case to ground GND. On the other hand, the source terminal of the PMOS transistor Mp ₂ n is connected to the constant current source CS ₂₁ .

A second branch also has a PMOS transistor Mp _2I2 and an NMOS transistor M _N212 , which are preferably also complementary. The gate terminals of both transistors Mp ₂ i ₂ and MN ₂₁₂ are directly connected together. Furthermore, the gate terminals of both transistors M _P2 i ₂ and M _{N212 are} connected to an output O _D2 i of the input differential amplifier A1.

Also, the drain terminals of both transistors M _P212 and M _N2 i _{2 are} directly connected to each other and to an output O _{22 of} the output stage D1. The source terminal of the NMOS transistor M _N2 i ₂ is connected to a supply voltage connection - in this case to ground GND. On the other hand, the source terminal of the PMOS transistor Mp _{212 is} connected to the source terminal of the PMOS transistor M _P2 n of the other branch and to the constant _current source CS _2I . The constant _{current source} CS _2I is connected to a supply voltage connection, here the positive supply voltage connection V +. The four transistors MP2H, MN2H, MP212, MN ₂₁₂ can also be referred to as a full bridge in the described interconnection. The differential output stage D1 therefore has the constant current source CS ₂₁ , which is connected to the full bridge for supplying a current I ₂₁ through the full bridge. The current i l ₂ by the full-bridge is determined solely by the constant current source CS _21, if no additional current of the constant current source CS superimposed by the outputs On or O21 of the output stage D1 the current I ₂₁ _21st

The constant current source CS ₂₁ continues to be the operating point setting. The voltage VDI adjusts itself by operating the first transistors of the first branch and the second transistors of the second branch with the constant current source CS ₂₁ .

The input differential amplifier A1 has two input transistors M _P m and Mp ₁₁₂ , which are formed in the embodiment of FIG. 1 as PMOS field effect transistors. Alternatively, of course, other types of transistors, such as junction field effect transistors may be used. The gate terminal of the first input transistor Mp ₁₁₁ is connected to an input In _{2I of} the operational amplifier. The gate terminal of the second input transistor M _P n ₂ is connected to the other input In _{11 of} the operational amplifier. The source terminals of both input transistors Mp ₁₁₁ and Mp ₁ _-I2 are connected directly to each other and to an input constant current source CS ₁₁ . The input constant current source CS ₁₁ is in turn connected to a supply voltage terminal, here to the positive supply voltage terminal V +.

The drain terminal of the first input transistor Mp _{H 1} is connected to a further current source and to a first output Op _{11 of} the input differential amplifier A1 and thus directly to the gate terminals of the transistors Mp ₂₁₁ and M _N2 n of the differential output stage D1. The drain terminal of the second input transistor is with a further current source and with a second output Ooi2 of the input differential amplifier A1 and thus directly connected to the gate terminals of the transistors M _P21 2 and M _N2 i _{2 of} the differential output stage D1.

For the full bridge connected to the constant current source CS21 of the embodiment of FIG. 1, unlike an AB amplifier, no drive circuit is provided for providing bias and signal voltage at the gates of the output transistors M _P 2n, M _N 211, M _P2 12, and M _N 2i2 needed. This has the advantage that push-pull operation of this push-pull stage is achieved, without requiring additional effort for the control of the output transistors Mp ₂ n, IvWn, MP212, and M _N 2i2. The maximum frequency to be amplified is determined by the electrical characteristics of the output transistors Mp2n, MN2H, MP212, and MN212 and not reduced by additional amplifier stages.

The maximum driver strength is achieved when the transconductances of the PMOS field effect transistors and the NMOS field effect transistors are equal within manufacturing tolerances. In this case, a signal amplitude (peak-peak) of a maximum of 2 xl ₂ i from the transistors of the first branch and the second branch at the outputs On, O ₂ i are discharged, wherein in each of the two branches a quiescent current of I ₂₁ / 2 flows. Another possible advantage is that the circuit of FIG. 1 is a low supply current needs, the current In for the input differential amplifier A1 is determined by the constant current source CSn and the current I ₂₁ for the output stage D1 by the constant current source CS21.

For a reliable operation of the input differential amplifier, it is only possible in the embodiment of FIG.

Apply common-mode voltage to half the supply voltage V + / 2 of 0.9V. The sum of threshold voltage, Vdsat of the amplifier transistor and Vdsat of the input constant current source CSn are larger than 0.9V in the embodiment of Fig. 1. Thus, the practical input common-mode voltage can be 0.6V to 0.7V, thus not requiring symmetrical modulation of the output stage D1.

The common mode control circuit which is preferably used for the differential operational amplifier of Fig. 1 is not shown in Fig. 1 for the sake of simplicity.

2, a further embodiment of an operational amplifier is shown schematically as a circuit diagram. The output stage D2 with the constant current source CS22 and the transistors MP221, MN221, MP222, and MN ₂₂₂ does not differ from the output stage D1 in FIG. 1. On the other hand, the input differential amplifier A2 has a first NMOS field effect transistor M _N121 and a second NMOS field effect transistor M. _1M 1 ₂₂ whose gate terminals are connected to inputs Ini ₂ and Iri _{22 of} the operational amplifier. In addition, the sources of the transistors M _N i ₂₂ . M _N i2i connected to an input constant current source CS12. The input constant current source CS ₁₂ is in turn connected to ground GND.

At the inputs Ini ₂ and In ₂₂ is an input signal which may have both a common-mode signal component and a push-pull signal component. In this case, a common-mode signal is understood to mean a signal which is applied to both inputs Ini ₂ and In _{22 of} the input differential amplifier A2 with the same frequency and the same phase position and the same amplitude. A push-pull signal is understood to be a signal applied to the inputs lni ₂ and In ₂₂ with the same frequency, the same amplitude and a phase shifted by 180 °. Common-mode signals and push-pull signals can also be superimposed on one another. The push-pull signal is usually the useful signal. The push-pull signal is voltage-amplified by the input differential amplifier A2 and passes through the outputs 0 _D i ₂ and O _{D22 of} the input differential amplifier A2 to the gate terminals of the transistors Mp22i, M _N 221, MP222 _> and M _N2 22 of the output stage D2. The gate electrodes of the transistors Mp22i, MN22I, MP222, and MN ₂₂₂ represent a capacitive impedance as additional load of the input differential amplifier A2. The smaller this capacitive load is formed, the higher a maximum amplification frequency of the input differential amplifier A2 can be achieved. However, as the capacitive load is reduced, the gate width of the transistors M _P22 i, M _N221> MP222, and M _{N222 of} the output stage D2 is also reduced. This in turn reduces the current driving capability of the output stage D2.

In Fig. 3, a further embodiment of an operational amplifier in the form of a circuit diagram is shown schematically. In the Fig. 3 are used for the input differential amplifier A3 and the output stage bipolar transistors Qp ₂₃ D3 I, QN23I, QP23I, QP232, QN232, and Qm QNI3I ₃₂ is used.

The input differential amplifier A3 includes npn bipolar transistors QN 32 and Q. ₂ _N131 on as the input transistors. The bases of the input transistors QN ₂₃₂ and Q.N131 are connected to the inputs lni ₃ and In ₂ 3 of the operational amplifier. The emitters of the input transistors QN ₂₃₂ and QN ₁ 31 are connected to an input constant current source CS ₁₃ , which in turn is connected to ground GND.

The output stage D3 has a first branch with a complementary npn bipolar transistor Q _N23 i and pnp bipolar transistor Qp ₂₃ i whose bases are connected to one another and to an output O _D i _{3 of} the input differential amplifier A3. Furthermore, the collectors of the npn bipolar transistor QN23 _I and the pnp bipolar transistor Qp ₂ 3i are connected to each other and to an output O _{13 of} the output stage D3. The emitter of npn bipolar transistor Q _N23I is connected to a constant _{current source} CS ₂₃ , which in turn is connected to ground GND. By contrast, the emitter of the pnp bipolar transistor Q _P231 is connected to a supply voltage connection, in this case to the positive supply voltage V +.

Furthermore, the output stage D3 has a second branch with a complementary npn bipolar transistor QN232 and pnp bipolar transistor Q _P232 . The emitter of the npn bipolar transistor QN232 is connected to the emitter of the npn bipolar transistor QN ₂ 31 and to the constant current source CS ₂ 3. Consequently, both the constant current source CS _{23 of} the output stage D3 and the input constant current source CS _{13 of} the input differential amplifier A3 are connected to the same supply voltage potential (here GND).

The embodiment of Fig. 3 is particularly suitable for small supply voltages by a battery. For this purpose, particularly small base-emitter voltages at the operating point and high current amplification factors of the bipolar transistors are advantageous. For particularly high frequencies, heterobipolar transistors, for example with a mixed crystal of silicon germanium, are advantageously used.

FIG. 4 shows yet another embodiment of an operational amplifier based on a schematic circuit diagram. In contrast to FIG. 3, the input differential amplifier A4 has pnp bipolar transistors Q _P14 i and QPI ₄₂ as input transistors. The bases of the input _transistors QPI ₄ I and Q. _P142 are connected to the inputs lni ₄ and In _{24 of} the operational amplifier. The emitters of the input transistors Qp _14I and Qp ₁₄₂ are connected to an input constant current source CS ₁₄ , which in turn is connected to the positive supply voltage V +. The embodiment of FIG. 4 has the advantage that the base currents of the transistors Qp24i, QN24I, QP242 and QN242 need not be set separately by extra steps, but automatically by the current distribution of the current I _{24 of} the constant current source CS ₂₄ be set in their operating point. Advantageously, the transistors QP2 ₄ I, QN241, QP242 and QN242 for this purpose have the same current amplification within the scope of the manufacturing tolerances.

However, the invention is not limited to the embodiments of the four figures. For example, in the exemplary embodiments of FIGS. 1 and 2, NPN bipolar transistors may be used instead of the NMOS field-effect transistors and PNP bipolar transistors may be used instead of the PMOS field-effect transistors. For example, in the exemplary embodiments of FIGS. 3 and 4, NMOS field-effect transistors may be used instead of the NPN bipolar transistors, and PMOS field-effect transistors may be used instead of the PNP bipolar transistors. Likewise, mixed bipolar transistors and field-effect transistors can also be used in the input differential amplifier and / or in the output stage. It is also possible in the input differential amplifier and / or in the output stage to use transistors in cascode or Darlington circuit to achieve a higher voltage gain or current gain.

The input differential amplifier is advantageously formed together with the differential output stage on a semiconductor chip as an integrated circuit.

LIST OF REFERENCES

MN2H, MN212, MNI2I, MNI22, field effect transistors (NMOS, N-SFET)

Mpin, Mpi ₁₂ , Mp ₂ n, M _P212 , field-effect transistors (PMOS, P-SFET)

Mp221, Mp222

QNI3I, QNI32, QN23I, QN232, npn bipolar transistor

QN241, QN242

Qp23i, QP232, Qp-141, Qpi42, pnp bipolar transistor

Qp241, QP242

CSn, CS21, CS ₁₂ , CS22, power source, current sink

V + positive supply voltage connection

GND ground connection

Irin, ln ₂ i, In ₁₂ , In ₂₂ , In ^, input of the input differential amplifier;

In ₂₃ , In ₁₄ , In ₂₄ input of the operational amplifier

ODH, O ₀₂₁ , OD-I ₂ , OD22, output of the input differential amplifier

OD13> OD23> OD14> OD24

O _{1 I} , O ₂₁ , O ₁₂ , O ₂₂ , O ₁₃ , output of the output stage; Output of the

O ₂₃ , O ₁₄ , O ₂₄ operational amplifier

A1, A2, A3, A4 input differential amplifier

D1, D2, D3, D4 output stage

I electricity

V voltage

Claims

claims

1. operational amplifier,

- having a first input (INN, lni _2, lni _3l lni ₄₎

with a second input (In ₂ -I, In ₂₂ , In ₂ 3, In ₂₄ ),

- With an input differential amplifier (A1, A2, A3, A4), with the first input (Irin, lni ₂ , lni ₃ , In ^) and with the second input

(ln ₂ i, In ₂₂ , In ₂₃ , In ₂₄ ),

with a first output (O ₂ i, O ₂₂ , O ₂₃ , O ₂₄ ),

with a second output (On, O ₁₂ , Oi ₃ , Ou), and

- With a differential output stage (D1, D2, D3, D4), with the input differential amplifier (A1, A2, A3, A4) and the first

Output (O ₂₁ , O ₂₂ , O ₂₃ , O ₂₄ ) and the second output (On, Oi ₂ , Oi ₃ , Oi ₄ ) is connected to the

- The differential output stage (D1, D2, D3, D4) a first branch with two first transistors ([M _P2 n, M _N2 n], [M _P22 i, M _N22 i], [Qp ₂ 3i,

QN23I], [Qp24i, QN24I]) whose drain or collector are connected to each other and to the first output (O ₂₁ , O ₂₂ , O ₂₃ , O ₂₄ ),

the differential output stage (D1, D2, D3, D4) has a second branch with two second transistors ([M _P2 i ₂ , MN212], [Mp ₂₂₂ , MN222], [QP232,

Q.N232], [QP242, QN242]) whose drain or collector are connected to each other and to the second output (On, O ₁₂ , Oi ₃ , d ₄ ),

the first gates or the first bases of the two first transistors ([M _P2 ii, M _N 2n], [Mp ₂₂₁ , M _N 22i], [Qp23i, QN231], [Qp24i, QN24I]) are connected in the first branch together and to a first output (ODH, 0 _D I2, I3 0 _D, O _D 24) of the input differential amplifier (A1, A2, A3, A4),

the second gates or the second bases of the two second transistors ([Mp ₂ I ₂ , MN212], [M _P2 22, M _N22 2], [QP232, QN232],

[Qp ₂ 42, QN ₂₄₂ ]) in the second branch are connected to one another and to a second output (O _D 2i, OD22, OD23, O ₀ I ₄ ) of the input differential amplifier (A1, A2, A3, A4),

- The differential output stage (D1, D2, D3, D4) has a constant current source (CS ₂ i, CS ₂₂ , CS ₂₃ , CS ₂₄ ), with each

Branch for supplying a current (I ₂₁ , I ₂₂ , I ₂₃ , I ₂₄ ) is connected by the branches.

The operational amplifier of claim 1, wherein the two first transistors are complementary bipolar transistors ([Qp ₂ 3i,

QN231], [Q.P241, QN24I]) and the two second transistors complementary bipolar transistors ([Qp ₂₃₂ ,

QN232], [QP242, QN242]).

The operational amplifier of claim 1, wherein the two first transistors are complementary field effect transistors

([M _P2 ii, M _N 2ii], [Mp ₂₂ I, M _N 22i]) and the two second transistors complementary field-effect transistors

([Mp ₂₁₂ , M _N 212], [Mp ₂₂₂ , MN222]).

4. An operational amplifier according to one of the preceding claims, in which the operating point of the two first transistors ([M _P2 n, MN2HL [Mp ₂₂₁ ,

M _N 22i], [QP23I, QN23I], [Qp24i, Q.N24i]) in the first branch and the two second transistors ([M _P2 i ₂ , MN212], [M _P2 22, MN222], [QP232, QN232] , [QP242, QN242]) in the second branch is set such that the constant current (I ₂₁ , I ₂₂ ,

I ₂ 3, I ₂₄ ) of the constant current source (CS21, CS ₂₂ , CS ₂ 3, CS24) to one half by the two first transistors ([Mp ₂ H, M _N 2n], [M _P2 2i, M _N 22i], [Qp23i, QN23I], [Qp24i, QN24I]) of the first branch and the other half by the two second transistors ([M _P2 12, MN212], [M _P22 2, MN222], [QP232, QN232], [QP242, QN242]) of the second branch.

5. Operational amplifier according to one of the preceding claims, wherein

- the input differential amplifier (A1, A2, A3, A4) has a first input transistor (Mpm, M _N i2i, QN ₁ 3 ₁ , QPMI) and a second input transistor (M _P n ₂ , M _N i22, QNI32, QP142),

a first source terminal or a first emitter terminal of the first input transistor (M _P m, M _N i2i, QN131, Q _P I ₄ I) and a second source terminal or a second emitter terminal of the second input transistor (M _P n ₂ , M _N122 , Q.N132, Q.P142) with an input constant current source (CSn, CSi ₂ ,

CS ₁₃ , CSi ₄ ), and

the constant current source (CS ₂ i, CS ₂₂ , CS ₂₃ , CS ₂₄ ) of the differential output stage (D1, D2, D3, D4) and the input constant current source (CS ₁₁ , CS ₁₂ , CS ₁₃ , CSi ₄ ) of the input differential amplifier (A1, A2, A3, A4) at the same supply voltage connection (V +,

GND) are connected.

6. Use of an operational amplifier according to one of the preceding claims for a battery-powered radio system.