EP1915694A1 - Procede et dispositif pour memoriser des donnees et/ou des ordres dans un systeme de calcul comprenant au moins deux unites de traitement et au moins une premiere memoire ou zone de memoire pour des donnees et/ou des ordres - Google Patents

Procede et dispositif pour memoriser des donnees et/ou des ordres dans un systeme de calcul comprenant au moins deux unites de traitement et au moins une premiere memoire ou zone de memoire pour des donnees et/ou des ordres

Info

Publication number
EP1915694A1
EP1915694A1 EP06777958A EP06777958A EP1915694A1 EP 1915694 A1 EP1915694 A1 EP 1915694A1 EP 06777958 A EP06777958 A EP 06777958A EP 06777958 A EP06777958 A EP 06777958A EP 1915694 A1 EP1915694 A1 EP 1915694A1
Authority
EP
European Patent Office
Prior art keywords
memory
access
port
data
memory area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP06777958A
Other languages
German (de)
English (en)
Inventor
Reinhard Weiberle
Bernd Mueller
Eberhard Boehl
Yorck Collani
Rainer Gmehlich
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Robert Bosch GmbH
Original Assignee
Robert Bosch GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch GmbH filed Critical Robert Bosch GmbH
Publication of EP1915694A1 publication Critical patent/EP1915694A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1658—Data re-synchronization of a redundant component, or initial sync of replacement, additional or spare unit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0853—Cache with multiport tag or data arrays
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1629—Error detection by comparing the output of redundant processing systems
    • G06F11/1641—Error detection by comparing the output of redundant processing systems where the comparison is not performed by the redundant processing components
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/845—Systems in which the redundancy can be transformed in increased performance

Definitions

  • Computer system with at least two processing units and at least one first memory or memory area for data and / or commands
  • the present invention relates to microprocessor systems with fast cache memory and in this context describes a dual port cache.
  • processors are cached to speed access to instructions and data. On the other hand, this is necessary with the constantly growing amount of data on the one hand and the increasing complexity of data processing with ever faster processors on the other hand.
  • a cache partially avoids slow access to large (main) memory, and the processor then does not have to wait for the data to be provided.
  • Both caches for commands and data only are known, as well as "unified caches" where both data and instructions are stored in the same cache.
  • Systems with several levels (hierarchy levels) of caches are also known. Such multi-level caches are used to optimally adjust the speeds between the processor and the (main) memory using graduated memory sizes and various addressing strategies of the caches at the different levels.
  • each processing unit must load these from the main memory into its associated cache. Bus conflicts may occur if two or more processors want to access the main memory. This leads to a performance loss of the multiprocessor system. If there are several shared caches, each of which has access to more than one processor, and if two processors require the same or different data from one of these caches, then because of the access conflict, it must be decided which processor can access with priority, and the other processor must inevitably waiting. The same is true even for different data and commands when a bus system is used for the caches, which at the same time only allows access to different caches.
  • processors each have a fixed cache, they can also be switched to different operating modes of the processor system, where they execute either different programs, program segments or commands (performance mode) or execute the same programs, program segments or commands and compare the results Voting (compare mode), the data or commands must be deleted in the parallel caches of each controller when switching between the operating modes eriificat, or they must be provided when loading the caches with the corresponding information of the respective operating mode, preferably together with the data is stored.
  • performance mode the processors
  • Compare mode compare the results Voting
  • the data or commands must be deleted in the parallel caches of each controller when switching between the operating modes eriificat, or they must be provided when loading the caches with the corresponding information of the respective operating mode, preferably together with the data is stored.
  • the object of the invention is therefore to design such a memory.
  • the object of the invention is to provide means and methods to optimize the size of the cache.
  • a dual port cache architecture can be used advantageously.
  • the main advantage over multi-cache multiprocessor systems is that, when switching between the operating modes of the multiprocessor system, the contents of the cache need not be cleared or invalidated because the data is stored only once and therefore remains consistent even after a switchover ,
  • a dual port cache in a multiprocessor system with multiple operating modes has the distribution that the data / instructions need not be repeatedly cached and possibly maintained, only one space per date / command must be provided in hardware, even if this date or This instruction is used by multiple execution units, the data does not have to be differentiated in different operating modes of the multiprocessor system in which mode they were processed or fetched, the cache at
  • a device for storing data and / or commands in a computer system having at least two processing units and at least a first memory or memory area for data and / or commands, if in the device, a second memory or memory area is included, wherein the device as cache memory - is formed and is equipped with at least two separate ports and accessed via these ports access the at least two processing units to the same or different memory cells of the second memory or memory area, the data and / or commands from the first memory system are cached in blocks.
  • Such a device is advantageous if means are provided which are configured in such a way that read access to a memory cell takes place simultaneously via the at least two ports.
  • Access addresses can be compared to the at least two ports
  • an address comparator is present in the device, which determines that at least one memory cell from that of the first via a second port
  • Processing unit to be accessed via the first port requested memory block.
  • the second memory or memory area is subdivided into at least two address areas which can be read or written independently of each other.
  • an address decoder is present in the device which generates select signals which only allow access to one port at a simultaneous access to an address area and inhibit or delay the access of the at least one further port, in particular by wait-signals.
  • an n-times associative cache is realized in the device with the aid of n different address ranges. Furthermore, it is advantageous if means are present in the device which simultaneously write the data to be written into the first memory or memory area during a write access to a memory cell or a memory area of the second memory.
  • a method for storing data and / or commands in a computer system having at least two processing units and at least one first memory or
  • Memory area for data and / or commands described characterized in that in the device, a second memory or memory area is included, wherein the device is designed as a cache memory system and is equipped with at least two separate ports and access to the at least two processing units via these ports identical or different memory cells of the second memory or memory area, wherein the
  • Data and / or commands from the first storage system are cached block by block.
  • a method is described, characterized in that for reading data from the second memory or memory area and / or for writing data in the second memory or memory area via the two ports, a parallel access of processing units to the same or different memory cells of the second memory or memory area and the reading of a same memory cell via both ports takes place at the same time
  • a method is described, characterized in that addresses which are applied to the two ports are compared.
  • a method is described, characterized in that a write access to the second memory or memory area and / or a memory cell of the second memory or memory area is detected via a first port, and the read and write access via a second port to this second Memory or memory area is prevented and / or delayed until the write access is completed via the first port.
  • a method is described, characterized in that, in the case of a read access via at least one port, it is checked whether the desired data and / or commands are present in the second memory or memory area.
  • a method is described, characterized in that the check is made on the basis of the address information.
  • a method is described that in the case when the data requested via a first port are not present in the second memory or memory area, the corresponding memory block is caused to move from the first memory array to the second memory
  • a method is described in that all information about the presence of the data and / or commands are updated as soon as the requested memory block has been transferred to the second memory or memory area.
  • a method is described, characterized in that an address comparator determines that a second processing unit would like to access at least one memory cell from the memory block requested by the first processing unit.
  • a method is described, characterized in that the access to the said memory cell is made possible only when the relevant information has been updated on the presence of the data and / or commands.
  • a method is described, characterized in that the second memory or memory area is subdivided into at least two address areas and these at least two address areas can be read or written independently of one another via the at least two ports of the second memory or memory area, each port being on can access any address range.
  • a method is described, characterized in that the simultaneous access to an address area is limited to exactly one port, and all further access requests via other ports to this address area are inhibited or delayed during the access of the first port, in particular by wait signals .
  • a method is described, characterized in that, in the case of a write access to a memory cell or a memory area of the second memory, the data to be written is simultaneously written into the first memory or memory area.
  • a method is described, characterized in that, in a write access to a memory cell or a memory area of the second memory, the data to be written is delayed in the first memory or memory area is written.
  • FIG. 1 shows a dual port cache for data and / or commands.
  • FIG. 2 shows a dual port cache with further details.
  • FIG. 3 shows a device and a method for address transformation.
  • FIG. 4 shows a division of the dual-port RAM into two subareas which can be operated independently of one another and are accessed by two separate select signals from each port.
  • FIG. 5 shows a realization of a dual port RAM area by a single port RAM by means of a port switch.
  • FIG. 6 the division of a multiple port RAM with p ports into several sub address areas 1... Q which can be processed in parallel is shown.
  • FIG. 7 shows the implementation of a multi-port RAM area by means of a single port RAM by means of port switching.
  • FIG. 8 a division of the RAM areas for the ports depending on a system state or a configuration is shown
  • FIG. 9 shows a division of a multi-port RAM into areas as a function of one
  • FIG. 10 shows the division of a multi-port RAM into areas with multiple associative access.
  • Table 1 shows the generation of 4 select signals from 2 address bits by means of decoding.
  • Table 2 shows the generation of two select signals on each port from an address bit taking into account a system state or configuration signal M.
  • Table 3 shows the generation of two select signals at each port from an address bit taking into account a system state or configuration signal M in another embodiment.
  • a processing unit or execution unit may denote both a processor / core / CPU and an FPU (floating point unit), DSP (digital signal processor), coprocessor or ALU (arithmetic logical unit).
  • FPU floating point unit
  • DSP digital signal processor
  • ALU arithmetic logical unit
  • the dual port cache 200 essentially consists of a dual port RAM (dpRAM, 230).
  • This dpRAM 230 is preferably provided with two independent address decoders, two data read / write stages and, unlike a simple memory cell matrix, also with duplicated word and bit lines, so that at least the read operation for any memory cells of the dpRAM of both ports can be done simultaneously.
  • a dual port RAM is therefore understood to mean any RAM which has two ports 231 and 232 which irrespective of how much time is needed to complete a request to read or write from this port, ie, how long it takes for the requested read or write to interact with requests from the other port is completed.
  • the Both ports of the dpRAM are connected via the signals 201 and 202, respectively, to the devices 210 and 220, respectively, which check the incoming addresses, data and control signals 211 and 221, respectively, of independent processing units 215 and 225 and optionally transform the addresses.
  • the data is output via 201 through 210 to 211 or via 202 by 220 to 221 or written in the reverse direction by the execution units into the cache memory.
  • Both ports of the dpRAM are connected via signals 201 and 202 to a bus access controller 240 which is connected to signals 241 which connect to a main memory (not shown) or to a next level cache.
  • the cache can be partially or completely associative, ie the data can be stored at several or even arbitrary locations of the cache.
  • the address In order to enable access to the dpRAM, the address must first be determined by means of which the desired data / commands can be accessed. Depending on the addressing mode, one or more block addresses are selected where the date is searched in the cache. All these blocks are read and the identifier stored in the cache with the data is compared with the index address (part of the original address). If there is a match and after the additional validation with the help of the control bits also stored in the cache for each block (eg valid bits, dirty bits and process ID), a cache hit signal is generated which indicates the validity.
  • a table is preferably used which is arranged in a memory unit 214 or 224 (register or RAM, also referred to as TAG RAM) shown in FIG. 2 and is located in units 210 and 220, respectively.
  • the table is an address transformation unit that both converts the virtual address to a physical address and, in the case of a direct-mapped cache, provides the exact (unique) cache access address; in a multi-associative cache organization, multiple blocks are addressed, and in a fully associative cache, all blocks of the cache must be read and compared.
  • Such an address transformation unit is described, for example, in US Pat. No. 4,669,043
  • Table stores the access address of the dpRAM for each address or address group of a block.
  • the significant address bits (index address) for the table are used as the address and the content is the access address of the dpRAM (FIG. 3).
  • a block is the number of bytes which, in the case of a cache miss (lack of the required data in the cache), are jointly fetched from the memory into the cache when an address from this area is read-accessed.
  • the address bits significant for the block are transformed with the table and the remaining (low-order) address bits are adopted unchanged.
  • one of the two ports is set to a higher priority, i. it prevents that is written from both ports simultaneously. Only when the preferred port has performed the write operation may the other port write; if necessary, only one processor has write access for correspondingly allocated memory areas.
  • any write operation to a memory cell one can prevent the same memory cell from being read from the other port, or the read operation can be stored by pausing the read-to-write processor until the write operation is completed.
  • an address comparator of all address bits shown in FIG. 2 is shown
  • the Output signals 213 and 223 may occupy at least three signal states in each case in an advantageous embodiment: enable, wait, equal, wherein enable allows access, wait is to effect a delay, and equal indicates that the same memory area is accessed from both ports. For a pure instruction cache, write access is not necessary; In this case, a signal state "equal" is sufficient for the output signals 213 and 223.
  • the date or command In the case of a cache miss, the date or command must be fetched from a program memory or data memory via the bus system.
  • the incoming data is forwarded to the processing unit and written to the cache in parallel together with the identifier and control bits.
  • the address comparator prevents retrieving the date from the memory if there is no hit but a signal equal (constituent or state of 213 and 223) is displayed by the address comparator.
  • the signal equal is formed in the case of two-sided reading only from the significant address bits, because always the entire block is fetched from the memory. Only when the block is cached can the waiting processing unit access the cache.
  • two separate dual port caches for data and for commands are provided, wherein in the latter usually no write operations are to be provided.
  • the address comparator only checks for equality of the significant address bits and provides the corresponding control signal "equal" in the signals 213 and 223, respectively.
  • the simultaneous read access from both ports only works without restriction if the requested data is present in different address areas which allow simultaneous access.
  • This can be saved in the hardware implementation expenses because not all access mechanisms must be duplicated in memory.
  • the cache can be implemented in several sub-storage areas that can be operated independently of each other. Each partial memory allows only the execution of a port via select signals. FIG. 4 shows such a memory
  • the 4 select signals can be generated from two address bits, since each partial memory uniquely serves a specific address range. For example, with the 2 address bits A + i and A 1, four partial memory areas can be addressed by generating the four select signals E 0 to E 3 corresponding to the binary significance in accordance with Table 1.
  • FIG. 4 For the partial memories 235 and 236 shown in FIG. 4, an exemplary embodiment is shown in FIG.
  • the designated there 260 part memory is executed in this particular embodiment as a single port RAM 280, the addresses, data and control signals are switched depending on the requirement. Switching is done by a multiplexer 275 control circuit 270, depending on the select signals and other control signals 2901 and 2902 (e.g., read, write) from the respective ports. These signals are included together with the data and addresses in the signals 233 and 234, respectively, and are fed to the multiplexer 275 via 5281 and 5282, respectively, depending on the decision of the control circuit 270 corresponding to the output signal 2701 either 5281 or 5282 with the signals 2801 connects.
  • a direct memory is executed in this particular embodiment as a single port RAM 280, the addresses, data and control signals are switched depending on the requirement. Switching is done by a multiplexer 275 control circuit 270, depending on the select signals and other control signals 2901 and 2902 (e.g., read
  • the control circuit can make the forwarding of the signals 5281 or 5282 to 2801 and thus to the single port RAM 280 and also forward the data and other signals from 280 in the opposite direction. This is done in response to a valid select signal and the signals 233 and 234 and / or the order in which the ports cause a read or write operation to the memory 280 via these signals. If the read or write signals become active in the signals 233 and 234 at the same time, one becomes previously defined port first served. This preferred port remains connected to 2801 even if no read or write signal is active. Alternatively, the preferred port may be set dynamically by the processor system, preferably depending on state information of the processor system.
  • This arrangement with a single port RAM is less expensive than a dual port RAM with parallel accessibility, but delays the processing of at least one processing unit when a partial memory (also reading) is accessed at the same time.
  • This arrangement can also be extended to accesses of more than two processors:
  • a multi-port RAM can likewise be implemented in the same way if the switching of the addresses, data and control signals via several multiplexers is provided in steps nadis each other (FIGS. 6 and 7).
  • Such a multi-port RAM 290 is shown in FIG. There, the port input signals 261, 262, ... 267 are decoded in the decoding devices 331, 332, ..337 to the signals 291, 292 ... 297. This decoding generates the select signals for the accesses to the individual RAMs in 281, 282 and 288.
  • FIG. 7 an embodiment for a sub-memory 28x (281 ... 288) is shown in more detail.
  • the select signals and control signals 3901, 3902, ... 3908 are processed from the control signals 291, 292 ... 298 to the output signals 3701, .. 3707.
  • These output signals each control a multiplexer 375 which, depending on the signal value, establishes the connections of the buses 381 or 382 to 387 or 388 with the signals 481... 488.
  • similar controllers 370 and multiplexers 375 are switched accordingly until in a last stage the signals 5901 and 5902 are used for the controller.
  • the output signal 5701 then connects either 581 or 582 to 681 which is connected to the single port RAM.
  • the multiplexers 375 of Figure 7 in addition to the address, data and control signals, also connect the select signals of the next stages contained in 381, 382 ... 388. Furthermore, 375 comparators can be included be in a multi-associative addressing the validity of the data read from the sub-areas.
  • FIG. 8 shows an example of a configurable dual port cache for this purpose.
  • the system mode or configuration signal 1000 is used in decoding the input signals for each of the two ports.
  • the address bit A 1 is not used to address the cache (in direct-mapped mode), but data that differ in addressing only in this bit are stored in the same place in the cache. Only when reading the cache content can be found by the identifier then, whether it is the date sought and accordingly the cach-hit signal are generated.
  • the data including identifier and control bits are transmitted via the signals 291, 292,... 297 to the ports 331, 332,... 337 and further to the signals 261, 262,. .267.
  • This embodiment is shown in Table 3.
  • the user can also make any other division of the cache by multiple configuration signals. This allows a higher hit rate once with a larger cache area and thus reduces the need to fetch the data from main memory.
  • the various processing units do not interfere with each other, if possible accessing only the independent cache areas via the different ports. Since these conditions depend on the programs intended for the application, it is advantageous if there is the possibility of a different configuration depending on the application.
  • the cache can be automatically switched over by the mode signal 1000.
  • FIG. 10 Another embodiment is shown in Figure 10 when there is a multi-associative cache in which the data is read back from each sub-memory 281, 282, ... 288 along with the identifier and control bits.
  • the comparators 2811, 2812, ... 2817, 2821 In the comparators 2811, 2812, ... 2817, 2821,
  • the validity is checked and, depending on the date on the signals 2910, 2920 ... 2970 forwarded together with the validity signals.
  • Switching with mode or configuration signals is optionally just as possible, as already shown and explained in FIG.
  • the validity signals and possibly the mode and configuration signals 1000 are evaluated and the corresponding valid date with the cache hit signal or the cache miss signal is sent to the signals 2610, 2620, .. .2670 forwarded.
  • RAM random access memory
  • FERAM programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable read-only memory
  • MRAM magnetic resonance RAM
  • FERAM programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable programmable

Abstract

L'invention concerne un procédé et un dispositif pour mémoriser des données et/ou des ordres dans un système de calcul comprenant au moins deux unités de traitement et au moins une première mémoire ou zone de mémoire pour des données et/ou des ordres. L'invention est caractérisée en ce que le dispositif comporte une deuxième mémoire ou zone de mémoire, qu'il est conçu comme système d'antémémoire et équipé d'au moins deux points d'accès séparés qui donnent accès aux deux unités de traitement à des cellules mémoires identiques ou différentes de la deuxième mémoire ou zone de mémoire, les données et/ou ordres du premier système de mémoire étant mis en mémoire temporaire par blocs.
EP06777958A 2005-08-08 2006-07-25 Procede et dispositif pour memoriser des donnees et/ou des ordres dans un systeme de calcul comprenant au moins deux unites de traitement et au moins une premiere memoire ou zone de memoire pour des donnees et/ou des ordres Withdrawn EP1915694A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102005037219A DE102005037219A1 (de) 2005-08-08 2005-08-08 Vorrichtung und Verfahren zur Speicherung von Daten und/oder Befehlen in einem Rechnersystem mit wenigstens zwei Verarbeitungseinheiten und wenigstens einem ersten Speicher oder Speicherbereich für Daten und/oder Befehle
PCT/EP2006/064629 WO2007017373A1 (fr) 2005-08-08 2006-07-25 Procede et dispositif pour memoriser des donnees et/ou des ordres dans un systeme de calcul comprenant au moins deux unites de traitement et au moins une premiere memoire ou zone de memoire pour des donnees et/ou des ordres

Publications (1)

Publication Number Publication Date
EP1915694A1 true EP1915694A1 (fr) 2008-04-30

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US (1) US20100005244A1 (fr)
EP (1) EP1915694A1 (fr)
JP (1) JP2009505180A (fr)
CN (1) CN101243416A (fr)
DE (1) DE102005037219A1 (fr)
WO (1) WO2007017373A1 (fr)

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DE102005037219A1 (de) 2007-02-15
WO2007017373A1 (fr) 2007-02-15
US20100005244A1 (en) 2010-01-07
CN101243416A (zh) 2008-08-13
JP2009505180A (ja) 2009-02-05

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