EP1766676A1 - Hybrid epitaxy support and method for making same - Google Patents

Hybrid epitaxy support and method for making same

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Publication number
EP1766676A1
EP1766676A1 EP05775231A EP05775231A EP1766676A1 EP 1766676 A1 EP1766676 A1 EP 1766676A1 EP 05775231 A EP05775231 A EP 05775231A EP 05775231 A EP05775231 A EP 05775231A EP 1766676 A1 EP1766676 A1 EP 1766676A1
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EP
European Patent Office
Prior art keywords
substrate
layer
nitride
insulating
monocrystalline
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Application number
EP05775231A
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German (de)
French (fr)
Inventor
Bruce Faure
Hacene Lahreche
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Soitec SA
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Soitec SA
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Publication of EP1766676A1 publication Critical patent/EP1766676A1/en
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    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/36—Carbides
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/40—AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
    • C30B29/403—AIII-nitrides
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/40—AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
    • C30B29/403—AIII-nitrides
    • C30B29/406—Gallium nitride
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds

Definitions

  • the invention relates to the field of epitaxial techniques, in particular with a view to producing layers of materials such as gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN) or their compounds. It also relates to the field of radio-frequency and hyper-frequency circuits based on materials such as GaN, AlN and their compounds. There is as yet no ingot drawing method similar to that of silicon to obtain monocrystalline substrates of GaN or other nitrides. These materials are mainly obtained by the formation of a thin film by hetero-epitaxy on substrates essentially of sapphire (Al 2 Cb) but also in some cases of silicon carbide (SiC) or silicon (Si).
  • GaN gallium arsenide
  • patteming pattern
  • the GaN has characteristics, such as in particular the energy gap, the breakdown field and the charge carrier saturation rate, which are very interesting from the point of view of the high-frequency applications of power.
  • SiC also has very interesting properties, the main advantage of SiC with respect to GaN being its thermal conductivity, which is more than 4 times higher than that of GaN. This criterion is important for the operation of power components, since the natural heating of the component must be evacuated to the maximum so as not to influence its operation. Nitrides, and in particular GaN and its compounds are obtained by hetero-epitaxy on a foreign material.
  • the main materials used as substrate or thin film epitaxy support are sapphire (Al 2 O 3 ), silicon carbide (SiC) and silicon (111) (Si). These three materials are used for example to produce single layers of GaN or more complex stacks of hetero-structures and superstructures for light-emitting diodes, lasers, radio and microwave components, etc. Silicon is very advantageous because of its ease of obtaining, its low cost and complete control of micro-manufacturing technologies for this material. However, the quality of the GaN layers obtained on Si (111) suffers from the difference in mesh parameter and the difference in the coefficients of thermal expansion between silicon and GaN. Like silicon, SiC has a coefficient of thermal expansion lower than that of GaN.
  • the GaN film epitaxied on silicon carbide is therefore in tension when the temperature is lowered after the step epitaxy performed at high temperature. But this effect is more pronounced on silicon since the difference in coefficient of thermal expansion is greater between Si and GaN than between SiC and GaN.
  • the GaN voltage layer therefore has a tendency to increase its defectivity on silicon and even to crack during cooling. For this reason, but also because of the hexagonal crystalline structure of the SiC and its mesh parameter, close to that of GaN, we obtain on the SiC layers of better quality than on silicon.
  • Sapphire gives good quality epitaxial layers because, unlike silicon and SiC, it has a higher coefficient of thermal expansion than GaN, which makes it possible to maintain the epitaxial layer of GaN in compression when goes down the temperature after epitaxy.
  • This state of compression is the best way to limit the appearance of defects in the GaN layer and, in particular, the cracking of the film as in the case of SiC. Since this possible cracking is linked to a limited thickness of GaN, the use of sapphire makes it possible to obtain thicker layers without cracking or appearance of defects. However, the thickening of the layer makes it possible to partially reduce the defectivity (by annihilation between defects) induced by the difference in crystal lattice parameter between the epitaxial material and the substrate. It is thus possible to obtain epitaxial layers on sapphire of the same crystalline quality as on SiC. Currently, most of the GaN heteroepitaxies are carried out on SiC or sapphire substrates, whatever the intended application.
  • a large number of advanced epitaxial techniques such as the use of more or less complex buffer layer, lateral growth epitaxy (Lateral Epitaxial OverGrowth) or even pendéo-epitaxy, made it possible to obtain layers with fewer and fewer defects and increasingly complex and efficient components, such as quantum super lattice lasers or high mobility electron transistors (HEMTs).
  • the technique giving the best layers of GaN is of course homoepitaxy, that is to say the epitaxy of GaN on a GaN substrate. These GaN substrates are for the moment also obtained from heterogeneous epitaxy and many crystal defects are present in these substrates.
  • Sapphire is naturally insulating and, as already explained above, allows to obtain GaN layers and its compounds of good quality, but its thermal conduction limits the evacuation of heat.
  • SiC has a thermal conductivity more than 10 times higher than that of sapphire and thus ensures very good heat dissipation for GaN-based high-power power components.
  • SiC silicon carbide
  • epitaxial techniques now exist to obtain layers with a minimum of defects.
  • SiC is little used because of its excessively high price. Indeed, for example, for heteroepitaxy treatments, an SiC substrate costs between 10 times for plates (wafers) and 50 times for semi-insulating plates the price of a sapphire substrate. This extra cost induced by the use of SiC limits the use of this type of substrate for high-frequency power applications.
  • massive GaN substrates still have too many disadvantages to constitute an industrial solution. Indeed, these substrates have lower thermal properties than SiC, in particular its thermal conductivity is of the order of that of Si.
  • a hybrid epitaxial support composed of a thin layer of a semi-insulating or insulating material, preferably of SiC or GaN, is produced on a support of polycrystalline material having a high thermal conductivity.
  • An embodiment of a method according to the invention therefore comprises: the formation, in a first SiC or conductive monocrystalline GaN substrate, of an insulating SiC or GaN monocrystalline layer, the transfer of this layer of SiC or monocrystalline GaN onto a second polycrystalline ceramic material substrate having a thermal conductivity greater than or equal to 1.5 W.cm ⁇ .K "1.
  • the cost of producing the epitaxial support is significantly reduced.
  • the cost of a conductive SiC substrate is 5 times less than that of a semi-insulating SiC substrate, and in the case of GaN, the formation of a GaN semi-insulating layer in a conductive GaN substrate to obtain GaN substrates with an electrical conductivity compatible with high-frequency power applications, which is impossible with the GaN currently available in massive form
  • the coating e SiC or monocrystalline GaN can be achieved by ion implantation of hydrogen or rare gas such as helium or argon, or a combination of hydrogen / rare gas (co-implantation) in the first monocrystalline SiC substrate conductor or monocrystalline GaN conductor.
  • This embodiment has the advantage that the SiC or the initially conducting GaN becomes, after the implantation, insulating or semi-insulating, whatever the polytype of the SiC used initially for the first substrate.
  • This high resistivity of the transferred thin film will therefore be retained after, for example, epitaxial growth.
  • a nitride GaN, AlN, InN or compounds.
  • the second substrate on which the insulating monocrystalline SiC layer is reported may be a polycrystalline SiC substrate having an electrical resistivity of at least 10 4 ⁇ .cm or a polycrystalline AIN substrate insulating or having an electrical resistivity of at least 10 4 ⁇ .cm.
  • Polycrystalline SiC has the same thermal expansion and thermal conductivity properties as monocrystalline SiC, and can be obtained in semi-insulating form, with a resistivity greater than or equal to 10 4 ⁇ .cm, for example between 10 4 ⁇ .cm and 10 5 ⁇ .cm.
  • the polycrystalline SiC therefore makes it possible to produce supports for radio and microwave circuits which have electrical and thermal properties equivalent to those obtained with monocrystalline SiC but at a much lower cost.
  • the non-destructive separation of the monocrystalline SiC layer from a portion of the first substrate allows recycling or reuse of this portion of the first substrate, for example to make other epitaxial supports.
  • the transfer of a monocrystalline SiC layer on a polycrystalline SiC support can be done directly without an intermediate layer, or via an insulating layer which may be silicon oxide, or silicon nitride or else other insulating materials with good thermal conductivity. Silicon nitride is particularly well suited for this type of application since it has a relatively high thermal conductivity of 0.3 W / cm / K which is notably greater than that of silicon oxide.
  • the thickness of the intermediate insulating layer can be minimized (for example between 50 nm and 500 nm) to have a very small influence on the thermal evacuation, which will be mainly ensured by the polycrystalline SiC support (which may be several hundred micrometers thick).
  • the transfer of the monocrystalline SiC layer may be carried out by fracturing the first substrate, for example along a layer or an embrittlement plane, and preferably at a temperature between 300 ° C. and 1100 ° C.
  • transfer step of the monocrystalline SiC layer on the second substrate can be carried out by assembling the two substrates by molecular adhesion, be preceded by a chemical or mechanochemical cleaning step, and be followed by an annealing step at a temperature of between 900 ° C.
  • the invention also relates to an epitaxial support comprising a substrate of polycrystalline material having a thermal conductivity greater than or equal to 1.5 W.cm ⁇ .K "1 and an epitaxial growth layer of insulating SiC or monocrystalline GaN
  • the substrate may be an insulating polycrystalline SiC substrate or a polycrystalline AIN substrate which is insulating or has an electrical resistivity of at least 10 4 ⁇ .cm.
  • the substrate may be further formed with other ceramic materials having a thermal conductivity greater than or equal to 1.5 W.cm ⁇ .K 1 and an electrical resistivity of at least 10 4 ⁇ .cm.
  • the epitaxial support further comprises an insulating layer between the polycrystalline substrate and the monocrystalline silicon carbide layer which may be silicon oxide or silicon nitride.
  • the thickness of the insulating layer may be between 10 nm and 3 ⁇ m.
  • the invention further relates to an electronic structure comprising an epitaxial support as described above and at least one layer of a nitride material in which at least one electronic component is made.
  • the material may be gallium nitride (GaN) or aluminum nitride (AIN) or indium nitride (InN) or gallium-indium nitride (InGaN) or a compound of gallium nitride and nitride of nitride.
  • the layer of nitride material is obtained by epitaxial growth carried out on the epitaxial support described above.
  • a conductive active layer is also produced on at least a portion of the nitride layer. This active layer can then be etched to form one or more electronic components such as an inductor, and / or a capacitance and / or a transmission line and / or a transistor.
  • FIGS. 1A to 1F show stages of a process according to the invention
  • FIGS. 2A and 2B show steps of epitaxy and of producing insulating structures using an epitaxial substrate according to the invention
  • FIG. 3 is an example of a HEMT structure based on GaN and AIGaN.
  • a first substrate 2 (FIG. 1A) is a standard conductive monocrystalline SiC silicon carbide of polytype 6H, 4H or 3C.
  • the first substrate 2 may also be made of conductive monocrystalline GaN gallium nitride.
  • the process steps described below in relation to a monocrystalline SiC substrate are implemented with a monocrystalline GaN substrate in place of the SiC substrate, the GaN substrate being a solid GaN substrate or a GaN substrate obtained by epitaxy on another substrate followed by implantation of hydrogen.
  • a second substrate 4 is insulating polycrystalline SiC silicon carbide (typically with a resistivity of 10 4 ⁇ .cm or more). According to an alternative embodiment of the invention, the second substrate 4 may also be polycrystalline aluminum nitride (AlN).
  • layers 6, 8 are deposited or grown in an insulating material, for example of the silicon oxide or silicon nitride type. Other materials can be used if they are insulating and have good thermal conductivity (silicon oxynitride for example). The thickness of these layers may vary from 10 nm or from a few tens of nanometers to 1 ⁇ m or more than one micrometer, for example 3 ⁇ m.
  • an atomic or ion implantation 10 forming a thin layer 12 which extends substantially parallel to a surface 13 of the substrate 2.
  • a layer or an embrittlement or fracture plane delimiting in the volume of the substrate 2 a region 6, 14 intended to constitute a thin film and a region 15 constituting the mass of the substrate 2.
  • This implantation is generally a hydrogen implantation, by example with a dose of between 1.10 16 and 1.10 17 H " / cm 2 and an energy of between 20 and 200 keV
  • the implantation can also be made using other species, or with co-implantation H / He thus obtains a buried layer 12 of defects created by the implantation.
  • This layer separates the substrate 2 from a monocrystalline SiC layer 14 having a thickness of between 10 nm and 1 ⁇ m, made semi-insulating by the ion implantation.
  • different methods can be used to prepare their surfaces for bonding, for example: chemical cleaning of CARO or RCA type (SC1, SC2), so-called "UV-ozone” cleaning, surface activation by plasma, the chemical-mechanical polishing of layers 6 and 8, or the mechano-chemical cleaning of the "scrubber” type, or a combination of these different methods to achieve optimal bonding.
  • the layer 6 and / or the layer 8 can be removed before bonding to obtain a molecular bonding adhesion according to all the possible configurations and, in particular, to have the possibility of direct bonding between the surfaces of the layer 14 and the substrate 4.
  • the two substrates are then assembled (FIG. ID), followed by transfer annealing at a temperature of between 300 ° C. and 1100 ° C. for a duration ranging from a few minutes to several hours depending on the temperature.
  • An example of a heat transfer process could be an annealing of 1 hour at 900 ° C., possibly combined with a feed. mechanical energy. This results in a separation along the embrittlement plane formed by the ionic layer 12.
  • the two substrates 2 and 4 are assembled by a "wafer bonding" type technique or by adhering type contact, for example by molecular adhesion or by gluing.
  • a wafer bonding technique for example by molecular adhesion or by gluing.
  • adhering type contact for example by molecular adhesion or by gluing.
  • a portion of the substrate 2 is then detached by a treatment for causing a fracture along the embrittlement plane 12.
  • An example of this technique is described in the article by AJ. Auberton-Hervé et al. "Why can Smart-Cut change the future of microelectronics? Published in International Journal of High Speed Electronics and Systems, Vol. 10, No. 1 (2000), p. 131-146.
  • the structure 16 (FIG. IE) is completely insulating (insulating substrate 4 and insulating layers 6 and 14). None of the following steps will change this property.
  • a step of high temperature annealing can then be used (between 900 0 C to 1200 0 C) to enhance or eliminate the bonding interface to prevent, thereafter, any risk of delamination of the film 14.
  • Oxidation sacrificial, or a chemical mechanical polishing step or a combination of these two techniques can be used to reduce the roughness of the surface 18, to achieve future epitaxies in the best possible conditions.
  • the roughness of the surface 18 can also be reduced by a plasma dry etching step, by an ion beam etching step, or by annealing operations under a non-oxidizing atmosphere.
  • FIG. 1F monocrystalline SiC substrate 2
  • FIG. 1F monocrystalline SiC substrate 2
  • This recycling makes it possible in particular to greatly reduce the final cost of the structure 16.
  • FIG. 2A an epitaxial layer 22, for example GaN or any material, in particular of the nitride type (InN or AIN or composed of GaN and AlN), for the production of the final components.
  • the epitaxial technique used is for example the MOCVD or MBE or HVPE technique. It is also possible to produce complex structures, for example of the type comprising quantum wells or electron gases of high mobility.
  • the epitaxy temperature not exceeding 1300 0 C for several hours, and in order to maintain the insulating character of the SiC layer 14.
  • This temperature is for example between 700 0 C to 1200 0 C.
  • a GaN semi-insulating layer 22 is first epitaxially grown and then a conductive active layer 24 comprising a high mobility electron gas for the future realization of a HEMT transistor.
  • the final circuit can be manufactured (FIG. 2B) by deleting in particular the active layer by dry or wet etching, in the zones 30 where it is desired to make passive components (inductance, capacitance, transmission line, etc.).
  • FIG. 3 represents a HEMT type structure in section, comprising an SiC substrate 4, provided with an insulating monocrystalline SiC layer 14, obtained according to the invention, and an epitaxial structure, comprising a layer 22 of GaN and a layer 23 in AIGaN.
  • Layer 26 is a passivation layer.
  • the references S, G and D respectively designate the source, the drain and the gate of the transistor obtained.
  • the following table compares the proposed structure with semi-insulating SiC and sapphire.
  • the structure proposed according to the invention (monocrystalline SiC layer insulating on SiC substrate or polycrystalline AIN) will have thermal characteristics (heat removal) and electrical characteristics (insulating nature of the structure) comparable to semi-insulating SiC, but at a much lower cost (about 3 times cheaper than with a monocrystalline semi-insulating SiC substrate), especially thanks to the possibility of recycling the monocrystalline SiC substrate 2 which accounts for most of the total cost of the structure.
  • the semi-insulating GaN can not be obtained so far only by epitaxy and in the form of a thin film difficult to transfer from one medium to another (ie on a polycrystalline substrate SiC or AlN).
  • the structure according to the invention is perfectly compatible with GaN epitaxy, in the same way as semi-insulating monocrystalline SiC. Its properties, such as its insulating nature, will not be modified during epitaxy.

Abstract

The invention concerns a method for making an epitaxy support, including forming, in a first monocrystalline conductive silicon carbide (SiC) or monocrystalline gallium nitride (GaN) substrate, an insulating monocrystalline silicon carbide or an insulating monocrystalline gallium nitride layer. The method further includes transferring said monocrystalline silicon carbide or gallium nitride layer onto a second substrate (4) made of polycrystalline ceramic material having a thermal conductivity not less than 1.5 W.cm<SUP>-1</SUP>.K<SUP>-1</SUP>. The method enables economical and efficient electronic components to be manufactured, in particular for power high frequency applications.

Description

Support d'épitaxie hybride et son procédé de fabrication Hybrid epitaxial support and its method of manufacture
Domaine technique et art antérieurTechnical field and prior art
L'invention concerne le domaine des techniques d'épitaxies, en particulier en vue de la réalisation de couches de matériaux tels que le nitrure de gallium (GaN), le nitrure d'aluminium (AIN), le nitrure d'indium (InN) ou leurs composés. Elle concerne aussi le domaine des circuits radio-fréquences et hyper-fréquences à base de matériaux comme le GaN, AIN et leurs composés. Il n'existe pas encore de méthode de tirage de lingot similaire à celle du silicium pour obtenir des substrats monocristallin de GaN ou d'autres nitrures. Ces matériaux sont obtenus majoritairement par formation d'un film mince par hétéro-épitaxie sur des substrats essentiellement de saphir (AI2Cb) rnais également dans quelques cas de carbure de silicium (SiC) ou de silicium (Si). Bien que l'utilisation sous forme de film mince pour les nitrures soit la plus répandue, on peut également trouver du GaN monocristallin sous forme de matériau massif. Ces substrats sont obtenus par hétéro-épitaxie d'une couche épaisse de GaN (typiquement de l'épaisseur du substrat) sur un substrat de nature différente, comme par exemple de l'arséniure de gallium (111) (GaAs) avec un motif (patteming) particulier à la surface, substrat qui est par la suite supprimé après épitaxie tel que décrit dans le brevet US 6 413 627. Cette approche permet d'obtenir des substrats de relativement bonne qualité mais en petite quantité (non industrielle) et à un coût assez élevé. Les matériaux à grand gap du type nitrure (GaN, AIN, InN et leurs composés) sont le sujet de projets de recherche et de développement très nombreux et très actifs. Les applications pour ces matériaux sont assez diverses. Une des propriétés importantes de ces matériaux est leur grand gap direct, qui leur donne la propriété d'émettre de la lumière bleue, ou de la lumière violette et ultra-violette lorsqu'ils sont composés avec d'autres espèces (nitrure de gallium-indium (InGaN) par exemple) et utilisés dans des structures de composants adaptées (laser UV, LED bleue, LED blanche, etc...)- Grâce à cette propriété de grand gap direct, les matériaux de la famille des nitrures (tels que GaN, AIN, InN, etc..) s'appliquent à un grand nombre d'applications optoélectroniques. Mais, cette propriété de grand gap donne à cette famille de matériaux d'autres propriétés très intéressantes, pour les applications haute fréquence de puissance par exemple. Parmi ces matériaux, le GaN présente des caractéristiques, comme notamment le gap énergétique, le champ de claquage et la vitesse de saturation des porteurs de charge, très intéressantes du point de vue des applications haute-fréquences de puissance. Le SiC a également des propriétés très intéressantes, l'atout principal du SiC par rapport au GaN étant sa conductivité thermique, qui est plus de 4 fois supérieure à celle du GaN. Ce critère est important pour le fonctionnement de composants de puissance, puisque l'échauffement naturel du composant doit être évacué au maximum pour ne pas influencer son fonctionnement. Les nitrures, et notamment le GaN et ses composés sont obtenus par hétéro-épitaxie sur un matériau étranger. Les principaux matériaux utilisés comme substrat ou support d'épitaxie de film mince sont le saphir (AI2O3), le carbure de silicium (SiC) et le silicium (111) (Si). Ces trois matériaux sont utilisés pour par exemple réaliser des couches simples de GaN ou des empilements plus complexes d'hétéro-structures et de superstructures pour les diodes électroluminescentes, les lasers, les composants radio et hyper-fréquences, etc.. Le silicium est très avantageux du fait de sa facilité d'obtention, de son faible coût et de la maîtrise complète des technologies de micro- fabrication pour ce matériau. Mais, la qualité des couches de GaN obtenues sur du Si (111) souffre de la différence de paramètre de maille et de la différence des coefficients de dilatation thermique entre le silicium et le GaN. Comme le silicium, le SiC a un coefficient de dilatation thermique inférieur à celui du GaN. Le film de GaN épitaxié sur du carbure de silicium est donc en tension lorsqu'on diminue la température après l'étape d'épitaxie réalisée à haute température. Mais cet effet est plus marqué sur le silicium puisque la différence de coefficient de dilatation thermique est plus importante entre le Si et le GaN qu'entre le SiC et le GaN. La couche en tension de GaN a donc tendance à voir sa défectivité augmenter sur le silicium et, même, à se fissurer pendant le refroidissement. Pour cette raison, mais aussi du fait de la structure cristalline hexagonale du SiC et de son paramètre de maille, proche de celui du GaN, on obtient sur le SiC des couches de meilleure qualité que sur le silicium. Le saphir permet d'obtenir des couches épitaxiées de bonne qualité car, contrairement au silicium et au SiC, il possède un coefficient de dilatation thermique plus élevé que celui du GaN, ce qui permet de maintenir la couche de GaN épitaxiée en compression lorsqu'on descend la température après l'épitaxie. Cet état de compression est le meilleur moyen de limiter l'apparition de défauts dans la couche de GaN et, en particulier, la fissuration du film comme dans le cas du SiC. Cette fissuration possible étant liée à une épaisseur limite du GaN, l'utilisation du saphir permet donc d'obtenir des couches plus épaisses sans fissuration ou apparition de défauts. Or, l'épaississement de la couche permet de diminuer partiellement la défectivité (par annihilation entre défauts) induite par la différence de paramètre de maille cristalline entre le matériau épitaxié et le substrat. On arrive ainsi à obtenir des couches épitaxiées sur saphir de même qualité cristalline que sur le SiC. Actuellement l'essentiel des hétéro-épitaxies de GaN sont réalisées sur des substrats de SiC ou de saphir, quelle que soit l'application visée. Un grand nombre de techniques avancées d'épitaxies, comme l'utilisation de couche tampon (buffer layer) plus ou moins complexe, l'épitaxie par croissance latérale (Epitaxial Latéral OverGrowth) ou encore la pendéo-épitaxie, ont permis d'obtenir des couches avec de moins en moins de défauts et des composants de plus en plus complexes et performants, comme par exemple les lasers à super-réseau quantique ou les transistors à électrons de haute mobilité (HEMT). La technique donnant les meilleures couches de GaN est bien-sûr l'homo-épitaxie, c'est-à-dire l'épitaxie de GaN sur un substrat GaN. Ces substrats de GaN sont pour l'instant eux aussi obtenus à partir d'hétéro- épitaxie et de nombreux défauts cristallins sont présents dans ces substrats. Néanmoins, leur densité est nettement inférieure à celle d'un film mince obtenu par hétéro-épitaxie (de 100 à 1000 fois moins importante pour les dislocations par exemple). Cela permet d'obtenir des couches d'excellente qualité mais avec certaines limitations comme la taille des substrats réalisés qui est pour l'instant inférieure à 50,8 mm (i.e. 2 pouces) ou leur nombre disponible sur le marché qui est trop faible pour assurer un approvisionnement suffisant. De plus, contrairement aux substrats de SiC, les substrats de GaN disponibles sont uniquement de type conducteur. Techniquement parlant, il a été possible de réaliser toutes sortes de composants, aussi bien sur silicium (111) que sur saphir ou SiC. Toutefois, deux critères sont à prendre en compte si l'on désire utiliser la structure épitaxiée obtenue pour des applications haute-fréquences de puissance : l'évacuation thermique assurée par le substrat pour limiter l'auto-échauffement du composant et assurer la stabilité de son fonctionnement avec de bonnes performances, et le caractère isolant du support du circuit, pour permettre la réalisation de composants passifs (capacité, inductance, etc..) et de lignes de transmission (guide pour l'onde électrique) avec de bonnes caractéristiques et un minimum de perte de signal. Le saphir est naturellement isolant et, comme déjà exposé ci- dessus, permet d'obtenir des couches de GaN et de ses composés de bonne qualité, mais sa conduction thermique limite l'évacuation de la chaleur. Le SiC possède une conduction thermique plus de 10 fois supérieure à celle du saphir et assure donc une très bonne évacuation de la chaleur pour les composants haute-fréquence de puissance réalisés à base de GaN. De plus, des techniques d'épitaxie existent maintenant pour obtenir des couches avec un minimum de défauts. Pourtant, le SiC est peu utilisé en raison de son prix excessivement élevé. En effet, par exemple, pour des traitements d'hétéro-épitaxie, un substrat SiC coûte entre 10 fois pour des plaques (wafers) conductrices et 50 fois pour des plaques semi-isolantes le prix d'un substrat en saphir. Ce surcoût induit par l'utilisation de SiC limite l'utilisation de ce type de substrat pour les applications haute-fréquence de puissance. D'autre part, les substrats de GaN massifs présentent encore trop d'inconvénients pour constituer une solution industrielle. En effet, ces substrats présentes des propriétés thermiques moins bonnes que celle du SiC, en particulier sa conductivité thermique est de l'ordre de celle du Si. De plus, le peu de matériau GaN qui est disponible sur le marché, ne l'est que dans des dimensions insuffisantes pour des applications industrielles et reste très cher (une à deux fois le prix d'un substrat SiC). Enfin, il n'existe pas encore de GaN semi-isolant sous forme de substrat mais seulement sous forme épitaxiée en film mince. L'état actuel de la technologie impose donc un choix entre des composants très performants, à un coût très élevé (sur SiC), et des composants peu performants, à un coût nettement plus faible (sur saphir ou même sur silicium). Il se pose donc le problème de trouver des technqiues alternatives d'épitaxies, et les substrats ou supports correspondants, permettant de réaliser des composants électroniques performants à un coût raisonnable, et notamment des composants à base de matériaux de type nitrure, tels que GaN, ou AIN ou InN ou leurs composés.The invention relates to the field of epitaxial techniques, in particular with a view to producing layers of materials such as gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN) or their compounds. It also relates to the field of radio-frequency and hyper-frequency circuits based on materials such as GaN, AlN and their compounds. There is as yet no ingot drawing method similar to that of silicon to obtain monocrystalline substrates of GaN or other nitrides. These materials are mainly obtained by the formation of a thin film by hetero-epitaxy on substrates essentially of sapphire (Al 2 Cb) but also in some cases of silicon carbide (SiC) or silicon (Si). Although thin-film use for nitrides is the most widespread, monocrystalline GaN can also be found as a bulk material. These substrates are obtained by hetero-epitaxy of a thick layer of GaN (typically the thickness of the substrate) on a substrate of different nature, such as, for example, gallium arsenide (GaAs) with a pattern ( patteming), which substrate is subsequently removed after epitaxy as described in US Pat. No. 6,413,627. This approach makes it possible to obtain substrates of relatively good quality but in a small quantity (non-industrial) and at a higher temperature. cost quite high. Large gap materials of the nitride type (GaN, AlN, InN and their compounds) are the subject of very numerous and very active research and development projects. Applications for these materials are quite diverse. One of the important properties of these materials is their large direct gap, which gives them the property of emitting blue light, or violet and ultraviolet light when they are compounded with other species (gallium nitride). indium (InGaN) for example) and used in structures of suitable components (UV laser, blue LED, white LED, etc ...) - Thanks to this property of large direct gap, the materials of the family of nitrides (such as GaN, AlN, InN, etc.) apply to a large number of optoelectronic applications. But, this property of large gap gives this family of materials other very interesting properties, for high frequency applications of power for example. Among these materials, the GaN has characteristics, such as in particular the energy gap, the breakdown field and the charge carrier saturation rate, which are very interesting from the point of view of the high-frequency applications of power. SiC also has very interesting properties, the main advantage of SiC with respect to GaN being its thermal conductivity, which is more than 4 times higher than that of GaN. This criterion is important for the operation of power components, since the natural heating of the component must be evacuated to the maximum so as not to influence its operation. Nitrides, and in particular GaN and its compounds are obtained by hetero-epitaxy on a foreign material. The main materials used as substrate or thin film epitaxy support are sapphire (Al 2 O 3 ), silicon carbide (SiC) and silicon (111) (Si). These three materials are used for example to produce single layers of GaN or more complex stacks of hetero-structures and superstructures for light-emitting diodes, lasers, radio and microwave components, etc. Silicon is very advantageous because of its ease of obtaining, its low cost and complete control of micro-manufacturing technologies for this material. However, the quality of the GaN layers obtained on Si (111) suffers from the difference in mesh parameter and the difference in the coefficients of thermal expansion between silicon and GaN. Like silicon, SiC has a coefficient of thermal expansion lower than that of GaN. The GaN film epitaxied on silicon carbide is therefore in tension when the temperature is lowered after the step epitaxy performed at high temperature. But this effect is more pronounced on silicon since the difference in coefficient of thermal expansion is greater between Si and GaN than between SiC and GaN. The GaN voltage layer therefore has a tendency to increase its defectivity on silicon and even to crack during cooling. For this reason, but also because of the hexagonal crystalline structure of the SiC and its mesh parameter, close to that of GaN, we obtain on the SiC layers of better quality than on silicon. Sapphire gives good quality epitaxial layers because, unlike silicon and SiC, it has a higher coefficient of thermal expansion than GaN, which makes it possible to maintain the epitaxial layer of GaN in compression when goes down the temperature after epitaxy. This state of compression is the best way to limit the appearance of defects in the GaN layer and, in particular, the cracking of the film as in the case of SiC. Since this possible cracking is linked to a limited thickness of GaN, the use of sapphire makes it possible to obtain thicker layers without cracking or appearance of defects. However, the thickening of the layer makes it possible to partially reduce the defectivity (by annihilation between defects) induced by the difference in crystal lattice parameter between the epitaxial material and the substrate. It is thus possible to obtain epitaxial layers on sapphire of the same crystalline quality as on SiC. Currently, most of the GaN heteroepitaxies are carried out on SiC or sapphire substrates, whatever the intended application. A large number of advanced epitaxial techniques, such as the use of more or less complex buffer layer, lateral growth epitaxy (Lateral Epitaxial OverGrowth) or even pendéo-epitaxy, made it possible to obtain layers with fewer and fewer defects and increasingly complex and efficient components, such as quantum super lattice lasers or high mobility electron transistors (HEMTs). The technique giving the best layers of GaN is of course homoepitaxy, that is to say the epitaxy of GaN on a GaN substrate. These GaN substrates are for the moment also obtained from heterogeneous epitaxy and many crystal defects are present in these substrates. However, their density is much lower than that of a thin film obtained by hetero-epitaxy (100 to 1000 times less important for dislocations, for example). This makes it possible to obtain layers of excellent quality but with certain limitations, such as the size of the substrates produced, which is currently less than 50.8 mm (ie 2 inches), or their number available on the market which is too low for ensure an adequate supply. In addition, unlike SiC substrates, the GaN substrates available are only of conductive type. Technically speaking, it was possible to make all kinds of components, both on silicon (111) and on sapphire or SiC. However, two criteria must be taken into account if it is desired to use the epitaxial structure obtained for high-power power applications: the thermal evacuation provided by the substrate to limit the self-heating of the component and ensure the stability of the its operation with good performance, and the insulating nature of the circuit support, to allow the realization of passive components (capacitance, inductance, etc. ..) and transmission lines (guide for the electric wave) with good characteristics and a minimum of signal loss. Sapphire is naturally insulating and, as already explained above, allows to obtain GaN layers and its compounds of good quality, but its thermal conduction limits the evacuation of heat. SiC has a thermal conductivity more than 10 times higher than that of sapphire and thus ensures very good heat dissipation for GaN-based high-power power components. In addition, epitaxial techniques now exist to obtain layers with a minimum of defects. Yet SiC is little used because of its excessively high price. Indeed, for example, for heteroepitaxy treatments, an SiC substrate costs between 10 times for plates (wafers) and 50 times for semi-insulating plates the price of a sapphire substrate. This extra cost induced by the use of SiC limits the use of this type of substrate for high-frequency power applications. On the other hand, massive GaN substrates still have too many disadvantages to constitute an industrial solution. Indeed, these substrates have lower thermal properties than SiC, in particular its thermal conductivity is of the order of that of Si. In addition, the little GaN material that is available on the market, is not that in insufficient dimensions for industrial applications and remains very expensive (one to two times the price of a SiC substrate). Finally, there is still no semi-insulating GaN in substrate form but only in thin film epitaxial form. The current state of the technology therefore imposes a choice between high-performance components, at a very high cost (on SiC), and poorly performing components, at a much lower cost (on sapphire or even silicon). There is therefore the problem of finding alternative techniques for epitaxies, and the corresponding substrates or supports, making it possible to produce high-performance electronic components at a reasonable cost, and in particular components based on nitride-type materials, such as GaN, or AIN or InN or their compounds.
Résumé de l'inventionSummary of the invention
Selon l'invention, on réalise un support d'épitaxie hybride composé d'une couche mince d'un matériau semi-isolant ou isolant, de préférence en SiC ou en GaN, sur un support en matériau polycristallin ayant une conductivité thermique élevée. Un mode de réalisation d'un procédé selon l'invention comporte donc : - la formation, dans un premier substrat en SiC ou en GaN monocristallin conducteur, d'une couche de SiC ou de GaN monocristallin isolant, - le report de cette couche de SiC ou de GaN monocristallin sur un deuxième substrat en matériau céramique polycristallin ayant une conductivité thermique supérieure ou égale à 1,5 W.cm^.K"1. Ainsi, en formant la couche de SiC monocristallin dans un substrat en SiC conducteur, on diminue significativement le coût de réalisation du support d'épitaxie. En effet, le coût d'un substrat SiC conducteur est 5 fois moins important que celui d'un substrat SiC semi- isolant. Par ailleurs, dans le cas du GaN, la formation d'une couche semi- isolante de GaN dans un substrat GaN conducteur permet d'obtenir des substrats GaN avec une conductivité électrique compatible avec des applications haute-fréquences de puissance, ce qui est impossible avec le GaN actuellement disponible sous forme massive. Selon un mode particulier de réalisation, la couche de SiC ou de GaN monocristallin peut être réalisée par implantation ionique d'hydrogène ou de gaz rare comme de l'hélium ou de l'argon, ou encore une combinaison hydrogène/gaz rare (co-implantation) dans le premier substrat SiC monocristallin conducteur ou de GaN monocristallin conducteur. Ce mode de réalisation présente l'avantage que le SiC ou le GaN initialement conducteur, devient, après l'implantation, isolant ou semi- isolant et ce, quel que soit le polytype du SiC utilisé au départ pour le premier substrat. Cette propriété de forte résistivité du film après transfert par implantation suivie d'un recuit haute température, perdure même après des recuits de plusieurs heures à 13000C. Cette forte résistivité du film mince transféré sera donc conservée après, par exemple, épitaxie d'un nitrure (GaN, AIN, InN ou composés). Le deuxième substrat sur lequel la couche de SiC monocristallin isolant est reportée peut être un substrat de SiC polycristallin présentant une résistivité électrique d'au moins 104 Ω.cm ou un substrat de AIN polycristallin isolant ou présentant une résistivité électrique d'au moins 104 Ω.cm. Le SiC polycristallin possède les mêmes propriétés de dilatation thermique et de conductivité thermique que le SiC monocristallin, et on peut l'obtenir sous forme semi-isolante, avec une résistivité supérieure ou égale à 104 Ω.cm, par exemple comprise entre 104 Ω.cm et 105 Ω.cm. Le SiC polycristallin permet donc la réalisation de supports pour des circuits radio et hyper-fréquences qui présentent des propriétés électriques et thermiques équivalentes à celles obtenues avec du SiC monocristallin mais pour un coût bien moins important. La séparation non-destructive de la couche de SiC monocristallin d'une partie du premier substrat permet un recyclage ou une réutilisation de cette partie du premier substrat, par exemple pour réaliser d'autres supports d'épitaxie. Le report d'une couche de SiC monocristallin sur un support de SiC polycristallin peut se faire directement sans couche intermédiaire, ou bien via une couche d'isolant qui peut être de l'oxyde de silicium, ou du nitrure de silicium ou encore d'autres matériaux isolants avec une bonne conductivité thermique. Le nitrure de silicium est notamment bien adapté pour ce type d'application puisqu'il possède une conductivité thermique assez élevée de 0,3 W/cm/K qui est notamment plus importante que celle de l'oxyde de silicium. De plus, l'épaisseur de la couche isolante intermédiaire peut-être minimisée (par exemple comprise entre 50 nm et 500 nm) pour avoir une influence très faible sur l'évacuation thermique, qui sera majoritairement assurée par le support de SiC polycristallin (qui peut avoir plusieurs centaines de micromètres d'épaisseur). Le report de la couche de SiC monocristallin peut être réalisée par fracture du premier substrat, par exemple le long d'une couche ou d'un plan de fragilisation, et de préférence à une température comprise entre 3000C et 1100 0C. L'étape de report de la couche de SiC monocristallin sur le deuxième substrat peut être réalisée par assemblage des deux substrats par adhésion moléculaire, être précédée d'une étape de nettoyage chimique ou mécano-chimique, et être suivie d'une étape de recuit à une température comprise entre 9000C et 1200 0C. L'invention concerne également un support d'épitaxie comportant un substrat en matériau polycristallin ayant une conductivité thermique supérieure ou égale à 1,5 W.cm^.K"1 et une couche de croissance épitaxiale en SiC ou GaN monocristallin isolant. Le substrat peut être un substrat de SiC polycristallin isolant ou un substrat de AIN polycristallin isolant ou présentant une résistivité électrique d'au moins 104 Ω.cm. Le substrat peut encore être formé avec d'autres matériaux céramiques qui présentent une conductivité thermique supérieure ou égale à 1,5 W.cm^.K"1 et une résistivité électrique d'au moins 104 Ω.cm. Selon une caractéristique de l'invention, le support d'épitaxie comporte en outre une couche isolante entre le substrat polycristallin et la couche en carbure de silicium monocristallin qui peut être en oxyde de silicium ou en nitrure de silicium. L'épaisseur de la couche isolante peut être comprise entre 10 nm et 3 μm. L'invention concerne en outre une structure électronique comportant un support d'épitaxie tel que décrit ci-dessus et au moins une couche d'un matériau de type nitrure dans lequel au moins un composant électronique est réalisé. Le matériau peut être du nitrure de gallium (GaN) ou du nitrure d'aluminium (AIN) ou du nitrure d'indium (InN) ou du nitrure de gallium-indium (InGaN) ou un composé de nitrure de gallium et de nitrure d'aluminium. La couche de matériau de type nitrure est obtenue par une croissance épitaxiale réalisée sur le support d'épitaxie décrit ci-dessus. Selon un aspect particulier, on réalise en outre une couche active conductrice sur au moins une partie de la couche de type nitrure. Cette couche active peut être ensuite gravée de manière à former un ou plusieurs composants électroniques tels qu'une inductance, et/ou une capacité et/ou une ligne de transmission et/ou un transistor. Brève description des figuresAccording to the invention, a hybrid epitaxial support composed of a thin layer of a semi-insulating or insulating material, preferably of SiC or GaN, is produced on a support of polycrystalline material having a high thermal conductivity. An embodiment of a method according to the invention therefore comprises: the formation, in a first SiC or conductive monocrystalline GaN substrate, of an insulating SiC or GaN monocrystalline layer, the transfer of this layer of SiC or monocrystalline GaN onto a second polycrystalline ceramic material substrate having a thermal conductivity greater than or equal to 1.5 W.cm ^ .K "1. Thus, by forming the monocrystalline SiC layer in a conductive SiC substrate, the cost of producing the epitaxial support is significantly reduced. the cost of a conductive SiC substrate is 5 times less than that of a semi-insulating SiC substrate, and in the case of GaN, the formation of a GaN semi-insulating layer in a conductive GaN substrate to obtain GaN substrates with an electrical conductivity compatible with high-frequency power applications, which is impossible with the GaN currently available in massive form According to a particular embodiment, the coating e SiC or monocrystalline GaN can be achieved by ion implantation of hydrogen or rare gas such as helium or argon, or a combination of hydrogen / rare gas (co-implantation) in the first monocrystalline SiC substrate conductor or monocrystalline GaN conductor. This embodiment has the advantage that the SiC or the initially conducting GaN becomes, after the implantation, insulating or semi-insulating, whatever the polytype of the SiC used initially for the first substrate. This property of high resistivity of the film after transfer by implantation followed by high temperature annealing, continues even after annealing for several hours at 1300 ° C. This high resistivity of the transferred thin film will therefore be retained after, for example, epitaxial growth. a nitride (GaN, AlN, InN or compounds). The second substrate on which the insulating monocrystalline SiC layer is reported may be a polycrystalline SiC substrate having an electrical resistivity of at least 10 4 Ω.cm or a polycrystalline AIN substrate insulating or having an electrical resistivity of at least 10 4 Ω.cm. Polycrystalline SiC has the same thermal expansion and thermal conductivity properties as monocrystalline SiC, and can be obtained in semi-insulating form, with a resistivity greater than or equal to 10 4 Ω.cm, for example between 10 4 Ω.cm and 10 5 Ω.cm. The polycrystalline SiC therefore makes it possible to produce supports for radio and microwave circuits which have electrical and thermal properties equivalent to those obtained with monocrystalline SiC but at a much lower cost. The non-destructive separation of the monocrystalline SiC layer from a portion of the first substrate allows recycling or reuse of this portion of the first substrate, for example to make other epitaxial supports. The transfer of a monocrystalline SiC layer on a polycrystalline SiC support can be done directly without an intermediate layer, or via an insulating layer which may be silicon oxide, or silicon nitride or else other insulating materials with good thermal conductivity. Silicon nitride is particularly well suited for this type of application since it has a relatively high thermal conductivity of 0.3 W / cm / K which is notably greater than that of silicon oxide. In addition, the thickness of the intermediate insulating layer can be minimized (for example between 50 nm and 500 nm) to have a very small influence on the thermal evacuation, which will be mainly ensured by the polycrystalline SiC support (which may be several hundred micrometers thick). The transfer of the monocrystalline SiC layer may be carried out by fracturing the first substrate, for example along a layer or an embrittlement plane, and preferably at a temperature between 300 ° C. and 1100 ° C. transfer step of the monocrystalline SiC layer on the second substrate can be carried out by assembling the two substrates by molecular adhesion, be preceded by a chemical or mechanochemical cleaning step, and be followed by an annealing step at a temperature of between 900 ° C. and 1200 ° C. The invention also relates to an epitaxial support comprising a substrate of polycrystalline material having a thermal conductivity greater than or equal to 1.5 W.cm ^ .K "1 and an epitaxial growth layer of insulating SiC or monocrystalline GaN The substrate may be an insulating polycrystalline SiC substrate or a polycrystalline AIN substrate which is insulating or has an electrical resistivity of at least 10 4 Ω.cm. The substrate may be further formed with other ceramic materials having a thermal conductivity greater than or equal to 1.5 W.cm ^ .K 1 and an electrical resistivity of at least 10 4 Ω.cm. According to a characteristic of the invention, the epitaxial support further comprises an insulating layer between the polycrystalline substrate and the monocrystalline silicon carbide layer which may be silicon oxide or silicon nitride. The thickness of the insulating layer may be between 10 nm and 3 μm. The invention further relates to an electronic structure comprising an epitaxial support as described above and at least one layer of a nitride material in which at least one electronic component is made. The material may be gallium nitride (GaN) or aluminum nitride (AIN) or indium nitride (InN) or gallium-indium nitride (InGaN) or a compound of gallium nitride and nitride of nitride. 'aluminum. The layer of nitride material is obtained by epitaxial growth carried out on the epitaxial support described above. According to a particular aspect, a conductive active layer is also produced on at least a portion of the nitride layer. This active layer can then be etched to form one or more electronic components such as an inductor, and / or a capacitance and / or a transmission line and / or a transistor. Brief description of the figures
les figures IA à IF représentent des étapes d'un procédé selon l'invention, - les figures 2A et 2B représentent des étapes d'épitaxie et de réalisation de structures isolantes à l'aide d'un substrat d'épitaxie selon l'invention, la figure 3 est un exemple de structure HEMT à base de GaN et d'AIGaN.FIGS. 1A to 1F show stages of a process according to the invention; FIGS. 2A and 2B show steps of epitaxy and of producing insulating structures using an epitaxial substrate according to the invention; FIG. 3 is an example of a HEMT structure based on GaN and AIGaN.
Exposé détaillé de modes de réalisation de l'inventionDetailed description of embodiments of the invention
Des étapes d'un procédé selon l'invention sont représentées aux figures IA à IF. Dans l'exemple considéré ici, un premier substrat 2 (figure IA) est en carbure de silicium SiC monocristallin conducteur, standard, de polytype 6H, 4H ou 3C. Toutefois, conformément à l'invention, le premier substrat 2 peut être également en nitrure de gallium GaN monocristallin conducteur. Dans ce cas, les étapes du procédé décrites ci-dessous en relation avec un substrat SiC monocristallin sont mises en œuvre avec un substrat en GaN monocritsallin à la place du substrat SiC, le substrat en GaN étant un substrat GaN massif ou un substrat GaN obtenu par épitaxie sur un autre substrat suivie d'une implantation d'hydrogène. Un second substrat 4 est en carbure de silicium SiC polycristallin isolant (typiquement d'une résistivité de 104 Ω.cm ou plus). Selon une variante de réalisation de l'invention, le second substrat 4 peut être aussi en nitrure d'aluminium (AIN) polycristallin. Au cours de l'étape suivante (figure IB), on réalise un dépôt ou une croissance de couches 6, 8 en un matériau isolant, par exemple du type oxyde de silicium ou nitrure de silicium. D'autres matériaux peuvent être utilisés s'ils sont isolants et ont une bonne conductivité thermique (oxynitrure de silicium par exemple). L'épaisseur de ces couches peut varier de 10 nm ou de quelques dizaines de nanomètres à 1 μm ou à plus d'un micromètre, par exemple 3 μm. Il est possible d'utiliser les deux couches 6, 8 ou seulement une des deux. Ces couches peuvent être de même nature ou de nature différente. Dans le substrat 2 est réalisée (figure IC), à travers la couche 6, une implantation atomique ou ionique 10, formant une mince couche 12 qui s'étend sensiblement parallèlement à une surface 13 du substrat 2. En fait, est ainsi formée une couche ou un plan de fragilisation ou de fracture délimitant dans le volume du substrat 2 une région 6, 14 destinée à constituer un film mince et une région 15 constituant la masse du substrat 2. Cette implantation est en général une implantation d'hydrogène, par exemple avec une dose comprise entre 1.1016 et 1.1017 H"/cm2 et une énergie comprise entre 20 et 200 keV. L'implantation peut être aussi faite à l'aide d'autres espèces, ou encore avec une co-implantation H/He. On obtient donc une couche enterrée 12 de défauts créés par l'implantation. Cette couche sépare le substrat 2 d'une couche 14 de SiC monocristallin ayant une épaisseur comprise entre 10 nm et 1 μm, rendue semi-isolante par l'implantation ionique. Avant l'étape d'assemblage des substrats, on peut utiliser différentes méthodes pour préparer leurs surfaces au collage comme par exemple : le nettoyage chimique du type CARO ou RCA (SCl, SC2), le nettoyage dit "UV-ozone", l'activation de surface par plasma, le polissage mécano-chimique des couches 6 et 8, ou bien le nettoyage mécano- chimique du type "scrubber", ou encore, une combinaison de ces différentes méthodes pour arriver à obtenir un collage optimal. Selon des variantes de l'invention, la couche 6 et/ou la couche 8 peuvent être supprimées avant le collage pour obtenir un collage par adhésion moléculaire suivant toutes les configurations envisageables et, en particulier, pour avoir la possibilité de réaliser un collage direct entre les surfaces de la couche 14 et du substrat 4. On réalise alors l'assemblage des deux substrats (figure ID), puis un recuit de transfert à une température comprise entre 3000C et 11000C pour une durée allant de quelques minutes à plusieurs heures selon la température. Un exemple de procédé de transfert thermique pourrait être un recuit de 1 heure à 9000C éventuellement combiné à un apport d'énergie mécanique. Il en résulte une séparation le long du plan de fragilisation formé par la couche ionique 12. Plus précisément, les deux substrats 2 et 4 sont assemblés par une technique de type "wafer bonding" ou par contact de type adhérant par exemple par adhésion moléculaire ou par collage. On pourra se reporter, en ce qui concerne ces techniques, à l'ouvrage de Q.Y. Tong et U. Gosele « Semiconductor Wafer Bonding » (Science and Technology), Wiley Interscience Publications. Une partie du substrat 2 est ensuite détachée par un traitement permettant de provoquer une fracture le long du plan de fragilisation 12. Un exemple de cette technique est décrit dans l'article de AJ. Auberton- Hervé et al. « Why can Smart-Cut change the future of microelectronics ? » paru dans International Journal of High Speed Electronics and Systems, Vol. 10, N°.l (2000), p. 131-146. On obtient ainsi la structure 16 (figure IE) qui est entièrement isolante (substrat isolant 4 et couches 6 et 14 isolantes). Aucune des étapes suivantes ne changera cette propriété. On peut alors utiliser une étape de recuit haute température (entre 9000C et 12000C) pour renforcer ou faire disparaître l'interface de collage, afin d'éviter, par la suite, tout risque de délaminage du film 14. Une oxydation sacrificielle, ou une étape de polissage mécano-chimique ou une combinaison de ces deux techniques, peuvent être utilisées pour diminuer la rugosité de la surface 18, afin de réaliser les futures épitaxies dans les meilleures conditions possibles. La rugosité de la surface 18 peut être également réduite par une étape de gravure sèche par plasma, par une étape de gravure par faisceau d'ions, ou par des opérations de recuits sous atmosphère non-oxydante. Il est alors possible de recycler le substrat 2 de SiC monocristallin (figure IF), par exemple après polissage mécano-chimique et nettoyage chimique, afin notamment de le réutiliser pour le même type d'application. Ce recyclage permet notamment de diminuer grandement le coût final de la structure 16. On peut ensuite réaliser (figure 2A) une couche épitaxiale 22, par exemple de GaN ou de tout matériau, notamment de type nitrure (InN ou AIN ou composé de GaN et de AIN), en vue de la réalisation des composants finaux. La technique d'épitaxie utilisée est par exemple la technique MOCVD ou MBE ou HVPE. Il est également possible de réaliser des structures complexes, par exemple du type comportant des puits quantiques ou des gaz d'électrons de haute mobilité. De préférence, la température d'épitaxie ne dépasse pas 13000C pendant plusieurs heures, et ceci afin de conserver le caractère isolant de la couche de SiC 14. Cette température est par exemple comprise entre 7000C et 12000C. Selon un exemple, pour la réalisation d'un circuit haute-fréquence de puissance, on épitaxie d'abord une couche 22 de GaN semi-isolante et ensuite une couche active conductrice 24 comprenant un gaz d'électrons de haute mobilité pour la réalisation future d'un transistor HEMT. Le circuit final peut être fabriqué (figure 2B) en supprimant notamment la couche active par gravure sèche ou humide, dans les zones 30 où on désire réaliser des composants passifs (inductance, capacité, ligne de transmission, etc.). Dans les régions 30 où la couche conductrice 24 est supprimée, il ne reste plus qu'une structure totalement isolante possédant de très bonnes propriétés d'évacuation de la chaleur, ce qui permet d'obtenir des performances de très bonne qualité pour le circuit réalisé, même à haute fréquence et forte puissance. La figure 3 représente une structure de type HEMT en coupe, comportant un substrat 4 en SiC, muni d'une couche 14 de SiC monocristallin isolant, obtenue conformément à l'invention, et une structure épitaxiée, comportant une couche 22 de GaN et une couche 23 en AIGaN. La couche 26 est une couche de passivation. Les références S, G et D désignent respectivement la source, le drain et la grille du transistor obtenu. Le tableau suivant compare la structure proposée avec le SiC semi-isolant et le saphir. Steps of a method according to the invention are shown in Figures IA to IF. In the example considered here, a first substrate 2 (FIG. 1A) is a standard conductive monocrystalline SiC silicon carbide of polytype 6H, 4H or 3C. However, in accordance with the invention, the first substrate 2 may also be made of conductive monocrystalline GaN gallium nitride. In this case, the process steps described below in relation to a monocrystalline SiC substrate are implemented with a monocrystalline GaN substrate in place of the SiC substrate, the GaN substrate being a solid GaN substrate or a GaN substrate obtained by epitaxy on another substrate followed by implantation of hydrogen. A second substrate 4 is insulating polycrystalline SiC silicon carbide (typically with a resistivity of 10 4 Ω.cm or more). According to an alternative embodiment of the invention, the second substrate 4 may also be polycrystalline aluminum nitride (AlN). During the next step (FIG. 1B), layers 6, 8 are deposited or grown in an insulating material, for example of the silicon oxide or silicon nitride type. Other materials can be used if they are insulating and have good thermal conductivity (silicon oxynitride for example). The thickness of these layers may vary from 10 nm or from a few tens of nanometers to 1 μm or more than one micrometer, for example 3 μm. It is possible to use both layers 6, 8 or only one of the two. These layers may be of the same nature or of a different nature. In the substrate 2 is carried out (FIG. 1C), through the layer 6, an atomic or ion implantation 10, forming a thin layer 12 which extends substantially parallel to a surface 13 of the substrate 2. In fact, is thus formed a layer or an embrittlement or fracture plane delimiting in the volume of the substrate 2 a region 6, 14 intended to constitute a thin film and a region 15 constituting the mass of the substrate 2. This implantation is generally a hydrogen implantation, by example with a dose of between 1.10 16 and 1.10 17 H " / cm 2 and an energy of between 20 and 200 keV The implantation can also be made using other species, or with co-implantation H / He thus obtains a buried layer 12 of defects created by the implantation.This layer separates the substrate 2 from a monocrystalline SiC layer 14 having a thickness of between 10 nm and 1 μm, made semi-insulating by the ion implantation Before the method of assembling substrates, different methods can be used to prepare their surfaces for bonding, for example: chemical cleaning of CARO or RCA type (SC1, SC2), so-called "UV-ozone" cleaning, surface activation by plasma, the chemical-mechanical polishing of layers 6 and 8, or the mechano-chemical cleaning of the "scrubber" type, or a combination of these different methods to achieve optimal bonding. According to variants of the invention, the layer 6 and / or the layer 8 can be removed before bonding to obtain a molecular bonding adhesion according to all the possible configurations and, in particular, to have the possibility of direct bonding between the surfaces of the layer 14 and the substrate 4. The two substrates are then assembled (FIG. ID), followed by transfer annealing at a temperature of between 300 ° C. and 1100 ° C. for a duration ranging from a few minutes to several hours depending on the temperature. An example of a heat transfer process could be an annealing of 1 hour at 900 ° C., possibly combined with a feed. mechanical energy. This results in a separation along the embrittlement plane formed by the ionic layer 12. More specifically, the two substrates 2 and 4 are assembled by a "wafer bonding" type technique or by adhering type contact, for example by molecular adhesion or by gluing. For these techniques, see QY Tong and U. Gosele "Semiconductor Wafer Bonding" (Science and Technology), Wiley Interscience Publications. A portion of the substrate 2 is then detached by a treatment for causing a fracture along the embrittlement plane 12. An example of this technique is described in the article by AJ. Auberton-Hervé et al. "Why can Smart-Cut change the future of microelectronics? Published in International Journal of High Speed Electronics and Systems, Vol. 10, No. 1 (2000), p. 131-146. Thus, the structure 16 (FIG. IE) is completely insulating (insulating substrate 4 and insulating layers 6 and 14). None of the following steps will change this property. A step of high temperature annealing can then be used (between 900 0 C to 1200 0 C) to enhance or eliminate the bonding interface to prevent, thereafter, any risk of delamination of the film 14. Oxidation sacrificial, or a chemical mechanical polishing step or a combination of these two techniques, can be used to reduce the roughness of the surface 18, to achieve future epitaxies in the best possible conditions. The roughness of the surface 18 can also be reduced by a plasma dry etching step, by an ion beam etching step, or by annealing operations under a non-oxidizing atmosphere. It is then possible to recycle the monocrystalline SiC substrate 2 (FIG. 1F), for example after mechanical-chemical polishing and chemical cleaning, in particular to reuse it for the same type of application. This recycling makes it possible in particular to greatly reduce the final cost of the structure 16. It is then possible to produce (FIG. 2A) an epitaxial layer 22, for example GaN or any material, in particular of the nitride type (InN or AIN or composed of GaN and AlN), for the production of the final components. The epitaxial technique used is for example the MOCVD or MBE or HVPE technique. It is also possible to produce complex structures, for example of the type comprising quantum wells or electron gases of high mobility. Preferably, the epitaxy temperature not exceeding 1300 0 C for several hours, and in order to maintain the insulating character of the SiC layer 14. This temperature is for example between 700 0 C to 1200 0 C. According to a for example, for the production of a high-frequency power circuit, a GaN semi-insulating layer 22 is first epitaxially grown and then a conductive active layer 24 comprising a high mobility electron gas for the future realization of a HEMT transistor. The final circuit can be manufactured (FIG. 2B) by deleting in particular the active layer by dry or wet etching, in the zones 30 where it is desired to make passive components (inductance, capacitance, transmission line, etc.). In regions 30 where the conductive layer 24 is removed, there remains only a fully insulating structure having very good heat removal properties, which allows to obtain very good performance for the circuit realized , even at high frequency and high power. FIG. 3 represents a HEMT type structure in section, comprising an SiC substrate 4, provided with an insulating monocrystalline SiC layer 14, obtained according to the invention, and an epitaxial structure, comprising a layer 22 of GaN and a layer 23 in AIGaN. Layer 26 is a passivation layer. The references S, G and D respectively designate the source, the drain and the gate of the transistor obtained. The following table compares the proposed structure with semi-insulating SiC and sapphire.
Tableau 1 : comparaison entre la structure proposée et les autres substrats utilisés.Table 1: Comparison between the proposed structure and the other substrates used.
On voit que la structure proposée selon l'invention (couche SiC monocristallin isolant sur substrat SiC ou AIN polycristallin) aura des caractéristiques thermiques (évacuation de la chaleur) et électriques (caractère isolant de la structure) comparable à du SiC semi-isolant, mais avec un coût nettement inférieur (environ 3 fois moins cher qu'avec un substrat SiC semi-isolant monocristallin), surtout grâce à la possibilité de recycler le substrat 2 de SiC monocristallin qui représente la majeure partie du coût total de la structure. D'autre part, dans le cas de l'utilisation d'un substrat de départ en GaN monocristallin conducteur, il est possible de former des structures telles que celles décrites ci-dessus avec une couche de GaN semi-isolant sous forme de substrat, le GaN semi-isolant ne pouvant être jusqu'ici obtenu que par épitaxie et sous forme d'un film mince difficilement transférable d'un support à un autre (i.e. sur un substrat polycristallin SiC ou AIN). De plus, la structure selon l'invention est parfaitement compatible avec l'épitaxie de GaN, au même titre que le SiC monocristallin semi- isolant. Ses propriétés, comme notamment son caractère isolant, ne seront pas modifiées lors de l'épitaxie. Le procédé selon l'invention utilisé pour réaliser une structure SiC monocristallin/SiC polycristallin, SiC monocristallin/isolant/SiC polycristallin, SiC monocristallin/AIN polycristallin, SiC monocristallin/isolant/AIN polycristallin, GaN monocristallin/SiC polycristallin, GaN monocristallin/isolant/SiC polycristallin, GaN monocristallin/AIN polycristallin, ou bien GaN monocristallin/isolant/AIN polycristallin permet donc d'offrir une alternative à l'utilisation des substrats de SiC semi-isolant monocristallin ou GaN conducteur monocristallin pour l'épitaxie, notamment de nitrure, par exemple pour des applications haute-fréquence de puissance. It can be seen that the structure proposed according to the invention (monocrystalline SiC layer insulating on SiC substrate or polycrystalline AIN) will have thermal characteristics (heat removal) and electrical characteristics (insulating nature of the structure) comparable to semi-insulating SiC, but at a much lower cost (about 3 times cheaper than with a monocrystalline semi-insulating SiC substrate), especially thanks to the possibility of recycling the monocrystalline SiC substrate 2 which accounts for most of the total cost of the structure. On the other hand, in the case of the use of a conductive monocrystalline GaN starting substrate, it is possible to form structures such as those described above with a semi-insulating GaN layer in the form of a substrate, the semi-insulating GaN can not be obtained so far only by epitaxy and in the form of a thin film difficult to transfer from one medium to another (ie on a polycrystalline substrate SiC or AlN). In addition, the structure according to the invention is perfectly compatible with GaN epitaxy, in the same way as semi-insulating monocrystalline SiC. Its properties, such as its insulating nature, will not be modified during epitaxy. The process according to the invention used to produce a monocrystalline SiC / polycrystalline SiC, monocrystalline SiC / insulator / polycrystalline SiC, monocrystalline SiC / AlN SiC structure polycrystalline, monocrystalline SiC / insulator / polycrystalline AIN, monocrystalline GaN / polycrystalline SiC, monocrystalline GaN / insulator / polycrystalline SiC, monocrystalline GaN / polycrystalline AIN, or monocrystalline GaN / insulator / polycrystalline AIN therefore offers an alternative to the use monocrystalline semi-insulating SiC substrates or monocrystalline conductive GaN for epitaxy, especially nitride, for example for high-frequency power applications.

Claims

REVENDICATIONS
1. Procédé de réalisation d'un support d'épitaxie, comportant : - la formation, dans un premier substrat (2) de carbure de silicium (SiC) ou de nitrure de gallium (GaN) monocristallin conducteur, d'une couche (14) de carbure de silicium monocristallin isolant ou de nitrure de gallium monocristallin isolant, - le report de cette couche de carbure de silicium ou de nitrure de gallium monocristallin sur un deuxième substrat (4) en matériau céramique polycristallin ayant une conductivité thermique supérieure ou égale à 1,5 W.cmλK 1.A method of producing an epitaxial support, comprising: forming, in a first substrate (2), silicon carbide (SiC) or conductive monocrystalline gallium nitride (GaN), with a layer (14) ) insulating monocrystalline silicon carbide or insulating monocrystalline gallium nitride, - the transfer of this layer of silicon carbide or monocrystalline gallium nitride to a second substrate (4) of polycrystalline ceramic material having a thermal conductivity greater than or equal to 1.5 W.cmλK 1 .
2. Procédé selon la revendication 1, caractérisé en ce que la couche de carbure de silicium ou de nitrure de gallium monocristallin est réalisée par implantation ionique dans le premier substrat.2. Method according to claim 1, characterized in that the silicon carbide layer or monocrystalline gallium nitride is produced by ion implantation in the first substrate.
3. Procédé selon la revendication 2, caractérisé en ce que l'implantation ionique consiste en une implantation ionique d'hydrogène ou de gaz rare, ou encore une combinaison d'hydrogène et de gaz rare par co-implantation.3. Method according to claim 2, characterized in that the ion implantation consists of an ion implantation of hydrogen or rare gas, or a combination of hydrogen and rare gas by co-implantation.
4. Procédé selon l'une des revendications 1 à 3, caractérisé en ce que le deuxième substrat est un substrat de carbure de silicium polycristallin présentant une résistivité électrique d'au moins 104 Ω.cm.4. Method according to one of claims 1 to 3, characterized in that the second substrate is a polycrystalline silicon carbide substrate having an electrical resistivity of at least 10 4 Ω.cm.
5. Procédé selon l'une des revendications 1 à 3, caractérisé en ce que le deuxième substrat est un substrat de nitrure d'aluminium (AIN) polycristallin isolant ou présentant une résistivité électrique d'au moins 104 Ω.cm.5. Method according to one of claims 1 to 3, characterized in that the second substrate is a polycrystalline aluminum nitride (AIN) substrate insulating or having an electrical resistivity of at least 10 4 Ω.cm.
6. Procédé selon l'une des revendications 1 à 3, caractérisé en ce que la couche de carbure de silicium ou de nitrure de gallium monocristallin présente une résistivité comprise entre 104 et 105 Ω.cm. 6. Method according to one of claims 1 to 3, characterized in that the layer of silicon carbide or monocrystalline gallium nitride has a resistivity of between 10 4 and 10 5 Ω.cm.
7. Procédé selon l'une des revendications 1 à 6, caractérisé en ce qu'il comporte en outre la réalisation d'une couche (6, 8) en un matériau isolant sur au moins l'un des premier et deuxième substrats.7. Method according to one of claims 1 to 6, characterized in that it further comprises the production of a layer (6, 8) of an insulating material on at least one of the first and second substrates.
8. Procédé selon la revendication 7, caractérisé en ce que chaque couche en matériau isolant présente une épaisseur comprise entre 10 nm et 3 μm.8. Method according to claim 7, characterized in that each layer of insulating material has a thickness of between 10 nm and 3 microns.
9. Procédé selon l'une des revendications 1 à 8, caractérisé en ce que le report de la couche de carbure de silicium ou de nitrure de gallium monocristallin est réalisé par fracture du premier substrat.9. Method according to one of claims 1 to 8, characterized in that the transfer of the silicon carbide layer or monocrystalline gallium nitride is produced by fracture of the first substrate.
10. Procédé selon la revendication 9, caractérisé en ce que la fracture du premier substrat est réalisée le long d'une couche ou d'un plan de fragilisation (12).10. The method of claim 9, characterized in that the fracture of the first substrate is made along a layer or an embrittlement plane (12).
11. Procédé selon la revendication 9 ou 10, caractérisé en ce que la fracture du premier substrat est réalisée à une température comprise entre 300 0C et 1100 0C.11. The method of claim 9 or 10, characterized in that the fracture of the first substrate is carried out at a temperature between 300 0 C and 1100 0 C.
12. Procédé selon l'une des revendications 1 à 11, caractérisé en ce que l'étape de report comporte un assemblage des deux substrats (2, 4) par adhésion moléculaire.12. Method according to one of claims 1 to 11, characterized in that the transfer step comprises an assembly of the two substrates (2, 4) by molecular adhesion.
13. Procédé selon l'une des revendications 1 à 12, caractérisé en que l'étape de report est précédée d'une ou plusieurs étapes de nettoyage choisie(s) parmi : nettoyage chimique, nettoyage mécano- chimique, nettoyage dit " UV-ozone ", activation de surface par plasma.13. Method according to one of claims 1 to 12, characterized in that the transfer step is preceded by one or more cleaning steps chosen (s) from: chemical cleaning, mechanical-chemical cleaning, cleaning said "UV- ozone ", plasma surface activation.
14. Procédé selon l'une des revendications 1 à 13, caractérisé en ce que l'étape de report est suivie d'une étape de recuit à une température comprise entre 900 0C et 1200 0C. 14. Method according to one of claims 1 to 13, characterized in that the transfer step is followed by an annealing step at a temperature between 900 0 C and 1200 0 C.
15. Support d'épitaxie (16) comportant : - un substrat (4) en matériau polycristallin ayant une conductivité thermique supérieure ou égale à 1,5 W.cm^.K"1, et - une couche de croissance épitaxiale (14) en carbure de silicium ou nitrure de gallium monocristallin isolant.15. Epitaxial support (16) comprising: - a substrate (4) of polycrystalline material having a thermal conductivity greater than or equal to 1.5 W.cm ^ .K "1 , and - an epitaxial growth layer (14) of silicon carbide or insulating monocrystalline gallium nitride.
16. Support d'épitaxie selon la revendication 15, caractérisé en ce que le substrat est en carbure de silicium polycristallin.16. epitaxy support according to claim 15, characterized in that the substrate is polycrystalline silicon carbide.
17. Support d'épitaxie selon la revendication 15, caractérisé en ce que le substrat est en nitrure d'aluminium (AIN) polycristallin.17. epitaxy support according to claim 15, characterized in that the substrate is polycrystalline aluminum nitride (AlN).
18. Support d'épitaxie selon l'une des revendications 15 à 17, caractérisé en ce qu'il comporte en outre une couche isolante (6,8) entre le substrat (4) polycristallin et la couche en carbure de silicium ou nitrure de gallium monocristallin (14).18. Epitaxial support according to one of claims 15 to 17, characterized in that it further comprises an insulating layer (6,8) between the polycrystalline substrate (4) and the silicon carbide or nitride layer. monocrystalline gallium (14).
19. Support d'épitaxie selon la revendication 18, caractérisé en ce que la couche isolante est en oxyde de silicium ou en nitrure de silicium.19. epitaxy support according to claim 18, characterized in that the insulating layer is silicon oxide or silicon nitride.
20. Support d'épitaxie selon la revendication 19, caractérisé en ce que l'épaisseur de la couche isolante est comprise entre 10 nm et 3 μm.20. epitaxy support according to claim 19, characterized in that the thickness of the insulating layer is between 10 nm and 3 microns.
21. Structure électronique comportant un support selon l'une des revendications 16 à 20, et au moins une couche d'un matériau de type nitrure (22) dans lequel au moins un composant électronique est réalisé.21. Electronic structure comprising a support according to one of claims 16 to 20, and at least one layer of a nitride material (22) in which at least one electronic component is produced.
22. Structure selon la revendication 21, caractérisé en ce que le matériau est du nitrure de gallium (GaN) ou du nitrure d'aluminium (AIN) ou du nitrure d'indium (InN) ou du nitrure de gallium-indium (InGaN) ou un composé de nitrure de gallium et de nitrure d'aluminium.22. Structure according to claim 21, characterized in that the material is gallium nitride (GaN) or aluminum nitride (AIN). or indium nitride (InN) or gallium-indium nitride (InGaN) or a compound of gallium nitride and aluminum nitride.
23. Procédé de croissance épitaxiale d'une couche d'un matériau de type nitrure, dans lequel la couche est réalisée sur un support selon l'une des revendications 16 à 20.23. Process for the epitaxial growth of a layer of a nitride-type material, in which the layer is produced on a support according to one of claims 16 to 20.
24. Procédé selon la revendication 23, caractérisé en ce que le matériau est du nitrure de gallium (GaN) ou du nitrure d'aluminium (AIN) ou du nitrure d'indium (InN) ou du nitrure de gallium-indium (InGaN) ou un composé de nitrure de gallium et de nitrure d'aluminium.24. The method of claim 23, characterized in that the material is gallium nitride (GaN) or aluminum nitride (AIN) or indium nitride (InN) or gallium-indium nitride (InGaN) or a compound of gallium nitride and aluminum nitride.
25. Procédé selon la revendication 23 ou 24, caractérisé en ce qu'on réalise en outre une couche active conductrice (24).25. The method of claim 23 or 24, characterized in that further carries a conductive active layer (24).
26. Procédé selon la revendication 25, caractérisé en ce qu'on grave la couche active (24) de manière à former au moins un composant électronique.26. The method of claim 25, characterized in that the active layer (24) is etched to form at least one electronic component.
27. Procédé selon la revendication 26, caractérisé en ce que le composant électronique comprend une inductance, et/ou une capacité et/ou une ligne de transmission et/ou un transistor. 27. The method of claim 26, characterized in that the electronic component comprises an inductor, and / or a capacitance and / or a transmission line and / or a transistor.
EP05775231A 2004-06-03 2005-06-02 Hybrid epitaxy support and method for making same Withdrawn EP1766676A1 (en)

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