EP1742159A3 - Software-to-Hardware compiler - Google Patents
Software-to-Hardware compiler Download PDFInfo
- Publication number
- EP1742159A3 EP1742159A3 EP06014115A EP06014115A EP1742159A3 EP 1742159 A3 EP1742159 A3 EP 1742159A3 EP 06014115 A EP06014115 A EP 06014115A EP 06014115 A EP06014115 A EP 06014115A EP 1742159 A3 EP1742159 A3 EP 1742159A3
- Authority
- EP
- European Patent Office
- Prior art keywords
- hardware
- software
- constructs
- programmable logic
- decisions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
- G06F30/343—Logical level
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Devices For Executing Special Programs (AREA)
Abstract
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US22347100P | 2000-08-07 | 2000-08-07 | |
EP01962358A EP1356401A2 (en) | 2000-08-07 | 2001-08-07 | Software-to-hardware compiler |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP01962358A Division EP1356401A2 (en) | 2000-08-07 | 2001-08-07 | Software-to-hardware compiler |
Publications (2)
Publication Number | Publication Date |
---|---|
EP1742159A2 EP1742159A2 (en) | 2007-01-10 |
EP1742159A3 true EP1742159A3 (en) | 2007-06-20 |
Family
ID=37487974
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP06014115A Ceased EP1742159A3 (en) | 2000-08-07 | 2001-08-07 | Software-to-Hardware compiler |
Country Status (1)
Country | Link |
---|---|
EP (1) | EP1742159A3 (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7343594B1 (en) * | 2000-08-07 | 2008-03-11 | Altera Corporation | Software-to-hardware compiler with symbol set inference analysis |
EP1356400A2 (en) | 2000-08-07 | 2003-10-29 | Altera Corporation | Inter-device communication interface |
US8959469B2 (en) | 2012-02-09 | 2015-02-17 | Altera Corporation | Configuring a programmable device using high-level language |
CN114610288B (en) * | 2022-05-12 | 2022-09-16 | 之江实验室 | Method and device for realizing back-end compiler based on array type analysis element structure |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0829812A2 (en) * | 1996-09-12 | 1998-03-18 | Sharp Kabushiki Kaisha | Method of designing an integrated circuit and integrated circuit designed by such method |
-
2001
- 2001-08-07 EP EP06014115A patent/EP1742159A3/en not_active Ceased
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0829812A2 (en) * | 1996-09-12 | 1998-03-18 | Sharp Kabushiki Kaisha | Method of designing an integrated circuit and integrated circuit designed by such method |
Non-Patent Citations (5)
Title |
---|
KOUNTOURIS A A ET AL: "High level pre-synthesis optimization steps using hierarchical conditional dependency graphs", EUROMICRO CONFERENCE, 1999. PROCEEDINGS. 25TH MILAN, ITALY 8-10 SEPT. 1999, LOS ALAMITOS, CA, USA,IEEE COMPUT. SOC, US, vol. 1, 8 September 1999 (1999-09-08), pages 290 - 294, XP010352209, ISBN: 0-7695-0321-7 * |
PAGE I: "CONSTRUCTING HARDWARE-SOFTWARE SYSTEMS FROM A SINGLE DESCRIPTION", JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL. IMAGE, AND VIDEO TECHNOLOGY, KLUWER ACADEMIC PUBLISHERS, DORDRECHT, NL, vol. 12, no. 1, 1996, pages 87 - 107, XP000552006, ISSN: 0922-5773 * |
PETERSON J B ET AL: "Scheduling and partitioning ANSI-C programs onto multi-FPGA CCM architectures", FPGAS FOR CUSTOM COMPUTING MACHINES, 1996. PROCEEDINGS. IEEE SYMPOSIUM ON NAPA VALLEY, CA, USA 17-19 APRIL 1996, LOS ALAMITOS, CA, USA,IEEE COMPUT. SOC, US, 17 April 1996 (1996-04-17), pages 178 - 187, XP010206380, ISBN: 0-8186-7548-9 * |
YAMAUCHI T ET AL: "SOP: a reconfigurable massively parallel system and its control-data-flow based compiling method", FPGAS FOR CUSTOM COMPUTING MACHINES, 1996. PROCEEDINGS. IEEE SYMPOSIUM ON NAPA VALLEY, CA, USA 17-19 APRIL 1996, LOS ALAMITOS, CA, USA,IEEE COMPUT. SOC, US, 17 April 1996 (1996-04-17), pages 148 - 156, XP010206377, ISBN: 0-8186-7548-9 * |
YAMAUCHI T ET AL: "SOP: ADAPTIVE MASSIVELY PARALLEL SYSTEM", NEC RESEARCH AND DEVELOPMENT, NIPPON ELECTRIC LTD. TOKYO, JP, vol. 37, no. 3, July 1996 (1996-07-01), pages 382 - 393, XP000631681, ISSN: 0547-051X * |
Also Published As
Publication number | Publication date |
---|---|
EP1742159A2 (en) | 2007-01-10 |
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