EP1590832B1 - Storage cell, storage cell arrangement, and method for the production of a storage cell - Google Patents

Description

The invention relates to a memory cell, a memory cell arrangement and a method for producing a memory cell.

With the rapid development in computer technology, there is a demand for ever faster, denser and more programmable, erasable and readable memory cells.

From the prior art, a non-volatile so-called CHE ("Channel Hot Electron") memory cell is known, which has a field-effect transistor with an electrically conductive floating gate layer between the gate-insulating layer and the control gate. By injecting hot channel electrons, electrical charge carriers are introduced into this memory cell. In the presence / absence of carriers in the floating gate layer, the information storable in the memory cell is coded. In a CHE memory cell, "hot", that is, sufficiently accelerated, electrons or holes in the vicinity of a drain region can pass through the gate insulating layer into the floating gate layer. Due to an electrically insulating region surrounding the floating gate, the introduced electrical charge carriers are protected from flowing out of the floating gate layer and thus remain permanently in the floating gate layer.

In the following, reference is made to Fig.1 A floating gate memory cell 100 known in the art is described.

The floating gate memory cell 100 is integrated in a p-doped silicon substrate 101. In the p-type silicon substrate 101, an n-type well 102 is formed. In the n-doped well 102, a p-doped well 103 is formed. In a first surface region of the p-doped well 103, a first source / drain region 104 is formed as an n ⁺ -doped region. Furthermore, in a second surface region of the p-doped well 103, a second source / drain region 105 is formed as an n ⁺ -doped region. In the surface area of the p-type well 103 between the source / drain regions 104, 105, a channel region 106 is formed. By means of an electrically insulating region 107, a floating gate region 108 arranged above the channel region 106 is electrically insulated from the channel region 106, and a control gate 109, which is arranged above the floating gate region 108, is separated from the floating gate. Section 108 electrically isolated. By means of the Shallow Trench Isolation (STI) regions 110 arranged laterally of the floating gate memory cell 101, the floating gate memory cell 100 of adjacent memory cells (not shown in FIG Fig.1 ) is electrically decoupled from a memory cell array. A predeterminable electrical potential can be applied to the source / drain regions 104, 105 and to the control gate 109 by means of contacting elements 111.

Between the n-doped well 102 and the p-doped well 103, a pn junction 112 is formed.

To introduce electrical charge carriers into the floating gate 108 of the non-volatile floating gate memory cell 100, hot electrons are injected from the substrate using an electrically forward biased pn junction 112. For this purpose, the control gate 109 is brought to a positive electric potential of a sufficiently large amount. Due to the (capacitive) coupling of the floating gate 108 and the control gate 109, this electrical potential also acts on the floating gate 108. The pn junction 112 between the n-doped well 102 and the p-doped well 103 is thus electrically biased, that electrons are injected from the n-doped well 102 into the p-doped well 103. Due to the positive potential at the floating gate 108, electrons are accelerated to the channel region 106 and can be injected into the floating gate 108 through the gate insulating layer formed by the electrically insulating region 107. As a result, information can be programmed into the memory cell 100.

However, the in Fig.1 shown floating gate memory cell 100 has the disadvantage that the entire pn junction 112 must be biased over a large lateral width. This leads to a high energy consumption during programming, erasing and reading of the memory cell 100, which is disadvantageous in particular for low-power applications.

In the following, reference is made to Fig.2 a test arrangement 200 is known which is known for investigations of the reliability of components. In particular, the test arrangement 200 serves to improve the quality or reliability of a gate-insulating Check layer in a previously formed field effect transistor.

The test arrangement 200 is integrated on and in a p-doped silicon substrate 201. In particular, a field-effect transistor 202 is integrated in the test arrangement 200. This includes a first source / drain region 203 formed in a first surface region of the p-doped silicon substrate 201 and a second source / drain region 204 formed in a second surface region of the p-doped silicon substrate 201. Both source / Drain regions 203, 204 are n ⁺ doped regions. Between the two source / drain regions 203, 204, a channel region 208 is formed. Above the channel region 208, a gate region 206 is formed, which is electrically separated from the channel region 208 by means of a gate-insulating layer, which is part of an electrically insulating region 205. Furthermore, contacting elements 207 are provided for applying defined electrical potentials to the source / drain regions 203, 204 or to the gate region 206. On the side of the field-effect transistor 202, an additional n ⁺ -doped region 209 is provided in another surface region of the silicon substrate 201, which region can be electrically driven by means of another contacting element 210. As in Fig.2 can be indicated schematically by means of applying 0V or a positive electrical potential to the source / drain regions 203, 204 and a positive electric potential to the gate region 206 which is stronger in comparison with this positive potential and a negative electrical potential to the n ⁺ -doped region 209 electrical charge carriers, namely electrons, from the n ⁺ -doped region 209 via the p-doped silicon substrate 201 and the channel region 208 through the gate insulating layer until possibly injected into the gate region 206.

1. [1] offenbart eine Flash-Speicherarray-Struktur und ein Verfahren zum Herstellen einer Flash-Speicherarray-Struktur, welche Struktur eine vergrabene Silizidleitung aufweist.
2. [2] offenbart ein Verfahren zum Herstellen und Betreiben einer nichtflüchtigen Flash-Speicherzellen-Struktur mit einem in einem Graben gebildeten Hilfs-Gate.
3. [3] offenbart ein Verfahren zum Programmieren einer elektrisch programmierbaren Speicherzelle, bei der ein n-Well und ein p-Well in einem Substrat separat kontaktierbar sind.
4. [4] offenbart ein Verfahren zum Herstellen einer Flash-Speicherzelle, bei der in einem Substrat ein Bipolartransistor gebildet ist.

However, the in Fig.2 shown test arrangement only for testing the operability of a trained using a semiconductor technology processing field effect transistor 202, in particular for testing the operation of the gate insulating layer of the field effect transistor suitable. It should also be noted that the test arrangement 200 leads to a very large area consumption on a silicon substrate 201.

1. [1] discloses a flash memory array structure and method of fabricating a flash memory array structure having a buried silicide line structure.
2. [2] discloses a method of manufacturing and operating a nonvolatile flash memory cell structure having a trench formed auxiliary gate.
3. [3] discloses a method of programming an electrically programmable memory cell in which an n-well and a p-well are separately contactable in a substrate.
4. [4] discloses a method of manufacturing a flash memory cell in which a bipolar transistor is formed in a substrate.

The invention is based in particular on the problem of providing a memory cell and a memory cell arrangement in which programming with reduced energy requirement is made possible.

The problem is solved by a memory cell, by a memory cell arrangement and by a method for producing a memory cell having the features according to the independent patent claims.

The memory cell according to the invention contains a substrate which contains charge carriers of a first conductivity type. Furthermore, the memory cell includes a first source / drain region in a first surface region of the substrate and a second source / drain region in a second surface region of the substrate. A channel region is formed in a surface region of the substrate between the first and second source / drain regions. Further, a charge storage region is formed over the channel region and a control gate is formed over the charge storage region, which control gate is electrically isolated from the charge storage region. In the substrate, a trench structure is formed, comprising charge carrier material having carriers of a second conductivity type and an isolation region between the substrate and at least a portion of the charge generating material. The first conductivity type is different from the second conductivity type, so that between the substrate and the charge-carrying material of the trench structure, a diode junction, when using a semiconductor material as a charge-carrier material depending on the doping a pn junction or np junction, when used For example, a metal such as tungsten, a Schottky diode is formed. Furthermore, the memory cell is set up in such a way that, by applying predeterminable electrical potentials to the memory cell, electrical charge carriers from the charge carrier-supplying material of the trench structure can be introduced into the charge storage region.

The memory cell arrangement according to the invention contains a plurality of memory cells integrated in the substrate with the features mentioned above.

In the inventive method for manufacturing a memory cell, a first source / drain region is formed in a first surface region of a substrate containing charge carriers of a first conductivity type and a second source / drain region in a second surface region of the substrate. Further, a channel region is formed in the surface region of the substrate between the first and second source / drain regions. A charge storage area is formed over the channel area. A control gate is formed over the charge storage region, which is electrically isolated from the charge storage region. In addition, a trench structure arranged in the substrate is formed, which has charge-generating material with charge carriers of a second conductivity type and an isolation region between the substrate and at least part of the charge-generating material. The first conductivity type is set differently from the second conductivity type, so that a diode junction is formed between the substrate and the charge carrier-supplying material of the trench structure. The memory cell is furthermore set up in such a way that, by applying predeterminable electrical potentials to the memory cell, electrical charge carriers from the charge carrier-supplying material of the trench structure can be introduced into the charge storage area.

A basic idea of the invention is to be seen in that in an integrated memory cell, a trench with increased charge carrier concentration as a supplier of charge carriers for injecting into a charge storage region of the memory cell. The injection can be done by applying presettable electrical potentials to the terminals of the memory cell, in particular to the trench structure and / or the substrate layer and the control gate. Furthermore, the memory cell according to the invention can be implemented in a very space-saving manner since the shallow STI isolation for decoupling adjacent memory cells of a memory cell arrangement can be eroded and can be eroded with an electrically conductive material (for example in n ⁺ -doped) Polysilicon) can be filled. The trench structure formed thereby can be used, on the one hand, as insulation for adjacent components in the substrate and, on the other hand, as a charge carrier emitter sufficiently deep in a substrate, without increasing the space requirement. In view of the need for high-density and securely programmable memory cells, the small space requirement of the memory cell according to the invention represents an important advantage. The memory cell according to the invention is designed for injecting hot electrical charge carriers (electrons or holes) from the trench structure via a substrate into the charged-material storage layer. Clearly, the emitter for emitting electrical charge carriers is embedded in a trench with at least partial sidewall insulation.

The memory cell according to the invention can be realized as an n-channel memory cell or as a p-channel memory cell.

The co-use of filled with electrically conductive material STI insulation as a feed structure of charge carriers for injecting into a charge storage area is a particularly space-saving solution.

It should be noted that the type of conduction (in the case of a p-type or n-type semiconductor material) of charge carriers (dopant atoms in the case of a semiconductor material) is different in the substrate on the one hand and in the trench structure of the trench structure on the other hand. complementary to one another (for example, p-type substrate and n-type or metallic carrier material of the trench structure or n-type substrate and p-type carrier of the trench structure). As a result, a diode junction (pn-junction or Schottky junction) is formed in a junction region between the substrate and the charge carrier-supplying material of the trench structure.

By applying suitably selected electrical potentials to the trench structure or the control gate, it is then possible to operate the diode in the boundary region in the forward direction, and thus to inject electrical charge carriers of the charge carrier material into the substrate towards the charge storage region, which charge carriers pass through the substrate be accelerated due to an applied to the control gate voltage and thus are permanently introduced into the charge storage area.

In particular, the memory cell according to the invention has the advantage that a uniform charge carrier injection into a charge storage layer is made possible, which leads to a lower degradation of the charge storage layer.

Furthermore, a local injection is made possible directly in a neighboring area of a memory cell, since the current paths of the charge carriers in the substrate can be predetermined by applying suitable potentials to the terminals of the memory cell. The local injection of charge carriers in a memory cell leads to a low energy requirement and the ability to address individual cells. Furthermore, the emitter of the electrical charge carriers is embedded in a trench, resulting in a small footprint.

Preferred developments of the invention will become apparent from the dependent claims.

The trench structure preferably extends deeper into the substrate than the first and second source / drain regions. This ensures that electrical charge carriers can be introduced very homogeneously into the charge storage layer. As a result, the service life of the memory cell, in particular the charge storage layer, is increased.

It should also be noted that in the case where the components of the memory cell of the invention are integrated in a well of a given conductivity type formed in the substrate, the vertical depth of the trench structure must not exceed the depth of the well region in the substrate.

The trench structure preferably extends in a substantially vertical direction to the surface of the substrate.

In the memory cell, the trench structure may be formed laterally of at least one of the source / drain regions and outside the channel region.

The memory cell according to the invention may comprise two (or more) trench structures in the substrate, one of which is arranged laterally of the first source / drain region and outside the channel region and the other laterally of the second source / drain region and outside Channel area is arranged. This configuration is symmetrical, giving a particularly homogeneous. Injecting of electric charge carriers in the charge storage layer is made possible. Furthermore, by means of two symmetrically arranged trench structures by means of their isolation regions, the memory cell can be electrically decoupled from both sides of possibly arranged in adjacent areas of the substrate components to avoid unwanted electrical interaction between such components and the memory cell. However, other integrations are also conceivable (e.g., NAND architectures)

The trench structure can have an electrically insulating jacket region on at least part of the side wall of the trench and an electrically conductive core region filled in the trench such that electrical charge carriers can emerge from the trench structure only from those regions into which the core region of a jacket is free with the cladding region, or of such regions in which the cladding region has a sufficiently small thickness to allow a tunneling current of charge carriers from the charge carrier material through the cladding region into the substrate.

For example, the trench structure may be fabricated by first forming a trench in the substrate. Thereafter, e.g. formed in a deposition method or by thermal oxidation, an insulating layer on the side wall of the trench and the bottom thereof. Thereafter, for example, with a unisotropic etching step (e.g., by reactive ion etching (RIE)), the insulating layer is at least partially removed from the bottom of the trench and / or its sidewall at the bottom. Subsequently, the trench is filled with the carrier-emitting material, whereby a diode junction is formed in the contact region. Then, starting from the bottom region of the trench, charge carriers can be introduced from the trench structure into the substrate. For example, in-situ doped polysilicon material or a metal is filled into the cavity introduced in the trench, thereby forming the trench structure.

Preferably, a partial region of the charge carrier-supplying material of the trench structure directly adjoins material of the substrate. However, it is also possible for insulation material of a sufficiently small thickness (typically less than 2 nm) to remain or be formed or introduced between the substrate and the charge-supplying material of the trench structure. In this case, upon application of suitable electrical potentials to the trench structure and the control gate, electrical charge carriers can tunnel through the thin electrically insulating layer.

The charge storage region may be a floating gate. In particular, a trained as a floating gate Charge storage region polysilicon have. In this embodiment, a gate insulating layer for electrically insulating the channel region from the floating gate is provided between the substrate and the floating gate.

Alternatively, the charge storage region may be an electrically insulating charge storage region. As the electrically insulating charge storage region, a silicon oxide-silicon nitride-silicon oxide layer sequence (ONO layer sequence) can be used. Alternatively, the silicon nitride layer may be replaced by another material such as alumina (Al ₂ O ₃ ), yttria (Y ₂ O ₃ ), lanthana (LaO ₂ ), hafnia (HfO ₂ ), and / or zirconia (ZrO ₂ ). In particular, a silicon oxide-aluminum oxide-silicon oxide layer sequence, a silicon oxide-yttrium-silicon oxide layer sequence, a silicon oxide-lanthanum oxide-silicon oxide layer sequence, a silicon oxide-hafnium oxide-silicon oxide layer sequence, a silicon oxide-zirconium oxide layer sequence and / or another layer sequence possible, which allows a permanent charge storage. Such an electrically insulating charge storage region is also referred to as a charge trapping layer. For example, when using an ONO layer sequence, electrical charge carriers are injected into the silicon nitride layer of the ONO layer sequence, where they are permanently stored, in particular, in imperfections.

The substrate may have a well region that has the charge carriers, in particular doping atoms, of the first conductivity type, and may have a charge carrier, in particular dopant atoms, of the region having the second conductivity type, wherein the components of the storage cell are formed in the well region. In other words, as the substrate of the memory cell of the present invention, it is not necessary to use a homogeneous substrate become. It is possible, for example, to form an n-doped well region in a p-doped substrate and to form the memory cell according to the invention therein. Also, a multiple well structure of vividly interleaved well regions of different conductivity types is possible (eg, an n-well in a p-substrate and a p-well in the n-well).

The memory cell can have a plurality of spatially separated control gates which can be controlled separately, such that by applying predeterminable electrical potentials to at least one selected one of the control gates, electrical charge carriers can be introduced from the trench structure into an area of the charge storage area adjacent to the at least one selected control gate. Such an embodiment is for example in fig.11 shown.

According to one aspect of this embodiment, a plurality of field-effect transistors in the memory cell according to the invention can illustratively be formed next to one another in the substrate. Each of the transistors is assigned its own control gate. Furthermore, a common charge storage layer can be provided for all the field-effect transistors; alternatively, each transistor can have its own charge storage layer.

According to another aspect of the considered embodiment, a memory cell of the invention may comprise only one field effect transistor, in the charge storage area in each of two spatially separated sections charge carriers can be introduced, each of the sections may be associated with a separately controllable control gate. In such a case, information of one bit may be stored in each of the sections, so that a plurality of bits can be stored in a field effect transistor.

Thus, the memory cell according to the invention can be set up such that several bits of information can be stored in the memory cell. Clearly n bit information can be stored in the charge storage layer using n control gates.

Such a multi-bit memory cell may be programmed, for example, as follows. First of all, by means of the inventive injection of hot charge carriers, all information can be deleted from the charge storage layer or the charge storage layers of the at least one field-effect transistor, which clearly corresponds to resetting the memory contents. This can be done, for example, by the fact that hot electrons can be introduced into the entire charge storage layer. Subsequently, each portion of the charge storage layer associated with a respective control gate may be fowled, for example, by Fowler-Nordheim tunneling, i. with particularly good spatial resolution and thus limited to a specific selected area of the charge storage layer, be programmed separately. Thus, the memory cell of the invention is set up as a high-density storage medium.

In the memory cell, the charge carriers of the first conductivity type and / or the charge carriers of the second conductivity type can be doping atoms. This refinement relates in particular to realizations of the memory cell using a semiconductor material for the substrate and / or the charge-supplying material.

In the following, the memory cell arrangement according to the invention, which has memory cells according to the invention, will be described in more detail. Embodiments of the memory cell also apply to the memory cell having memory cell arrangement.

The memory cell arrangement may be designed such that different memory cells are electrically decoupled from one another by means of the electrically insulating jacket regions. This refinement corresponds to the realization of the trench structure using a clearly hollowed-out STI structure which, apart from its isolation function, additionally fulfills the function of a charge carrier feed structure for injecting electrical charge carriers into the substrate.

In the following, the inventive method for producing the memory cell according to the invention will be described in more detail. Embodiments of the memory cell also apply to the method for producing the memory cell and vice versa.

It is possible to first make the trench structure and then fabricate the source / drain regions and the gate structure (i.e., charge storage region and control gate).

The trench structure may be formed by forming at least one trench in the substrate, forming an electrically insulating cladding region at least on at least a part of the surface of the at least one trench, and forming an electrically conductive core region in the at least one trench. According to this embodiment, for example, first a trench in the substrate are introduced and subsequently formed an electrically insulating jacket area. This can be done, for example, by generating an electrically insulating layer by means of thermal oxidation of the side wall of the trench. Subsequently, charge carrier-supplying material, for example doped polysilicon, can be introduced into the obtained arrangement, whereby the trench structure is formed.

Alternatively, the trench may be filled with electrically insulating material and partially removed from the trench using a lithography and an etching process. In the method, the trench structure can thus be formed by forming at least one trench in the substrate and filling the trench with electrically insulating material. A part of the electrically insulating material is removed from the trench, whereby the electrically insulating cladding region is formed. An electrically conductive core region is formed in the at least one trench.

Embodiments of the invention are illustrated in the figures and are explained in more detail below.

Figur 1

eine Speicherzelle gemäß dem Stand der Technik,

Figur 2

eine Test-Anordnung gemäß dem Stand der Technik,

Figur 3

eine Speicherzelle gemäß einem ersten Ausführungsbeispiel der Erfindung,

Figur 4

eine Speicherzelle gemäß einem zweiten Ausführungsbeispiel der Erfindung,

Figur 5

eine Speicherzelle gemäß einem dritten Ausführungsbeispiel der Erfindung,

Figur 6

eine Speicherzelle gemäß einem vierten Ausführungsbeispiel der Erfindung,

Figur 7

eine Speicherzelle gemäß einem fünften Ausführungsbeispiel der Erfindung,

Figur 8

eine Speicherzelle gemäß-einem sechsten Ausführungsbeispiel der Erfindung,

Figur 9

die in Figur 3 gezeigte Speicherzelle in einem Betriebszustand zum Einbringen von Elektronen in den Ladungsspeicherbereich,

Figur 10

die in Figur 4 gezeigte Speicherzelle in einem Betriebszustand zum Einbringen von Löchern in die Ladungsspeicherschicht,

Figur 11

eine Speicherzelle gemäß einem siebten Ausführungsbeispiel der Erfindung,

Figur 12

eine Layout-Ansicht einer Speicherzellen-Anordnung gemäß einem Ausführungsbeispiel der Erfindung,

Figur 13

eine Speicherzelle gemäß einem achten Ausführungsbeispiel der Erfindung,

Figur 14

eine Layout-Ansicht einer Speicherzellen-Anordnung gemäß einem anderen Ausführungsbeispiel der Erfindung.

Show it:

FIG. 1

a memory cell according to the prior art,

FIG. 2

a test arrangement according to the prior art,

FIG. 3

a memory cell according to a first embodiment of the invention,

FIG. 4

a memory cell according to a second embodiment of the invention,

FIG. 5

a memory cell according to a third embodiment of the invention,

FIG. 6

a memory cell according to a fourth embodiment of the invention,

FIG. 7

a memory cell according to a fifth embodiment of the invention,

FIG. 8

a memory cell according to a sixth embodiment of the invention,

FIG. 9

in the FIG. 3 shown memory cell in an operating state for introducing electrons in the charge storage area,

FIG. 10

in the FIG. 4 shown memory cell in an operating state for introducing holes in the charge storage layer,

FIG. 11

a memory cell according to a seventh embodiment of the invention,

FIG. 12

a layout view of a memory cell array according to an embodiment of the invention,

FIG. 13

a memory cell according to an eighth embodiment of the invention,

FIG. 14

a layout view of a memory cell array according to another embodiment of the invention.

The same or similar components in different figures are provided with the same reference numerals.

The illustrations in the figures are schematic and not to scale.

In the following, reference is made to Figure 3 a memory cell 300 according to a first embodiment of the invention described.

The memory cell 300 is formed on and in a p-doped silicon substrate 301. In a first surface region of the p-doped silicon substrate 301, a first source / drain region 302 is formed as an n ⁺ -doped region. In a second surface region of the p-doped silicon substrate 301, a second source / drain region 303 is formed as an n ⁺ -doped region. In the surface region between the first and second source / drain regions 302, 303, a channel region 304 of the floating gate arrangement 300 is formed. In the substrate 301, laterally from the first source / drain region 302 and outside the channel region 304, a first trench structure 305 is formed, which comprises a first n ⁺ -doped polysilicon core 307 and a first silicon oxide partially formed around it. Sheath 308 contains. In the substrate 301, laterally of the second source / drain region 303 and outside of the channel region 304, a second trench structure 306 is formed. This includes a second n ⁺ -doped polysilicon core 309 and second silicon oxide cladding 310 surrounding the core 309. By means of an electrical insulation region 311 made of silicon oxide material, the channel region 304 is electrically separated from a floating gate 312 made of polysilicon material. Furthermore, means of the electrical isolation region 311, the control gate 313 formed over the floating gate 312 is electrically isolated from the floating gate 312. Contacting elements 314 are realized as vias and make it possible to provide the trench structures 305, 306 with a predeterminable electrical potential. Between the first n ⁺ -doped polysilicon core 307 and the p-doped substrate 301, a first pn junction 315, that is, a first diode junction is provided. Furthermore, a second pn junction 316 is realized between the second n ⁺ -doped polysilicon core 309 and the p-doped silicon substrate 301.

The trench structures 305, 306 have due to the Siliziumoxid-coats 308, 310, an electrical insulation of in Figure 3 shown memory cell of possibly formed in adjacent portions of the substrate 301 other components, such as other memory cells on.
In 3 to Fig.8 Implementation possibilities are described based on a p-substrate. The same implementation variants are also possible on an n-substrate (reverse doping for substrate, wells, trench filling, source / drain). Instead of an n ⁺ filling of the trench, a metallic filling, for example of tungsten material, can also be used ,

In the following, reference is made to Figure 3 . Figure 9 describes how electrical charge carriers can be introduced into the n ⁺ -type floating gate 312 made of polysilicon as a charge storage region, that is, how information can be programmed into the storage cell 300.

For writing memory information into the nonvolatile memory cell 300, that is, permanently introducing electrons into the floating gate 312, as shown in FIG Figure 9 shown, the first and second n ⁺ -doped polysilicon cores 307, 309 brought to a negative electrical potential (eg of -2 volts). The source / drain regions 302, 303 are held at the potential of the substrate. To the control gate 313 (which may or may not be doped n ^+, for example) a positive electrical potential of eg + 8 volts is applied. The doping of the gate regions is of no particular importance, so that no definition of a specific doping type is given. The p-doped silicon substrate 301 can be held at the electrical ground potential. At the described potential ratios, electrons from the first n ⁺ -doped polysilicon core 307 of the trench structure 305 and from the second n ⁺ -doped polysilicon core 309 of the second trench structure 306 at the pn junctions 315, 316 to the p-doped Substrate 301 exit into the substrate 301. It should be noted that in those areas where the p-doped substrate 301 is separated from the n ⁺ doped polysilicon cores 307, 308 by the silicon oxide cladding regions 308, 310, leakage of electrical charge carriers is avoided because, the thickness of the electrically insulating jacket portions 308, 310 is so thin that an electrical tunneling current is made possible. Illustratively, first electrons 902 are injected into the silicon substrate 201 due to the forward biased diodes 315, 316, as indicated by first current paths 900. Due to the strong positive bias of the control gate 313, the injected negatively charged first electron 902 accelerates toward the channel region 304 of the p-doped substrate 301, which is illustrated by means of second current paths 901. The accelerated, "hot" second electrons 903 can then pass through the gate insulating layer of the electrical isolation region 311, that is to say between the channel region 304 and the floating gate 312, and be injected into the floating gate 312 and remain there permanently.

In a first operating state, in which the floating gate 312 is ideally free of electrical charge carriers, the floating gate memory cell 300 has a different threshold voltage than in a scenario in which electrical charge carriers are injected in the floating gate 312. Illustratively, electrons contained within the floating gate 312 act similarly to an external electrical voltage applied to the control gate 313, so that the amount of current flow between the source / drain regions 302, 303 is dependent upon a fixed voltage applied therebetween. whether electric charge carriers are injected in the floating gate 312 or not. The magnitude of such a read current includes information having a logical value "1" (e.g., floating gate electrodes 312) or a logic "0" (e.g., floating gate 312 electrons).

In the following, reference is made to Figure 4 a memory cell 400 according to a second embodiment of the invention described.

The memory cell 400 differs from the memory cell 300 essentially in that the conductivity types of the doped regions are designed differently in the memory cell 400 than in the memory cell 300.

The memory cell 400 also has a p-doped silicon substrate 301. However, in the p-doped silicon substrate 301, an n-doped well region 401 is formed, which may also be referred to as a high-voltage n-well region. As the first and second source / drain regions 402, 403, p ⁺ -doped regions are formed in the first and second surface regions of the n-well region 401. Furthermore, first and second trench structures 404, 405 are provided which extend from the first and second trench structures 305, 306 Figure 3 in that first and second p ⁺ doped polysilicon cores 406, 407 of the trench structures 404, 405 are made of p ⁺ doped polysilicon, rather than of nu doped polysilicon as in FIG Figure 3 , are made. This in Figure 4 provided n ⁺ -doped control gate can alternatively be realized as a p ⁺ -doped control gate. Also in the memory cell 400, the junction between the first p ⁺ -doped polysilicon core 406 and the n-well region 401 forms a first diode 315, and the junction between the second n ⁺ -doped polysilicon core 407 and the n-well region 401 forms a second diode 316.

In the following, reference is made to Figure 4 . Figure 10 the functionality of memory cell 400 is described.

In Figure 10 2 shows what potentials are to be applied to the terminals of the memory cell 400 in order to inject hot holes (designated h ⁺ in the figures) into the floating gate 312. For this purpose, the first and second p ⁺ -doped polysilicon cores 406, 407 are brought to a potential of, for example, + 2 volts. The source / drain terminals 402, 403 are held at the potential of the n-well 401. The terminals of the p-doped substrate 301 and the n-well region 401 are preferably maintained at the electrical ground potential. The control gate 408, however, is brought to a negative potential of, for example, -8 volts. It should be noted that the n-well can be set to a positive potential. As a result, all other applied potentials are to be seen in relation to this positive n-well potential. The diodes 315, 316 are according to Figure 10 operated in the forward direction. Due to the forward-biased diodes 315, 316, first holes 1002 h ^{+ are} injected into the n-well region 401, as illustrated by first current paths 1000. Due to the high negative potential at the control gate 408, the positively charged first 1002 holes are accelerated toward the channel region 304, thereby converting the first holes 1002 into "hot" second holes 1003. The second holes 1003, due to their sufficiently high kinetic energy, can reach the floating gate region 312 into which they are injected. Again, by means of a shift of the threshold voltage of the transistor-like arrangement 400, it can be determined whether or not electrical charge carriers (namely, holes) are injected in the floating gate 312 of the memory cell 400. A read current at a high voltage at a constant voltage between the source / drain regions 402, 403 may be assigned to information of logical value "1" and "0", respectively.

In the following, reference is made to Figure 5 a memory cell 500 according to a third embodiment of the invention described.

In the Figure 5 shown memory cell 500 differs from that in Figure 3 shown memory cell 300 substantially in that the memory cell is not formed directly in the p-doped substrate 301, but in a p-doped small well region 502, which in turn is formed within an n-doped large well region 501. In other words, it is not necessary that the memory cell according to the invention directly in a. Substrate is integrated, but it can also be formed in an introduced into the substrate well area. In particular, in such a well construction, a negative potential can be applied to the (inner) p-well. This means that the voltages applied to other areas must always be seen in relation to this negative well potential.

In the following, reference is made to Figure 6 a memory cell 600 according to a fourth embodiment of the invention described.

In the Figure 6 shown memory cell 600 differs from that in Figure 3 shown memory cell 300 substantially in that instead of the floating gate 312 as a charge storage region, a silicon nitride layer (Si ₃ N ₄ ) 601 sandwiched between two silica partial layers of the electrical insulation region 311, whereby between the channel region 304 and the control gate 313, an ONO layer sequence (silicon oxide-silicon nitride-silicon oxide) is formed. In the memory cell 600, the silicon nitride layer 601 of the ONO layer sequence is used as a charge trapping layer, that is, as an electrically insulating charge storage region. The injection of electrons into the silicon nitride layer 601 is similar to the injection of electrons into the floating gate 312 in the memory cell 300, due to the electrical insulating property of silicon nitride material, the charge carriers placed in the silicon nitride layer 601 remain at the respective injection site within the silicon nitride layer 601 and are not distributed freely in the charge storage region.

In the following, reference is made to Figure 7 a memory cell 700 according to a fifth embodiment of the invention described.

The memory cell 700 differs from that in FIG Figure 4 1, that the floating gate 312 from Figure 4 is replaced by the silicon nitride layer 601.

In the following, reference is made to Figure 8 a memory cell 800 according to a sixth embodiment of the invention described.

The memory cell 800 differs from the one in FIG Figure 5 shown memory cell 500 in that the floating gate 312 is replaced by the silicon nitride layer 601.

In the following, reference is made to Figure 11 a memory cell 1100 according to a seventh embodiment of the invention described.

In the fig.11 shown memory cell 1100 differs from that in Figure 6 shown memory cell 600 substantially by, 1 that instead of only one memory field effect transistor in Figure 6 according to fig.11 a first memory field effect transistor 1101 and at least one second memory field effect transistor 1102 are formed. The Control gates 313 of the first and second memory field effect transistors 1101, 1102 can be controlled separately. The control gates 313 of the two memory field-effect transistors 1101, 1102 are spatially separated from one another and can be driven separately electrically. As a charge storage region, the memory cell 1100 has an ONO layer sequence 1103, which is formed from a first silicon oxide layer 1104, a silicon nitride layer 1105 as a "charge trapping layer" and a second silicon oxide layer 1106.

As described below, by applying predeterminable electrical potentials to the terminals of the memory cell 1100, electrons from the trench structures 305, 306 can be introduced into the ONO layer sequence 1103.

According to the in fig.11 In the scenario shown, a negative electrical potential of, for example, -2 volts is applied to the n ⁺ -doped polysilicon cores 307, 309 of the trench structures 305, 306. To the control gates 313 of the first and the second memory field effect transistor 1101, 1102, in each case a positive electrical potential of, for example, + 8 volts is applied. Due to the potential relationships, the electrons emerging from the diodes 315, 316 are accelerated towards the channel regions 304 of the memory field effect transistors 1101, 1102 and injected in a first charge storage region 1107 and in a second charge storage region 1108 of the ONO layer sequence 1103. This process step may be referred to as resetting the memory contents of the field effect transistors 1101, 1102.

To selectively select into a selected one of the first and second charge storage regions 1107 or 1108 Programming memory information of one bit, Fowler-Nordheim tunneling selectively removes the electrons introduced into the respective charge storage region 1107 or 1108 by injecting hot electrons. In this case, the very good spatial resolution of Fowler-Nordheim programming can be used to advantage in the introduction / removal of charge carriers.

Thus, it is possible for the memory cell 1100 to separately describe different memory field effect transistors of the memory cell. Thereby, the memory cell of the invention can be used as a multi-bit memory cell such as a 2-bit memory cell as in FIG fig.11 , be realized.

Clearly, different areas of the ONO layer sequence 1103 can be operated as a charge storage layer for the separate introduction / removal of electrical charge carriers and thus as separate information bit storage areas.

An advantageous mode of operation of such a memory cell 1100 is that first all memory cells are reset by injecting charge carriers (for example by means of hot carrier tunnels) into the entire charge storage layer 1103. The programming of information is then performed using location-specific removal of charge carriers from a selected region of the charge storage layer, e.g. using Fowler-Nordheim tunnels.

Alternatively, hot carrier injection may be selective by applying the one control gate as described puts a positive potential, leaves the other control gate to substrate or well potential. As a result, the charge carriers are selectively accelerated only to a gate, whereby a selective programming is achieved.

Furthermore, it should be noted that the in fig.11 described implementation also with the in Fig.7 and Fig.8 featured tub construction is analogous possible.

In the following, reference is made to Figure 12 a schematic layout view (top view) of a memory cell array 1200 according to an embodiment of the invention described.

The memory cell array 1200 includes a plurality of memory cells, such as those shown in FIG Figure 3 are shown. For clarity are in Figure 12 Reference number from Figure 3 inserted. The memory cell array 1200 is realized SNOR architecture.

The control gate 313 is in Figure 12 for a row of memory cells running together and is thus realized similar to a conductor track. By means of a substrate contacting (not in Fig. 12 drawn), a defined electrical potential can be provided to the substrate 301. Furthermore, printed conductors 1202 and printed circuit vias 1203 or contact holes 1201 are shown, by means of which the source / drain regions can be contacted.

In the following, reference is made to Figure 13 a memory cell 1300 according to an eighth embodiment of the invention described.

The memory cell 1300 differs from the memory cell 1100 essentially in that of FIG fig.11 right, ie the second source / drain region 303 of the first memory field effect transistor 1101 with the according to fig.11 left, ie second source / drain region 302 of the second memory field effect transistor 1102 is designed as a common source / drain region 1301. The common source / drain region 1301 thus represents a coherent implantation region. Such a combination of two source / drain regions of two adjacent memory cells can also be realized for a memory cell arrangement having a multiplicity of memory cells. If you put the source / drain regions 303/302 together, you will clearly get a kind of NAND structure.

In the following, reference is made to Figure 14 a schematic layout view (top view) of a memory cell array 1400 according to another embodiment of the invention described, wherein in the memory cell array tracks 1401 are provided.

The memory cell array 1400 Figure 14 FIG. 12 illustrates a schematic layout from which it can be seen how memory cells according to the invention can be integrated into a NAND structure. Integration into other arrangements (eg NOR, ...) is also possible. Therefore, the examples shown are for illustrative purposes only, without being limited to any particular memory arrangement.

• [1] US 2003/0006448 A1
• [2] US 6,518,126 B2
• [3] US 6,366,499 B1
• [4] US 6, 329, 246 B1

This document cites the following publications:

• [1] US 2003/0006448 A1
• [2] US 6,518,126 B2
• [3] US 6,366,499 B1
• [4] US Pat. No. 6,329,246 B1

LIST OF REFERENCE NUMBERS

• 100 floating gate memory cell
• 101 p-doped silicon substrate
• 102 n-doped tub
• 103 p-doped tub
• 104 first source / drain region
• 105 second source / drain region
• 106 channel area
• 107 electrically insulating area
• 108 floating gate area
• 109 control gate
• 110 STI area
• 111 contacting elements
• 112 pn junction
• 200 test aria order
• 201 p-doped silicon substrate
• 202 field effect transistor
• 203 first source / drain region
• 204 second source / drain region
• 205 electrically insulating area
• 206 gate area
• 207 contacting elements
• 208 channel area
• 209 n ⁺ doped area
• 210 other contacting element
• 300 memory cell
• 301 p-doped substrate
• 302 first n ⁺ doped source / drain region
• 303 second n ⁺ doped source / drain region
• 304 channel area
• 305 first trench structure
• 306 second trench structure
• 307 first n ⁺ -doped polysilicon core
• 308 first silicon oxide jacket
• 309 second n ⁺ -doped polysilicon core
• 310 second silica shell
• 311 electrical insulation area
• 312 floating gate
• 313 n ⁺ control gate
• 314 contacting elements
• 315 first pn junction
• 316 second pn junction
• 400 memory cell
• 401 n-tub area
• 402 first p ⁺ doped source / drain region
• 403 second p ⁺ doped source / drain region
• 404 first trench structure
• 405 second trench structure
• 406 first p ⁺ -doped polysilicon core
• 407 second n ⁺ -doped polysilicon core
• 408 p ⁺ control gate
• 500 memory cell
• 501 n-doped large well area
• 502 p-doped small well area
• 600 memory cell
• 601 silicon nitride layer
• 700 memory cell
• 800 memory cell
• 900 first current paths
• 901 second current paths
• 902 first electrons
• 903 second electrons
• 1000 first current paths
• 1001 second current paths
• 1002 first holes
• 1003 second holes
• 1100 memory cell
• 1101 first memory field effect transistor
• 1102 second memory field effect transistor
• 1103 ONO layer sequence
• 1104 first silicon oxide layer
• 1105 silicon nitride layer
• 1106 second silicon oxide layer
• 1107 first charge storage area
• 1108 second charge storage area
• 1200 memory cell arrangement
• 1202 tracks
• 1203 Track via
• 1300 memory cell
• 1301 common source / drain region
• 1400 memory cell arrangement
• 1401 tracks

Claims (20)

1. Storage cell, comprising

   - a substrate (301), containing charge carriers of a first conduction type;

   - a first source-/drain region (302) in a first surface region of the substrate and a second source-/drain-region (303) in a second surface region of the substrate;

   - a channel region (304) in a surface region of the substrate between the first and the second source/drain region;

   - a charge storage region (312) above the channel region;

   - a control gate (313) above the charge storage region, which is electrically insulated from the charge storage region;

   - a trench structure (305, 306) formed in the substrate, comprising material (307, 309) providing charge carriers having charge carriers of a second conduction type and an insulating region (308) between the substrate and between at least a part of the material providing charge carriers, wherein the trench structure is at least partially provided with a shallow trench side wall insulation;

   - wherein the first conduction type is different from the second conduction type such that a diode junction (315, 316) is formed between the substrate and the charge carriers providing material of the trench structure;

   - wherein the storage cell is configured such that electrical charge carriers from the charge carrier providing material of the trench structure are insertable into the charge storage region by applying presettable electrical potentials to the storage cell.
2. Storage cell according to claim 1,
   wherein the trench structure extends deeper into the substrate than the first and the second source-/drain region.
3. Storage cell according to claim 2,
   wherein the trench structure extends into the substrate at least by a factor 3 deeper than the first and the second source-/drain region.
4. Storage cell according to one of the claims 1 to 3,
   wherein the trench structure extends in an essentially vertical direction relative to the surface structure of the substrate.
5. Storage cell according to one of the claims 1 to 4,
   wherein the trench structure is formed on a side of at least one of the source-/drain regions and outside the channel region.
6. Storage cell according to one of the claims 1 to 5,
   having two trench structures, one of which is arranged on a side of the first source-/drain region and outside the channel region und the other one of which is arranged on a side of the second source-/drain region and outside the channel region.
7. Storage cell according to one of the claims 1 to 6,
   wherein the trench structure comprises an electrically insulating coating region on at least a part of the sidewall of the trench and an electrically conductive core region filled into the trench such that electrical charge carriers from the trench structure are only allowed to leak from such regions into the substrate, in which the core region is free from a coating by the coating region, or in such regions, in which the coating region comprises a sufficient small thickness for enabling a tunnel current.
8. Storage cell according to one of the claims 1 to 7,
   wherein the charge storage region is a floating-gate.
9. Storage cell according to claim 8,
   wherein the floating-gate comprises polysilicon.
10. Storage cell according to claim 8 or 9,
    wherein a gate-insulating layer is arranged between the substrate and the floating-gate.
11. Storage cell according to one of the claims 1 to 7,
    wherein the charge storage region is an electrically insulating charge storage region.
12. Storage cell according to claim 11,
    wherein the electrically insulating charge storage region comprises or consists of

    - a silicon oxide - silicon nitride - silicon oxide layer sequence;

    - silicon nitride;

    - aluminium oxide;

    - yttrium oxide;

    - lanthanum oxide;

    - hafnium oxide;

    - zirconium oxide;

    - a silicon oxide - aluminium oxide - silicon oxide layer sequence;

    - a silicon oxide - yttrium oxide - silicon oxide layer sequence;

    - a silicon oxide - lanthanum oxide - silicon oxide layer sequence;

    - a silicon oxide - hafnium oxide - silicon oxide layer sequence;

    - a silicon oxide - zirconium oxide layer sequence; and/or

    - another layer sequence, which enables a permanent charge storage.
13. Storage cell according to one of the claims 1 to 12,
    wherein the substrate comprises a well region comprising the charge carriers of the first conduction type and a region comprising the charge carriers of the second conduction type,
    wherein the components of the storage cell are formed in the well region.
14. Storage cell according to one of the claims 1 to 13,
    comprising a plurality of spatially separated and electrically separately controllable control gates such that electrical charge carriers from the trench structure are insertable into a region adjacent to the at least one selected control gate by applying presettable electrical potentials to at least selected one of the control gates.
15. Storage cell according to one of the claims 1 to 14,
    wherein the charge carriers of the first conduction type and/or the charge carriers of the second conduction type are doping atoms.
16. Storage cell arrangement,
    comprising a plurality of storage cells integrated in the substrate according to one of the claims 1 to 15.
17. Storage cell arrangement according to claim 16,
    which is formed in such a manner that different storage cells are electrically decoupled from each other by the electrically insulating coating regions.
18. Method for manufacturing a storage cell,
    wherein

    - a first source-/drain region (302) is formed in a first surface region of a substrate, which contains charge carriers of a first conduction type, and a second source-/drain-region (303) is formed in a second surface region of the substrate;

    - a channel region (304) is formed in a surface region of the substrate between the first and the second source-/drain region;

    - a charge storage region (312) is formed above the channel region;

    - a control gate (313), which is electrically insulated from the charge storage region, is formed above the charge storage region;

    - a trench structure (305, 306) arranged in the substrate is formed, which comprises material (307, 309) providing charge carriers having charge carriers of a second conduction type and an insulating region (308) between the substrate and between at least a part of the material providing charge carriers,

    wherein the trench structure is at least partially provided with a shallow trench side wall insulation;

    - wherein the first conduction type is adjusted differently from the second conduction type such that a diode-junction (315, 316) is formed between the substrate and the charge carriers providing material of the trench structure;

    - wherein the storage cell is configured such that electrical charge carriers from the charge carrier providing material of the trench structure are insertable into the charge storage region by applying presettable electrical potentials to the storage cell.
19. Method according to claim 18,
    wherein the trench structure is formed by

    - forming at least one trench in the substrate;

    - forming an electrically insulating coating region on at least one part of the surface of the at least one trench;

    - forming an electrically conductive core region in the at least one trench.
20. Method according to claim 18,
    wherein the trench structure is formed by

    - forming at least one trench in the substrate;

    - filling the trench with electrically insulating material;

    - removing a part of the electrically insulating material from the trench, whereby the electrically insulating coating region is formed;

    - forming an electrically conductive core region in the at least one trench.

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