EP1576669A1 - Power integrated circuits - Google Patents

Power integrated circuits

Info

Publication number
EP1576669A1
EP1576669A1 EP03780365A EP03780365A EP1576669A1 EP 1576669 A1 EP1576669 A1 EP 1576669A1 EP 03780365 A EP03780365 A EP 03780365A EP 03780365 A EP03780365 A EP 03780365A EP 1576669 A1 EP1576669 A1 EP 1576669A1
Authority
EP
European Patent Office
Prior art keywords
trench
wafer
high voltage
insulating material
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP03780365A
Other languages
German (de)
French (fr)
Inventor
Philip Mawby
Peter Igic
Paul Holland
Thomas Starke
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Power Electronics Design Centre
Original Assignee
Power Electronics Design Centre
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from GB0228754A external-priority patent/GB0228754D0/en
Priority claimed from GB0228755A external-priority patent/GB0228755D0/en
Application filed by Power Electronics Design Centre filed Critical Power Electronics Design Centre
Publication of EP1576669A1 publication Critical patent/EP1576669A1/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors

Definitions

  • This invention relates to semiconductor devices and technology and, more precisely, to power integrated circuit technology.
  • PICs Power Integrated Circuits
  • LDMOSFET Lateral Doubled Diffused power MOSFET transistors or the lateral IGBT are typically used.
  • bipolar - CMOS-DMOS allow the integration of a single DMOS transistor with low- voltage control functionality.
  • the DMOS is a vertical device with a drain contact on the backside of the wafer. This technology is extensively used at higher voltages, but at lower voltages or where several devices are needed alternatives such as the JI- LDMOS solution are sought.
  • the vertical power devices have bottom contacts (drain - VDMOSFET, Anode - IGBT), these making integration of the more than one device impossible using existing isolation techniques.
  • Some designers use very deep sinkers to bring those contacts on the wafer top surface, the manufacture of those deep sinkers being a limiting factor.
  • an integrated circuit comprising a semiconductor wafer having a front or upper surface and an opposing rear or bottom surface, the circuit further comprising a first trench in the rear or bottom surface of the wafer which defines a membrane in or on which one or more low voltage circuits or components are provided, said first, trench being at least partially covered or filled with an insulating material, a second trench in the front or upper surface of the wafer, said second trench being in communication with said insulating material, and at least one high voltage circuit or device provided in or on said semiconductor wafer, said second trench being provided between said membrane and said high voltage circuit or device so as to isolate them from each other.
  • a method of fabricating an integrated circuit comprising the steps of providing a semiconductor wafer having a front or upper surface and an opposing rear or bottom surface, forming a first trench in said rear or bottom surface of said wafer which defines a membrane, providing one or more low voltage circuits or components in or on said membrane, at least partially covering or filling said first trench with an insulating material, and providing at least one high voltage circuit or device in or on said wafer, forming a second trench in said front or upper surface of said wafer between said membrane and said high voltage circuit or device such that said second trench is in communication with said first trench and isolates said one or more low voltage circuits or components and said high voltage circuit or device from each other.
  • a method of isolating a high voltage power device and a low voltage circuit provided on a semiconductor wafer from each other comprising the steps of forming a first trench in a rear or bottom surface of said wafer so as to define a membrane in or on which said low voltage circuit or component is provided, at least partially covering or filling said first trench with an insulating material, and forming a second trench in a front or upper surface of the wafer between said high voltage power device and said low voltage circuit or component such that said second trench is in communication with said first trench and said high voltage power device and said low voltage circuit or component are isolated from each other.
  • an integrated circuit comprising a semiconductor wafer having a front or upper surface and an opposing rear or bottom surface, the circuit further comprising a first trench in the rear or bottom surface of the wafer on either side of which is provided a respective first and second high voltage power devices, said first trench being at least partially covered or filled with an insulating material, a second trench in the front or upper surface of the wafer, said second trench being located between said first and second high voltage power devices and in communication with said insulating material, so as to dielectrically isolate said first and second high voltage power devices from each other.
  • a method of fabricating an integrated circuit comprising the steps of providing a semiconductor wafer having a front or upper surface and an opposing rear or bottom surface, forming a first trench in said rear or bottom surface of said wafer, providing respective first or second high voltage power devices on either side of said first trench, at least partially covering or filling said first trench with an insulating material, forming a second trench in said front or upper surface of said wafer between said first and second high voltage high voltage power devices such that said second trench is in communication with said first trench and isolates said first and second high voltage power devices from each other.
  • a method of isolating first and second high voltage power devices provided on a semiconductor wafer from each other comprising the steps of forming a first trench in a rear or bottom surface of said wafer, said first and second high voltage power devices being provided on either side of said first trench, at least partially covering or filling said first trench with an insulating material, and forming a second trench in a front or upper surface of the wafer between said first and second high voltage power devices such that said second trench is in communication with said first trench and said first and second high voltage power devices are isolated from each other.
  • the method of isolation enabling dielectric isolation of the high voltage power devices from the low voltage control and protection circuitry (typically comprised of CMOS or BiCMOS devices) and from adjacent devices (i.e. each other), and also enabling the multiple power devices and the low voltage control logic to be fabricated simultaneously to form a monolithic integrated circuit, and all of this at an acceptably low processing cost.
  • the low voltage control and protection circuitry typically comprised of CMOS or BiCMOS devices
  • adjacent devices i.e. each other
  • the first trench is relatively significantly deeper than the second trench, and is preferably substantially completely covered and/or filled with an insulating material. It will be appreciated that the first trench may be etched to form a membrane in the conventional MEMS processes.
  • the second trench is preferably also at least partially covered or filled with an insulating material.
  • the power devices would typically (but not necessarily exclusively) be vertical power transistors, such as vertical IGBT's, vertical trench IGBT's, VDMOSFET's, trench MOSFET's, and the like.
  • PICS Power Integrated Circuits
  • high voltage/power devices are fabricated on a common semiconductor substrate (usually silicon) used for low voltage logic circuits.
  • a very complex functionality of the power IC is combined with higher switching speed, higher reliability, and less weight and size.
  • pure bipolar technologies were used for power ICs implementation.
  • Lateral DMOSFETs are preferably used because of their fast switching characteristics and the possibility of controlling them by voltage rather than current.
  • Conventional LDMOSFETs are used for up to 100V applications.
  • the introduction of Reduced Surface Field devices (RESURF LDMOSFET) in the early eighties made these devices applicable for the higher voltage applications (up to 700V).
  • RESURF LDMOSFET Reduced Surface Field devices
  • JI Junction Isolation
  • IGBT devices For applications higher than 700V, IGBT devices have to be integrated with the low voltage circuitry. Full integration of the lateral IGBT devices is a much more complex task since a high level of the minority carriers injected into the substrate will lead to interference with a low voltage (logic) circuits for junction isolated devices.
  • SOI silicon oxide
  • SOI-SDVIOX SOI- Wafer Bonding
  • SOI-Unibond can be employed to adequately protect low voltage devices from carrier injection. Consequently, sol devices have very low interference between adjacent devices, high speed and low area consumption, but they are more expensive, and they involve self-heating problems (thermal conductivity of the silicon-dioxide is about 100 times larger than silicon).
  • an integrated circuit comprising a semiconductor wafer comprising upper and lower layers of semiconductor material bonded together with a layer of insulating material therebetween, said wafer having a front or upper surface and an opposing rear or bottom surface, the circuit further comprising a trench in the rear or bottom surface of the wafer which trench extends into the lower layer of semiconductor material but does not extend beyond said layer of insulating material, said trench being at least partially covered or filled with an insulating material, said lower layer of semiconductor material being for receiving one or more high voltage power devices adjacent said trench and said upper layer of semiconductor material being for receiving one or more low voltage circuits or components, said layer of insulating material providing electrical insulation between said upper and lower layers.
  • a method of fabricating an integrated circuit comprising the steps of providing a semiconductor wafer comprising upper and lower layers of semiconductor material bonded together with a layer of insulating material therebetween, said wafer having a front or upper surface and an opposing rear or bottom surface, the method further comprising the steps of forming a trench in the rear or bottom surface of the wafer which extends into the lower layer of semiconductor material but does not extend beyond said layer of insulating material, at least partially covering or filling said trench with an insulating material, providing one or more high voltage power devices in or on said lower layer of semiconductor material adj acent said trench and providing one or more low voltage circuits or components in or on said upper layer of semiconductor material, said layer of insulating material providing electrical insulation between said upper and lower layers.
  • a method of isolating from each other a high voltage power device and a low voltage circuit provided on a semiconductor wafer comprising upper and lower layers of semiconductor material bonded together with a layer of insulating material there between, wherein at least one high voltage power device is provided in or on said lower layer of semiconductor material and at least one low voltage circuit or component is provided in or on said upper layer of semiconductor material, the method comprising the steps of forming a trench in a rear or bottom surface of said wafer which extends into the lower layer of semiconductor material but does not extend beyond said layer of insulating material, and at least partially covering or filling said first trench with an insulating material.
  • the third aspect of the present invention it is possible to integrate one or more vertical power devices (and, more particularly, high voltage power transistors and the like) into the same integrated circuit, with the method of isolation enabling dielectric isolation of the high voltage power devices from the low voltage control and protection circuitry (typically comprised of CMOS or BiCMOS devices) and from adjacent devices (i.e. each other), and also enabling the multiple power devices and the low voltage control logic to be fabricated simultaneously to form a monolithic integrated circuit, and all of this at an acceptably low processing cost.
  • the low voltage control and protection circuitry typically comprised of CMOS or BiCMOS devices
  • adjacent devices i.e. each other
  • the power devices would typically (but not necessarily exclusively) be vertical power transistors, such as vertical IGBT's, vertical trench IGBT's, VDMOSFET's, trench MOSFET's, and the like. It is preferred that the trench extends up to but not beyond the layer of insulating material and is substantially completely covered and/or filled with an insulating material, such that high voltage power devices provided in the lower layer of semiconductor material, on either side of the trench, are completely isolated from each other by the trench and from the low voltage circuitry provided in the upper layer of semiconductor material by the layer of insulating material.
  • the trench may be etched by, for example, wet chemical etching, reactive ion etching (RIE), or the like, and preferably tapers inwardly from the bottom surface of the wafer up.
  • RIE reactive ion etching
  • the layer of insulation material provides a natural etch stop layer.
  • the upper layer of semiconductor material may be etched to form one or more semiconductor islands, in or on which the low voltage circuitry may be provided (for example, CMOS or BiCMOS circuitry is preferred).
  • Figure 1 is a schematic perspective view of a semiconductor wafer
  • Figure 2 is a schematic perspective view of the semiconductor wafer of Figure 1 after the first trench has been formed in the rear or bottom surface thereof;
  • Figure 3 is a schematic perspective view of the semiconductor wafer of Figure 2 after the first trench has been covered with an insulating material;
  • Figure 4 is a schematic perspective view of the semiconductor wafer of Figure 3 after the first trench has been filled with an insulating material
  • Figure 5 is a partial schematic cross-sectional view of the semiconductor wafer of Figure 4 after a second trench has been formed in the front or upper surface thereof;
  • Figure 6 is a schematic perspective view of the semiconductor wafer of Figure 5 after the second trench has been filled with an insulating material
  • Figure 7 is a schematic perspective view of an integrated circuit according to an exemplary embodiment of the present invention.
  • Figure 8 is a partial schematic cross-sectional view of an integrated circuit according to a first specific exemplary embodiment of the present invention.
  • Figure 9 is a partial schematic cross-sectional view of an integrated circuit according to a second exemplary embodiment of the present invention.
  • Figure 10 is a partial schematic cross-sectional view of an integrated circuit according to a third exemplary embodiment of the present invention.
  • Figure 11 is a partial schematic cross-sectional view of an integrated circuit according to a fourth exemplary embodiment of the present invention.
  • Figure 12 is a schematic perspective view of a semiconductor (SOI) wafer
  • Figure 13 is a schematic perspective view of the semiconductor wafer of Figure 12 after two trenches have been formed in the rear or bottom surface thereof;
  • Figure 14 is a schematic perspective view of the semiconductor wafer of Figure 13 after the trenches have been covered with an insulating material;
  • Figure 15 is a schematic perspective view of the semiconductor wafer of Figure 14 after the trenches have been filled with another material;
  • Figure 16 is a schematic perspective view of the semiconductor wafer of Figure 15 after the upper layer of semiconductor material has been etched;
  • Figure 17 is a schematic cross-sectional view of an integrated circuit according to a specific exemplary embodiment of the present invention.
  • Figure 18 is a schematic cross-sectional view of an integrated circuit according to another exemplary embodiment of the present invention.
  • Figure 19 is a schematic cross-sectional view of an integrated circuit according to yet another exemplary embodiment of the present invention.
  • Figure 20 is a schematic cross-sectional view of an integrated circuit according to yet another exemplary embodiment of the present invention.
  • Figure 21 is a schematic plan view of a semiconductor chip according to an exemplary embodiment of the invention.
  • the starting material for an integrated circuit according to the invention is a semiconductor wafer 1.
  • a silicon membrane 2 is formed in the wafer 1 by etching, and low voltage logic circuitry can be provided, either partially or completely in the membrane 2, whereas the power device area 10 remains intact and is reserved for a vertical power device.
  • the trench formed to provide the membrane 2 is covered with an insulating material 3 and then filled with another material 4, such as another insulating material, glass or metal.
  • a second trench 12 is etched in the upper surface of the semiconductor wafer- 1 until it reaches the layer 3 of insulating material covering the first trench.
  • the second trench 12 is then filled with an insulating material, such that the low voltage area (provided by the membrane 2) is completely isolated from the power device area (in which a vertical power device is provided).
  • This process can, of course, be extended to three or more vertical power devices, as required. It will be appreciated that the devices 10 are completely isolated from each other as well as the low voltage circuitry.
  • Figure 8 of the drawings illustrates an integrated circuit according to a first specific exemplary embodiment of the present invention, in which a vertical IGBT 10 is integrated with the low voltage CMOS circuitry 20.
  • Figure 9 illustrates an integrated circuit according to a second specific exemplary embodiment of the present invention, in which a vertical trench IGBT 10 is integrated with the low voltage CMOS circuitry 20.
  • Figure 10 illustrates an integrated circuit according to a third specific exemplary embodiment of the present invention, in which a VDMOSFET 10 is integrated with the low voltage CMOS circuitry 20.
  • Figure 11 illustrates an integrated circuit according to a fourth specific exemplary embodiment of the present invention, in which a vertical trench MOSFET 10 is integrated with the low voltage CMOS circuitry 20.
  • the starting material for an integrated circuit is a semiconductor (SOI) wafer 1, comprising a first, lower layer 100 of semiconductor material (typically silicon), a second layer 102 of insulating material (typically silicon oxide) and a third, upper layer of semiconductor material (again, typically silicon).
  • SOI semiconductor
  • Trenches 2 are formed by, for example, wet chemical etching, or reactive ion etching in the lower layer 100 of semiconductor material up to the insulating layer 102, which may be used as a natural etch stop layer.
  • the trenches 2 are covered with an insulating material 3 and then filled with another material 4, such as another insulating material, glass or metal.
  • the upper layer 104 of semiconductor material is etched to form semiconductor islands 5, inside which low voltage (for example BiCMOS) circuitry can be completely provided.
  • low voltage for example BiCMOS
  • FIG. 17 of the drawings illustrates a structure in which two vertical IGBT's 10 are monolithically integrated with CMOS low voltage devices 20. It will be appreciated that the vertical power devices are completely isolated from each other and from the low voltage circuits.
  • Figure 18 of the drawings illustrates a structure in which two trench IGBT's 10 are monolithically integrated with CMOS low voltage devices 20. It will be appreciated once again that the vertical power devices are completely isolated from each other and from the low voltage circuits.
  • Figure 19 of the drawings illustrates a structure in which two vertical DMOSFET's 10 are monolithically integrated with CMOS low voltage devices 20. Once again, it will be appreciated that the vertical power devices are completely isolated from each other and from the low voltage circuits.
  • Figure 20 of the drawings illustrates a structure in which two vertical trench MOSFET's 10 are monolithically integrated with CMOS low voltage devices 20. It will once again be appreciated that the vertical power devices are completely isolated from each other and from the low voltage circuits.
  • Figure 21 is a schematic plan view of a semiconductor chip according to an exemplary embodiment of the first, second or third aspects of the present invention.
  • the two top trenches 6 and 7 have been designed to create five semiconductor regions 1, 2, 3, 4 and 5 (although it will be appreciated by a person skilled in the art that any other combination can be assumed).
  • a vertical device Inside each of the semiconductor regions 1 -5, a vertical device, one or more lateral devices, or CMOS circuitry can be placed. Isolation amongst the regions 1, 2, 3, 4 and 5 is achieved in combination by the present invention between the top trenches 6 and 7, the cut lines (kerfs) 8, 9, 10, and 11 , and the bottom (back) trenches (not shown in the figure).

Abstract

A monolithic integrated circuit comprising at least one relatively deep trench (14) etched into the rear or lower surface of a semiconductor wafer (1) to create a membrane in or on which low voltage logic circuitry for control and protection may be provided. At least one power device area (10) is also provided adjacent to the trench (14). The or each trench (14) is covered with an insulating material (3) and then filled with another material (4). A second, relatively shallow trench (12) is provided on the front or upper surface of the semiconductor wafer (1), in communication with the layer of insulating material (3) and located between adjacent devices or a power device (10) and the low voltage circuitry (2). A monolithic integrated circuit comprising a semiconductor (SOI) wafer is also disclosed.

Description

Power Integrated Circuits
This invention relates to semiconductor devices and technology and, more precisely, to power integrated circuit technology.
In recent years, Power Integrated Circuits (PICs) have gained huge interest in system integrations. PICs consist of high- voltage power devices and low- voltage control circuitry integrated on to the same semiconductor substrate (usually silicon). Lateral devices have generally been used for this type of application as they are easily integrated into existing processes and they have all their terminals available at the surface. The Lateral Doubled Diffused power MOSFET (LDMOSFET) transistors or the lateral IGBT are typically used.
Conventional extended drain LDMOSFETs are used for applications requiring voltages up to around 100V. However, the introduction of the Reduced Surface Field devices (RESURF LDMOSFET) in the early eighties allowed voltages to be significantly increased up to 700V). Such devices are majority carrier devices, which means all the current is carried by one carrier type and therefore switch very quickly. For lower on-state resistances it is possible to replace the LDMOS transistor with a lateral IGBT (LIGBT), which will have a lower on-state resistance, but as it is a bipolar device will have a much slower switching speed. Junction Isolation (JI) is usually used to separate such devices from each other and from the low- voltage circuitry.
Other technologies such as bipolar - CMOS-DMOS allow the integration of a single DMOS transistor with low- voltage control functionality. Here the DMOS is a vertical device with a drain contact on the backside of the wafer. This technology is extensively used at higher voltages, but at lower voltages or where several devices are needed alternatives such as the JI- LDMOS solution are sought.
Junction isolation is not ideal, since under certain transient conditions high injection conditions may well occur. Under such conditions, high levels of minority carriers will be injected into the substrate and will lead to interference with the low- voltage circuitry. To tackle this problem Silicon on insulator (SOI) technologies have been developed to provide dielectric isolation.
Despite the big improvement made in lateral power devices, their performances (current and voltage handling capabilities) are still far behind those of the vertical power devices. The vertical power devices have bottom contacts (drain - VDMOSFET, Anode - IGBT), these making integration of the more than one device impossible using existing isolation techniques. Some designers use very deep sinkers to bring those contacts on the wafer top surface, the manufacture of those deep sinkers being a limiting factor.
We have now devised an arrangement which addresses the issues referred to above, and overcomes some of the problems raised thereby.
Thus, in accordance with a first aspect of the present invention there is provided an integrated circuit comprising a semiconductor wafer having a front or upper surface and an opposing rear or bottom surface, the circuit further comprising a first trench in the rear or bottom surface of the wafer which defines a membrane in or on which one or more low voltage circuits or components are provided, said first, trench being at least partially covered or filled with an insulating material, a second trench in the front or upper surface of the wafer, said second trench being in communication with said insulating material, and at least one high voltage circuit or device provided in or on said semiconductor wafer, said second trench being provided between said membrane and said high voltage circuit or device so as to isolate them from each other.
Also in accordance with the first aspect of the present invention, there is provided a method of fabricating an integrated circuit comprising the steps of providing a semiconductor wafer having a front or upper surface and an opposing rear or bottom surface, forming a first trench in said rear or bottom surface of said wafer which defines a membrane, providing one or more low voltage circuits or components in or on said membrane, at least partially covering or filling said first trench with an insulating material, and providing at least one high voltage circuit or device in or on said wafer, forming a second trench in said front or upper surface of said wafer between said membrane and said high voltage circuit or device such that said second trench is in communication with said first trench and isolates said one or more low voltage circuits or components and said high voltage circuit or device from each other.
Still further in accordance with the first aspect of the present invention there is provided a method of isolating a high voltage power device and a low voltage circuit provided on a semiconductor wafer from each other, the method comprising the steps of forming a first trench in a rear or bottom surface of said wafer so as to define a membrane in or on which said low voltage circuit or component is provided, at least partially covering or filling said first trench with an insulating material, and forming a second trench in a front or upper surface of the wafer between said high voltage power device and said low voltage circuit or component such that said second trench is in communication with said first trench and said high voltage power device and said low voltage circuit or component are isolated from each other.
In accordance with a second aspect of the present invention, there is provided an integrated circuit comprising a semiconductor wafer having a front or upper surface and an opposing rear or bottom surface, the circuit further comprising a first trench in the rear or bottom surface of the wafer on either side of which is provided a respective first and second high voltage power devices, said first trench being at least partially covered or filled with an insulating material, a second trench in the front or upper surface of the wafer, said second trench being located between said first and second high voltage power devices and in communication with said insulating material, so as to dielectrically isolate said first and second high voltage power devices from each other.
Also in accordance with the second aspect of the present invention, there is provided a method of fabricating an integrated circuit comprising the steps of providing a semiconductor wafer having a front or upper surface and an opposing rear or bottom surface, forming a first trench in said rear or bottom surface of said wafer, providing respective first or second high voltage power devices on either side of said first trench, at least partially covering or filling said first trench with an insulating material, forming a second trench in said front or upper surface of said wafer between said first and second high voltage high voltage power devices such that said second trench is in communication with said first trench and isolates said first and second high voltage power devices from each other. Still further in accordance with the second aspect of the present invention, there is provided a method of isolating first and second high voltage power devices provided on a semiconductor wafer from each other, the method comprising the steps of forming a first trench in a rear or bottom surface of said wafer, said first and second high voltage power devices being provided on either side of said first trench, at least partially covering or filling said first trench with an insulating material, and forming a second trench in a front or upper surface of the wafer between said first and second high voltage power devices such that said second trench is in communication with said first trench and said first and second high voltage power devices are isolated from each other.
Thus, in accordance with the first and second aspects of the present invention, it is possible to integrate one or more vertical power devices (and, more particularly, high voltage power transistors and the like) into the same integrated circuit, with the method of isolation enabling dielectric isolation of the high voltage power devices from the low voltage control and protection circuitry (typically comprised of CMOS or BiCMOS devices) and from adjacent devices (i.e. each other), and also enabling the multiple power devices and the low voltage control logic to be fabricated simultaneously to form a monolithic integrated circuit, and all of this at an acceptably low processing cost.
hi a preferred embodiment, the first trench is relatively significantly deeper than the second trench, and is preferably substantially completely covered and/or filled with an insulating material. It will be appreciated that the first trench may be etched to form a membrane in the conventional MEMS processes. The second trench is preferably also at least partially covered or filled with an insulating material. The power devices would typically (but not necessarily exclusively) be vertical power transistors, such as vertical IGBT's, vertical trench IGBT's, VDMOSFET's, trench MOSFET's, and the like.
Within the last decade, Power Integrated Circuits (PICS) have gained huge interest in system intregrations. In the PICs, high voltage/power devices are fabricated on a common semiconductor substrate (usually silicon) used for low voltage logic circuits. A very complex functionality of the power IC is combined with higher switching speed, higher reliability, and less weight and size. At the beginning, pure bipolar technologies were used for power ICs implementation. These days, Lateral DMOSFETs are preferably used because of their fast switching characteristics and the possibility of controlling them by voltage rather than current. Conventional LDMOSFETs are used for up to 100V applications. The introduction of Reduced Surface Field devices (RESURF LDMOSFET) in the early eighties made these devices applicable for the higher voltage applications (up to 700V). These are majority carrier devices and Junction Isolation (JI) can be used to separate them from a low voltage circuitry. The junction isolation technique is based on reverse biased p-n junctions, and it is a low self- heating and relatively cheap technique. On the negative side, JI involves parasitic currents causing interference thus leading to a low speed and high leakage current.
For applications higher than 700V, IGBT devices have to be integrated with the low voltage circuitry. Full integration of the lateral IGBT devices is a much more complex task since a high level of the minority carriers injected into the substrate will lead to interference with a low voltage (logic) circuits for junction isolated devices. Alternatively SOI (silicon oxide) technologies, such as SOI-SDVIOX, SOI- Wafer Bonding or SOI-Unibond can be employed to adequately protect low voltage devices from carrier injection. Consequently, sol devices have very low interference between adjacent devices, high speed and low area consumption, but they are more expensive, and they involve self-heating problems (thermal conductivity of the silicon-dioxide is about 100 times larger than silicon).
In spite of big improvements being made in the last decade regarding lateral power devices, their performances (current and voltage handling capabilities) are still far behind those of the vertical power devices. The vertical power devices have bottom contacts to the back of the wafer (drain - VDMOSFET, Anode - IGBT), these making integration of more than one device impossible using existing isolation techniques. Some designers use very deep sinkers to bring these contacts on the wafer top surface, manufacturing of deep sinkers being a limiting factor. Some effort has been made to achieve Smart Power Integration (one power device with gate control logic) of the vertical power device into SOI wafer, but there is no present isolation technique which allows monolithic integration of more than one vertical power device with low voltage circuitry in the SOI wafer.
We have now devised an arrangement which addresses the issues referred to above, and overcomes some of the problems raised thereby. Thus, in accordance with a third aspect of the present invention there is provided an integrated circuit comprising a semiconductor wafer comprising upper and lower layers of semiconductor material bonded together with a layer of insulating material therebetween, said wafer having a front or upper surface and an opposing rear or bottom surface, the circuit further comprising a trench in the rear or bottom surface of the wafer which trench extends into the lower layer of semiconductor material but does not extend beyond said layer of insulating material, said trench being at least partially covered or filled with an insulating material, said lower layer of semiconductor material being for receiving one or more high voltage power devices adjacent said trench and said upper layer of semiconductor material being for receiving one or more low voltage circuits or components, said layer of insulating material providing electrical insulation between said upper and lower layers.
Also in accordance with the third aspect of the present invention, there is provided a method of fabricating an integrated circuit comprising the steps of providing a semiconductor wafer comprising upper and lower layers of semiconductor material bonded together with a layer of insulating material therebetween, said wafer having a front or upper surface and an opposing rear or bottom surface, the method further comprising the steps of forming a trench in the rear or bottom surface of the wafer which extends into the lower layer of semiconductor material but does not extend beyond said layer of insulating material, at least partially covering or filling said trench with an insulating material, providing one or more high voltage power devices in or on said lower layer of semiconductor material adj acent said trench and providing one or more low voltage circuits or components in or on said upper layer of semiconductor material, said layer of insulating material providing electrical insulation between said upper and lower layers.
Still further in accordance with the third aspect of the present invention there is provided a method of isolating from each other a high voltage power device and a low voltage circuit provided on a semiconductor wafer comprising upper and lower layers of semiconductor material bonded together with a layer of insulating material there between, wherein at least one high voltage power device is provided in or on said lower layer of semiconductor material and at least one low voltage circuit or component is provided in or on said upper layer of semiconductor material, the method comprising the steps of forming a trench in a rear or bottom surface of said wafer which extends into the lower layer of semiconductor material but does not extend beyond said layer of insulating material, and at least partially covering or filling said first trench with an insulating material.
Thus, in accordance with the third aspect of the present invention, it is possible to integrate one or more vertical power devices (and, more particularly, high voltage power transistors and the like) into the same integrated circuit, with the method of isolation enabling dielectric isolation of the high voltage power devices from the low voltage control and protection circuitry (typically comprised of CMOS or BiCMOS devices) and from adjacent devices (i.e. each other), and also enabling the multiple power devices and the low voltage control logic to be fabricated simultaneously to form a monolithic integrated circuit, and all of this at an acceptably low processing cost.
The power devices would typically (but not necessarily exclusively) be vertical power transistors, such as vertical IGBT's, vertical trench IGBT's, VDMOSFET's, trench MOSFET's, and the like. It is preferred that the trench extends up to but not beyond the layer of insulating material and is substantially completely covered and/or filled with an insulating material, such that high voltage power devices provided in the lower layer of semiconductor material, on either side of the trench, are completely isolated from each other by the trench and from the low voltage circuitry provided in the upper layer of semiconductor material by the layer of insulating material.
The trench may be etched by, for example, wet chemical etching, reactive ion etching (RIE), or the like, and preferably tapers inwardly from the bottom surface of the wafer up. The layer of insulation material provides a natural etch stop layer.
The upper layer of semiconductor material may be etched to form one or more semiconductor islands, in or on which the low voltage circuitry may be provided (for example, CMOS or BiCMOS circuitry is preferred).
Embodiments of the present invention will now be described by way of examples only with reference to the accompanying drawings, in which:
Figure 1 is a schematic perspective view of a semiconductor wafer; Figure 2 is a schematic perspective view of the semiconductor wafer of Figure 1 after the first trench has been formed in the rear or bottom surface thereof;
Figure 3 is a schematic perspective view of the semiconductor wafer of Figure 2 after the first trench has been covered with an insulating material;
Figure 4 is a schematic perspective view of the semiconductor wafer of Figure 3 after the first trench has been filled with an insulating material;
Figure 5 is a partial schematic cross-sectional view of the semiconductor wafer of Figure 4 after a second trench has been formed in the front or upper surface thereof;
Figure 6 is a schematic perspective view of the semiconductor wafer of Figure 5 after the second trench has been filled with an insulating material;
Figure 7 is a schematic perspective view of an integrated circuit according to an exemplary embodiment of the present invention;
Figure 8 is a partial schematic cross-sectional view of an integrated circuit according to a first specific exemplary embodiment of the present invention;
Figure 9 is a partial schematic cross-sectional view of an integrated circuit according to a second exemplary embodiment of the present invention;
Figure 10 is a partial schematic cross-sectional view of an integrated circuit according to a third exemplary embodiment of the present invention;
Figure 11 is a partial schematic cross-sectional view of an integrated circuit according to a fourth exemplary embodiment of the present invention;
Figure 12 is a schematic perspective view of a semiconductor (SOI) wafer; Figure 13 is a schematic perspective view of the semiconductor wafer of Figure 12 after two trenches have been formed in the rear or bottom surface thereof;
Figure 14 is a schematic perspective view of the semiconductor wafer of Figure 13 after the trenches have been covered with an insulating material;
Figure 15 is a schematic perspective view of the semiconductor wafer of Figure 14 after the trenches have been filled with another material;
Figure 16 is a schematic perspective view of the semiconductor wafer of Figure 15 after the upper layer of semiconductor material has been etched;
Figure 17 is a schematic cross-sectional view of an integrated circuit according to a specific exemplary embodiment of the present invention;
Figure 18 is a schematic cross-sectional view of an integrated circuit according to another exemplary embodiment of the present invention;
Figure 19 is a schematic cross-sectional view of an integrated circuit according to yet another exemplary embodiment of the present invention;
Figure 20 is a schematic cross-sectional view of an integrated circuit according to yet another exemplary embodiment of the present invention; and
Figure 21 is a schematic plan view of a semiconductor chip according to an exemplary embodiment of the invention.
Thus, referring first to Figures 1 and 2 of the drawings, the starting material for an integrated circuit according to the invention is a semiconductor wafer 1. A silicon membrane 2 is formed in the wafer 1 by etching, and low voltage logic circuitry can be provided, either partially or completely in the membrane 2, whereas the power device area 10 remains intact and is reserved for a vertical power device. As shown in Figures 3 and 4 of the drawings, the trench formed to provide the membrane 2 is covered with an insulating material 3 and then filled with another material 4, such as another insulating material, glass or metal.
Referring now to Figures 5 and 6, a second trench 12 is etched in the upper surface of the semiconductor wafer- 1 until it reaches the layer 3 of insulating material covering the first trench. The second trench 12 is then filled with an insulating material, such that the low voltage area (provided by the membrane 2) is completely isolated from the power device area (in which a vertical power device is provided).
As shown in Figure 7 of the drawings, an integrated circuit according to one exemplary embodiment of the present invention comprises a semiconductor wafer 1 in which two sets of upper 12 and lower trenches 14 are etched (simultaneously) in the upper and lower surfaces respectively of the wafer, such that two power devices 10 can be integrated into the device. This process can, of course, be extended to three or more vertical power devices, as required. It will be appreciated that the devices 10 are completely isolated from each other as well as the low voltage circuitry.
Figure 8 of the drawings illustrates an integrated circuit according to a first specific exemplary embodiment of the present invention, in which a vertical IGBT 10 is integrated with the low voltage CMOS circuitry 20.
Figure 9 illustrates an integrated circuit according to a second specific exemplary embodiment of the present invention, in which a vertical trench IGBT 10 is integrated with the low voltage CMOS circuitry 20.
Figure 10 illustrates an integrated circuit according to a third specific exemplary embodiment of the present invention, in which a VDMOSFET 10 is integrated with the low voltage CMOS circuitry 20. Figure 11 illustrates an integrated circuit according to a fourth specific exemplary embodiment of the present invention, in which a vertical trench MOSFET 10 is integrated with the low voltage CMOS circuitry 20.
Referring first to Figures 12 and 13 of the drawings, the starting material for an integrated circuit according to an exemplary embodiment of the third aspect of the present invention is a semiconductor (SOI) wafer 1, comprising a first, lower layer 100 of semiconductor material (typically silicon), a second layer 102 of insulating material (typically silicon oxide) and a third, upper layer of semiconductor material (again, typically silicon). The three layers are bonded together as shown, and this type of wafer structure is well known in the art.
Trenches 2 are formed by, for example, wet chemical etching, or reactive ion etching in the lower layer 100 of semiconductor material up to the insulating layer 102, which may be used as a natural etch stop layer.
As shown in Figures 14 and 15 of the drawings, the trenches 2 are covered with an insulating material 3 and then filled with another material 4, such as another insulating material, glass or metal.
Referring now to Figure 16, the upper layer 104 of semiconductor material is etched to form semiconductor islands 5, inside which low voltage (for example BiCMOS) circuitry can be completely provided.
Figure 17 of the drawings illustrates a structure in which two vertical IGBT's 10 are monolithically integrated with CMOS low voltage devices 20. It will be appreciated that the vertical power devices are completely isolated from each other and from the low voltage circuits.
Figure 18 of the drawings illustrates a structure in which two trench IGBT's 10 are monolithically integrated with CMOS low voltage devices 20. It will be appreciated once again that the vertical power devices are completely isolated from each other and from the low voltage circuits. Figure 19 of the drawings illustrates a structure in which two vertical DMOSFET's 10 are monolithically integrated with CMOS low voltage devices 20. Once again, it will be appreciated that the vertical power devices are completely isolated from each other and from the low voltage circuits.
Figure 20 of the drawings illustrates a structure in which two vertical trench MOSFET's 10 are monolithically integrated with CMOS low voltage devices 20. It will once again be appreciated that the vertical power devices are completely isolated from each other and from the low voltage circuits.
Figure 21 is a schematic plan view of a semiconductor chip according to an exemplary embodiment of the first, second or third aspects of the present invention. In this particular case, the two top trenches 6 and 7 have been designed to create five semiconductor regions 1, 2, 3, 4 and 5 (although it will be appreciated by a person skilled in the art that any other combination can be assumed). Inside each of the semiconductor regions 1 -5, a vertical device, one or more lateral devices, or CMOS circuitry can be placed. Isolation amongst the regions 1, 2, 3, 4 and 5 is achieved in combination by the present invention between the top trenches 6 and 7, the cut lines (kerfs) 8, 9, 10, and 11 , and the bottom (back) trenches (not shown in the figure).
Embodiments of the present invention have been described above by way of examples only, and it will be appreciated that modifications and variations can be made to the described embodiments without departing from the scope of the present invention as defined by the appended claims.

Claims

Claims
1. An integrated circuit comprising a semiconductor wafer having a front or upper surface and an opposing rear or bottom surface, the circuit further comprising a first trench in the rear or bottom surface of the wafer which defines a membrane in or on which one or more low voltage circuits or components are provided, said first trench being at least partially covered or filled with an insulating material, a second trench in the front or upper surface of the wafer, said second trench being in communication with said insulating material, and at least one high voltage circuit or device provided in or on said semiconductor wafer, said second trench being provided between said membrane and said high voltage circuit or device so as to isolate them from each other.
2. A method of fabricating an integrated circuit comprising the steps of providing a semiconductor wafer having a front or upper surface and an opposing rear or bottom surface, forming a first trench in said rear or bottom surface of said wafer which defines a membrane, providing one or more low voltage circuits or components in or on said membrane, at least partially covering or filling said first trench with an insulating material, and providing at least one high voltage circuit or device in or on said wafer, forming a second trench in said front or upper surface of said wafer between said membrane and said high voltage circuit or device such that said second trench is in communication with said first trench and isolates said one or more low voltage circuits or components and said high voltage circuit or device from each other.
3. A method of isolating a high voltage power device and a low voltage circuit or component provided on a semiconductor wafer from each other, the method comprising the steps of forming a first trench in a rear or bottom surface of said wafer so as to define a membrane in or on which said low voltage circuit or component is provided, at least partially covering or filling said first trench with an insulating material, and forming a second trench in a front or upper surface of the wafer between said high voltage power device and said low voltage circuit or component such that said second trench is in communication with said first trench and said high voltage power device and said low voltage circuit or component are isolated from each other.
4. An integrated circuit according to claim 1, comprising two or more high voltage circuits or devices are isolated from each other and from said low voltage circuit or component by respective one or more second trenches provided in said front or upper surface of said wafer.
5. An integrated circuit comprising a semiconductor wafer having a front or upper surface and an opposing rear or bottom surface, the circuit further comprising a first trench in the rear or bottom surface of the wafer on either side of which is provided a respective first and second high voltage power devices, said first trench being at least partially covered or filled with an insulating material, a second trench in the front or upper surface of the wafer, said second trench being located between said first and second high voltage power devices and in communication with said insulating material, so as to dielectrically isolate said first and second high voltage power devices from each other.
6. An integrated circuit according to claim 1 , claim 4 or claim 5 , wherein the first trench is relatively significantly deeper than the second trench.
7. An integrated circuit according to any one of claims 1, or claims 4 to 6, wherein second trench is at least partially covered or filled with an insulating material.
8. An integrated circuit according to any one of claims 1 or claims 4 to 7, wherein the or each power device comprises a vertical power transistor, such as a vertical IGBT, a vertical trench IGBT, a VDMOSFET, a trench MOSFET, or the like.
9. An integrated circuit according to any one of claims 1 or claims 4 to 8, wherein said one or more low voltage circuits or components comprise one or more CMOS or BiCMOS devices.
10. An integrated circuit according to any one of claims 1 or claims 4 to 9, wherein said one or more low voltage circuits or devices comprise low voltage logic circuitry.
11. A method according to claim 2 or claim 3 , wherein two or more high voltage circuits or devices are provided in said semiconductor wafer, and including the step of forming a plurality of second trenches in said front or upper surface of said wafer so as to isolate the high voltage circuits or devices from each other and from said low voltage circuits or components.
12. A method of fabricating an integrated circuit comprising the steps of providing a semiconductor wafer having a front or upper surface and an opposing rear or bottom surface, forming a first trench in said rear or bottom surface of said wafer, providing respective first or second high voltage power devices on either side of said first trench, at least partially covering or filling said first trench with an insulating material, forming a second trench in said front or upper surface of said wafer between said first and second high voltage high voltage power devices such that said second trench is in communication with said first trench and isolates said first and second high voltage power devices from each other.
13. A method of isolating first and second high voltage power devices provided on a semiconductor wafer from each other, the method comprising the steps of forming a first trench in a rear or bottom surface of said wafer, said first and second high voltage power devices being provided on either side of said first trench, at least partially covering or filling said first trench with an insulating material, and forming a second trench in a front or upper surface of the wafer between said first and second high voltage power devices such that said second trench is in communication with said first trench and said first and second high voltage power devices are isolated from each other.
14. An integrated circuit comprising a semiconductor wafer comprising upper and lower layers of semiconductor material bonded together with a layer of insulating material therebetween, said wafer having a front or upper surface and an opposing rear or bottom surface, the circuit further comprising a trench in the rear or bottom surface of the wafer which extends into the lower layer of semiconductor material but does not extend beyond said layer of insulating material, said trench being at least partially covered or filled with an insulating material, said lower layer of semiconductor material being for receiving one or more high voltage power devices adjacent said trench and said upper layer of semiconductor material being for receiving one or more low voltage circuits or components, said layer of insulating material providing electrical insulation between said upper and lower layers.
15. A method of fabricating an integrated circuit comprising the steps of providing a semiconductor wafer comprising upper and lower layers of semiconductor material bonded together with a layer of insulating material therebetween, said wafer having
• a front or upper surface and an opposing rear or bottom surface, the method further comprising the steps of forming a trench in the rear or bottom surface of the wafer which extends into the lower layer of semiconductor material but does not extend beyond said layer of insulating material, at least partially covering or filling said trench with an insulating material, providing one or more high voltage power devices in or on said lower layer of semiconductor material adjacent said trench and providing one or more low voltage circuits or components in or on said upper layer of semiconductor material, said layer of insulating material providing electrical insulation between said upper and lower layers.
16. A method of isolating from each other a high voltage power device and a low voltage circuit provided on a semiconductor wafer comprising upper and lower layers of semiconductor material bonded together with a layer of insulating material therebetween, wherein at least one high voltage power device is provided in or on said lower layer of semiconductor material and at least one low voltage circuit or component is provided in or on said upper layer of semiconductor material, the method comprising the steps of forming a trench in a rear or bottom surface of said wafer which extends into the lower layer of semiconductor material but does not extend beyond said layer of insulating material, and at least partially covering or filling said first trench with an insulating material.
17. An integrated circuit according to claim 14, wherein the trench extends up to but not beyond the layer of insulating material.
• 18. An integrated circuit according to claim 14 or claim 17, wherein the trench is substantially completely covered and/or filled with an insulating material.
19. An integrated circuit according to any one of claims 14, 17 or 18, wherein respective high voltage power devices are provided in the lower layer of semiconductor material, on either side of the trench.
20. An integrated circuit according to any one of claims 14 or 17 to 19, wherein the trench tapers inwardly from the bottom surface of the wafer up.
21. An integrated circuit according to any one of claims 14 or 17 to 20, wherein the upper layer of semiconductor material is etched to form one or more semiconductor islands, in or on which the low voltage circuitry may be provided.
22. An integrated circuit according to any one of claims 14 or 17 to 21, wherein two or more trenches are provided in said lower layer of semiconductor material.
23. An integrated circuit substantially as herein described with reference to the accompanying drawings.
24. A method of fabricating an integrated circuit substantially as herein described with reference to the accompanying drawings.
5. A method of isolating from each other a high voltage power device and a low voltage circuit provided on a semiconductor wafer, the method being substantially as herein described with reference to the accompanying drawings.
EP03780365A 2002-12-10 2003-12-09 Power integrated circuits Withdrawn EP1576669A1 (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
GB0228755 2002-12-10
GB0228754 2002-12-10
GB0228754A GB0228754D0 (en) 2002-12-10 2002-12-10 Power integrated circuits
GB0228755A GB0228755D0 (en) 2002-12-10 2002-12-10 Power integrated circuits
PCT/GB2003/005367 WO2004053993A1 (en) 2002-12-10 2003-12-09 Power integrated circuits

Publications (1)

Publication Number Publication Date
EP1576669A1 true EP1576669A1 (en) 2005-09-21

Family

ID=32510404

Family Applications (1)

Application Number Title Priority Date Filing Date
EP03780365A Withdrawn EP1576669A1 (en) 2002-12-10 2003-12-09 Power integrated circuits

Country Status (3)

Country Link
EP (1) EP1576669A1 (en)
AU (1) AU2003288446A1 (en)
WO (1) WO2004053993A1 (en)

Families Citing this family (59)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1623495B1 (en) 2003-05-06 2009-10-07 Enecsys Limited Power supply circuits
US8067855B2 (en) 2003-05-06 2011-11-29 Enecsys Limited Power supply circuits
EP1617476A3 (en) * 2004-07-16 2007-12-26 Power Electronics Design Centre Vertical integration in power integrated circuits
US8077437B2 (en) 2004-11-08 2011-12-13 Enecsys Limited Integrated circuits and power supplies
DE102005002023B4 (en) * 2005-01-15 2007-08-16 Atmel Germany Gmbh Semiconductor structure with vertical JFET
DE102005046624B3 (en) * 2005-09-29 2007-03-22 Atmel Germany Gmbh Production of semiconductor arrangement with formation of conductive substrate, structural element region (SER) layer for insulating SER from substrate useful in semiconductor technology, e.g. in production of DMOS-field effect transistors
US11881814B2 (en) 2005-12-05 2024-01-23 Solaredge Technologies Ltd. Testing of a photovoltaic panel
US10693415B2 (en) 2007-12-05 2020-06-23 Solaredge Technologies Ltd. Testing of a photovoltaic panel
JP4087416B2 (en) * 2006-04-06 2008-05-21 シャープ株式会社 Power IC device and manufacturing method thereof
US11735910B2 (en) 2006-12-06 2023-08-22 Solaredge Technologies Ltd. Distributed power system using direct current power sources
US11309832B2 (en) 2006-12-06 2022-04-19 Solaredge Technologies Ltd. Distributed power harvesting systems using DC power sources
US8473250B2 (en) 2006-12-06 2013-06-25 Solaredge, Ltd. Monitoring of distributed power harvesting systems using DC power sources
US11296650B2 (en) 2006-12-06 2022-04-05 Solaredge Technologies Ltd. System and method for protection during inverter shutdown in distributed power installations
US11728768B2 (en) 2006-12-06 2023-08-15 Solaredge Technologies Ltd. Pairing of components in a direct current distributed power generation system
US9088178B2 (en) 2006-12-06 2015-07-21 Solaredge Technologies Ltd Distributed power harvesting systems using DC power sources
US9130401B2 (en) 2006-12-06 2015-09-08 Solaredge Technologies Ltd. Distributed power harvesting systems using DC power sources
US8319483B2 (en) 2007-08-06 2012-11-27 Solaredge Technologies Ltd. Digital average input current control in power converter
US8384243B2 (en) 2007-12-04 2013-02-26 Solaredge Technologies Ltd. Distributed power harvesting systems using DC power sources
US11855231B2 (en) 2006-12-06 2023-12-26 Solaredge Technologies Ltd. Distributed power harvesting systems using DC power sources
US11569659B2 (en) 2006-12-06 2023-01-31 Solaredge Technologies Ltd. Distributed power harvesting systems using DC power sources
US11687112B2 (en) 2006-12-06 2023-06-27 Solaredge Technologies Ltd. Distributed power harvesting systems using DC power sources
US8618692B2 (en) 2007-12-04 2013-12-31 Solaredge Technologies Ltd. Distributed power system using direct current power sources
US11888387B2 (en) 2006-12-06 2024-01-30 Solaredge Technologies Ltd. Safety mechanisms, wake up and shutdown methods in distributed power installations
US8963369B2 (en) 2007-12-04 2015-02-24 Solaredge Technologies Ltd. Distributed power harvesting systems using DC power sources
US8947194B2 (en) 2009-05-26 2015-02-03 Solaredge Technologies Ltd. Theft detection and prevention in a power generation system
US8816535B2 (en) 2007-10-10 2014-08-26 Solaredge Technologies, Ltd. System and method for protection during inverter shutdown in distributed power installations
US8319471B2 (en) 2006-12-06 2012-11-27 Solaredge, Ltd. Battery power delivery module
US9112379B2 (en) 2006-12-06 2015-08-18 Solaredge Technologies Ltd. Pairing of components in a direct current distributed power generation system
US8013472B2 (en) 2006-12-06 2011-09-06 Solaredge, Ltd. Method for distributed power harvesting using DC power sources
WO2008152911A1 (en) * 2007-06-08 2008-12-18 Panasonic Electric Works Co., Ltd. Semiconductor device, and its manufacturing method
US8278731B2 (en) 2007-11-20 2012-10-02 Denso Corporation Semiconductor device having SOI substrate and method for manufacturing the same
WO2009072076A2 (en) 2007-12-05 2009-06-11 Solaredge Technologies Ltd. Current sensing on a mosfet
US9291696B2 (en) 2007-12-05 2016-03-22 Solaredge Technologies Ltd. Photovoltaic system power tracking method
US11264947B2 (en) 2007-12-05 2022-03-01 Solaredge Technologies Ltd. Testing of a photovoltaic panel
CN101933209B (en) 2007-12-05 2015-10-21 太阳能安吉有限公司 Release mechanism in distributed electrical power apparatus, to wake up and method for closing
WO2009073867A1 (en) 2007-12-05 2009-06-11 Solaredge, Ltd. Parallel connected inverters
EP2269290B1 (en) 2008-03-24 2018-12-19 Solaredge Technologies Ltd. Switch mode converter including active clamp for achieving zero voltage switching
EP2294669B8 (en) 2008-05-05 2016-12-07 Solaredge Technologies Ltd. Direct current power combiner
US10673222B2 (en) 2010-11-09 2020-06-02 Solaredge Technologies Ltd. Arc detection and prevention in a power generation system
US10673229B2 (en) 2010-11-09 2020-06-02 Solaredge Technologies Ltd. Arc detection and prevention in a power generation system
US10230310B2 (en) 2016-04-05 2019-03-12 Solaredge Technologies Ltd Safety switch for photovoltaic systems
GB2485527B (en) 2010-11-09 2012-12-19 Solaredge Technologies Ltd Arc detection and prevention in a power generation system
GB2486408A (en) 2010-12-09 2012-06-20 Solaredge Technologies Ltd Disconnection of a string carrying direct current
GB2483317B (en) 2011-01-12 2012-08-22 Solaredge Technologies Ltd Serially connected inverters
US8570005B2 (en) 2011-09-12 2013-10-29 Solaredge Technologies Ltd. Direct current link circuit
GB2498365A (en) 2012-01-11 2013-07-17 Solaredge Technologies Ltd Photovoltaic module
US9853565B2 (en) 2012-01-30 2017-12-26 Solaredge Technologies Ltd. Maximized power in a photovoltaic distributed power system
GB2498790A (en) 2012-01-30 2013-07-31 Solaredge Technologies Ltd Maximising power in a photovoltaic distributed power system
GB2498791A (en) 2012-01-30 2013-07-31 Solaredge Technologies Ltd Photovoltaic panel circuitry
GB2499991A (en) 2012-03-05 2013-09-11 Solaredge Technologies Ltd DC link circuit for photovoltaic array
US10115841B2 (en) 2012-06-04 2018-10-30 Solaredge Technologies Ltd. Integrated photovoltaic panel circuitry
US9941813B2 (en) 2013-03-14 2018-04-10 Solaredge Technologies Ltd. High frequency multi-level inverter
US9548619B2 (en) 2013-03-14 2017-01-17 Solaredge Technologies Ltd. Method and apparatus for storing and depleting energy
EP3506370B1 (en) 2013-03-15 2023-12-20 Solaredge Technologies Ltd. Bypass mechanism
EP2887387A1 (en) * 2013-12-20 2015-06-24 Nxp B.V. Semiconductor device and associated method
US9318974B2 (en) 2014-03-26 2016-04-19 Solaredge Technologies Ltd. Multi-level inverter with flying capacitor topology
US11177663B2 (en) 2016-04-05 2021-11-16 Solaredge Technologies Ltd. Chain of power devices
US11018623B2 (en) 2016-04-05 2021-05-25 Solaredge Technologies Ltd. Safety switch for photovoltaic systems
US11830778B2 (en) 2020-11-12 2023-11-28 International Business Machines Corporation Back-side wafer modification

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5138422A (en) * 1987-10-27 1992-08-11 Nippondenso Co., Ltd. Semiconductor device which includes multiple isolated semiconductor segments on one chip
JP2788269B2 (en) * 1988-02-08 1998-08-20 株式会社東芝 Semiconductor device and manufacturing method thereof
IL154945A0 (en) * 2000-09-21 2003-10-31 Cambridge Semiconductor Ltd Semiconductor device and method of forming a semiconductor device

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO2004053993A1 *

Also Published As

Publication number Publication date
AU2003288446A1 (en) 2004-06-30
WO2004053993A1 (en) 2004-06-24

Similar Documents

Publication Publication Date Title
WO2004053993A1 (en) Power integrated circuits
US10431598B2 (en) Vertical semiconductor device with thinned substrate
US10079230B2 (en) Double-sided vertical semiconductor device with thinned substrate
JP5392959B2 (en) Semiconductor device and method for forming a semiconductor device
KR100311589B1 (en) Semiconductor component for high voltage
CN104221147B (en) Semiconductor integrated circuit device
WO2006109265A1 (en) Semiconductor device and method for manufacture
US7772652B2 (en) Semiconductor component arrangement having a first and second region
US8115273B2 (en) Deep trench isolation structures in integrated semiconductor devices
EP3961722A1 (en) Apparatus for extension of operation voltage
US6525392B1 (en) Semiconductor power device with insulated circuit
EP1617476A2 (en) Vertical integration in power integrated circuits
KR100265049B1 (en) MOS field effect transistor and manufacturing method of S.O.I device
AU2006200447B2 (en) Semiconductor device and method of forming a semiconductor device
KR100268866B1 (en) Semiconductor device and method for fabricating the same
Rotter et al. High-voltage devices (> 600 V) produced with a low-voltage (< 150 V) smart-power IC-technology
KR960015944A (en) Transverse high speed bipolar transistor and method of manufacturing the same

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20050707

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LI LU MC NL PT RO SE SI SK TR

AX Request for extension of the european patent

Extension state: AL LT LV MK

DAX Request for extension of the european patent (deleted)
STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 20060303