EP1521189A2 - Méthodes de preuve formelle pour analyser des problèmes de charge de circuit dans des conditions d'opération - Google Patents
Méthodes de preuve formelle pour analyser des problèmes de charge de circuit dans des conditions d'opération Download PDFInfo
- Publication number
- EP1521189A2 EP1521189A2 EP04292204A EP04292204A EP1521189A2 EP 1521189 A2 EP1521189 A2 EP 1521189A2 EP 04292204 A EP04292204 A EP 04292204A EP 04292204 A EP04292204 A EP 04292204A EP 1521189 A2 EP1521189 A2 EP 1521189A2
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- EP
- European Patent Office
- Prior art keywords
- logic
- node
- driving
- circuit
- equations
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 238000000034 method Methods 0.000 title claims abstract description 24
- 238000004458 analytical method Methods 0.000 claims description 17
- 239000000284 extract Substances 0.000 claims description 3
- 230000001419 dependent effect Effects 0.000 claims 1
- 238000012067 mathematical method Methods 0.000 claims 1
- 238000013461 design Methods 0.000 description 7
- 230000000052 comparative effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000135 prohibitive effect Effects 0.000 description 2
- 238000004513 sizing Methods 0.000 description 2
- 244000309464 bull Species 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000008520 organization Effects 0.000 description 1
- 238000010200 validation analysis Methods 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3323—Design verification, e.g. functional simulation or model checking using formal methods, e.g. equivalence checking or property checking
Definitions
- This invention relates to the art of logic design and implementation and, more particularly, to a tool for determining if any driving node in a very complex logic circuit, such as a processor, has suitable power handling capacity to drive its collective loads under "real", rather than "worst-case” assumed, conditions.
- formal proof is used herein as a generic term for these types of programs.
- formal proof programs may still take a long time to analyze all combinations of the reduced logic, the time is not prohibitive for use during the development and analysis of a complex logic component.
- this absolute worst-case assumed solution may be much too pessimistic in that, in all "real" possible combinations for a given driving node, some of the loads may be through transistors which are not enabled such that the actual worst case loading might be less or even much less.
- This characteristic leads to warnings or error reports, from circuit analysis programs, which are in fact not "real” or possible during the actual operation of the logic circuit.
- the logic even of a single driving node may be too complicated to analyze easily by hand, and/or the number of warnings/errors reported may obscure the recognition of "real" errors; i.e., the important message may be buried in a report containing a large number of "false” errors.
- a process for determining the optimum load driving capacity for each driving node in a complex logic circuit First, the logic equations of the logic circuit are extracted from an electronic circuit description. Then, the fan-out of each driving node is analyzed to determine if the total number of pass transistor loads of the analyzed node is excessive compared to a predetermined driving capacity. For each flagged driving node, logic equations are added which represent the sum of the driving node's pass transistor loads, and further logic equations are added to compare the number of pass transistors turned on from one to the absolute maximum for the flagged driving node. Then, a formal proof program is used to analyze the logic circuit and determine which of the comparators have a true output. For each flagged node, the comparator for the largest number which has a possible true output is identified to determine the highest possible actual load for the flagged driving node; and, if necessary, the driving capacity of the node is adjusted to handle the determined highest possible actual load.
- an exemplary node includes a driver 1 and loads 3, 5, 7, 9 selectively imposed on driver 1 according to the input status of pass transistors 2, 4, 6, 8.
- the pass transistors are individually enabled by suitable signals applied to their respective gates 2G, 4G, 6G, 8G.
- FIG. 2 shows a second exemplary node in which the load 7 may be imposed on the driver 1 if either or both control transistors 6A, 6B are enabled.
- the driver nodes shown in FIGs. 1 and 2 are representative of circuits widely found in complex logic, and the transistors are typically input stages to certain types of logic elements such as latches, switches, multiplexers, etc. Often, an individual driver will selectively provide switching current to more than four loads as shown, but this is a sufficient number to explain the invention.
- a logic equation generation and analysis software tool is used to extract logic equations from a circuit description.
- the software tool "Circuit” (from Bull Worldwide Information Systems) will perform this function.
- the logic equations generated by Circuit and equivalent software tools will identify and configure driver nodes along with other logic and will provide a certain amount of analysis such as determining how many loads are driven by a given driving node.
- the "real" loading is not determinable by such tools, and therefore, the worst case is assumed with the resulting drawbacks discussed above.
- FIG. 3 is a process flow chart according to the prior art.
- the software tool extracts the logic equations for a given logic circuit from a circuit description.
- the software tool (or another suitable software tool) analyzes the fan-out of every driving node to determine the amount of loading driven by each node, some or all of which may be loading "through" pass transistors.
- the software tool marks each node which has potentially too many loads. That is, a standard driver capable of driving a predetermined number of loads may be assumed for all drivers or for each of a class of drivers. Thus, if a given driver node, such as the driver 1 of the nodes shown in FIGs.
- the drive handling capacity specification for the given node is adjusted higher such that, when the circuit is implemented in hardware, the worst case condition can be handled.
- step 20 use a software tool which extracts the logic equations for a given logic circuit from a circuit description, step 20. Then, also as in the prior art, analyze, at step 21, the fan-out of every driving node to determine the total number of pass transistor loads driven by each node. At step 22, also as in the prior art, flag each node which has potentially too many loads (for an assumed "standard” driver which has a predetermined load driving capacity which is less than "worst case").
- Step 23 begins a fundamental departure from the prior art. During step 23, for those nodes identified as having potentially too many loads, equations are added to the circuit's logic description to represent the sum of the loads through all transistors that are "turned on”.
- step 22 assume that the driver 1 of FIG. 1 is preliminarily established as capable of driving three unit loads simultaneously, but it was found in step 22 that there were potentially four loads on driving gate 1. Without this new methodology, the driving capacity of gate 1 would have to be enlarged to provide for a capacity of four.
- the process might determine that the highest load to which the driving node might be subjected is only two so it would be found not to be necessary to increase the driving strength of the driver 1 accordingly (in this example, to full "worst case”) and indeed the driving capacity could be reduced to a driver for gate 1 capable of driving only two units of loading.
- the average size of driving nodes in a component can be substantially reduced to achieve the objects set forth above.
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Logic Circuits (AREA)
- Tests Of Electronic Circuits (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US675851 | 2003-09-30 | ||
US10/675,851 US6983429B2 (en) | 2003-09-30 | 2003-09-30 | Formal proof methods for analyzing circuit loading problems under operating conditions |
Publications (3)
Publication Number | Publication Date |
---|---|
EP1521189A2 true EP1521189A2 (fr) | 2005-04-06 |
EP1521189A3 EP1521189A3 (fr) | 2007-02-14 |
EP1521189B1 EP1521189B1 (fr) | 2018-05-02 |
Family
ID=34314015
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP04292204.7A Active EP1521189B1 (fr) | 2003-09-30 | 2004-09-14 | Méthodes de preuve formelle pour analyser des problèmes de charge de circuit dans des conditions d'opération |
Country Status (2)
Country | Link |
---|---|
US (1) | US6983429B2 (fr) |
EP (1) | EP1521189B1 (fr) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8688630B2 (en) | 2008-10-24 | 2014-04-01 | Compuverde Ab | Distributed data storage |
US8769138B2 (en) | 2011-09-02 | 2014-07-01 | Compuverde Ab | Method for data retrieval from a distributed data storage system |
US8843710B2 (en) | 2011-09-02 | 2014-09-23 | Compuverde Ab | Method and device for maintaining data in a data storage system comprising a plurality of data storage nodes |
US8997124B2 (en) | 2011-09-02 | 2015-03-31 | Compuverde Ab | Method for updating data in a distributed data storage system |
US9021053B2 (en) | 2011-09-02 | 2015-04-28 | Compuverde Ab | Method and device for writing data to a data storage system comprising a plurality of data storage nodes |
US9305012B2 (en) | 2011-09-02 | 2016-04-05 | Compuverde Ab | Method for data maintenance |
US9503524B2 (en) | 2010-04-23 | 2016-11-22 | Compuverde Ab | Distributed data storage |
US9626378B2 (en) | 2011-09-02 | 2017-04-18 | Compuverde Ab | Method for handling requests in a storage system and a storage node for a storage system |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0867819A2 (fr) * | 1997-03-28 | 1998-09-30 | Nec Corporation | Méthode pour concevoir un dispositif de circuit intégré basée sur la capacité de charge maximale |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6886152B1 (en) * | 2002-08-09 | 2005-04-26 | Xilinx, Inc. | Delay optimization in signal routing |
-
2003
- 2003-09-30 US US10/675,851 patent/US6983429B2/en active Active
-
2004
- 2004-09-14 EP EP04292204.7A patent/EP1521189B1/fr active Active
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0867819A2 (fr) * | 1997-03-28 | 1998-09-30 | Nec Corporation | Méthode pour concevoir un dispositif de circuit intégré basée sur la capacité de charge maximale |
Cited By (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10650022B2 (en) | 2008-10-24 | 2020-05-12 | Compuverde Ab | Distributed data storage |
US11907256B2 (en) | 2008-10-24 | 2024-02-20 | Pure Storage, Inc. | Query-based selection of storage nodes |
US11468088B2 (en) | 2008-10-24 | 2022-10-11 | Pure Storage, Inc. | Selection of storage nodes for storage of data |
US9026559B2 (en) | 2008-10-24 | 2015-05-05 | Compuverde Ab | Priority replication |
US8688630B2 (en) | 2008-10-24 | 2014-04-01 | Compuverde Ab | Distributed data storage |
US9329955B2 (en) | 2008-10-24 | 2016-05-03 | Compuverde Ab | System and method for detecting problematic data storage nodes |
US9495432B2 (en) | 2008-10-24 | 2016-11-15 | Compuverde Ab | Distributed data storage |
US9503524B2 (en) | 2010-04-23 | 2016-11-22 | Compuverde Ab | Distributed data storage |
US9948716B2 (en) | 2010-04-23 | 2018-04-17 | Compuverde Ab | Distributed data storage |
US9021053B2 (en) | 2011-09-02 | 2015-04-28 | Compuverde Ab | Method and device for writing data to a data storage system comprising a plurality of data storage nodes |
US8843710B2 (en) | 2011-09-02 | 2014-09-23 | Compuverde Ab | Method and device for maintaining data in a data storage system comprising a plurality of data storage nodes |
US8769138B2 (en) | 2011-09-02 | 2014-07-01 | Compuverde Ab | Method for data retrieval from a distributed data storage system |
US8997124B2 (en) | 2011-09-02 | 2015-03-31 | Compuverde Ab | Method for updating data in a distributed data storage system |
US10430443B2 (en) | 2011-09-02 | 2019-10-01 | Compuverde Ab | Method for data maintenance |
US10579615B2 (en) | 2011-09-02 | 2020-03-03 | Compuverde Ab | Method for data retrieval from a distributed data storage system |
US9305012B2 (en) | 2011-09-02 | 2016-04-05 | Compuverde Ab | Method for data maintenance |
US10769177B1 (en) | 2011-09-02 | 2020-09-08 | Pure Storage, Inc. | Virtual file structure for data storage system |
US10909110B1 (en) | 2011-09-02 | 2021-02-02 | Pure Storage, Inc. | Data retrieval from a distributed data storage system |
US11372897B1 (en) | 2011-09-02 | 2022-06-28 | Pure Storage, Inc. | Writing of data to a storage system that implements a virtual file structure on an unstructured storage layer |
US9965542B2 (en) | 2011-09-02 | 2018-05-08 | Compuverde Ab | Method for data maintenance |
US9626378B2 (en) | 2011-09-02 | 2017-04-18 | Compuverde Ab | Method for handling requests in a storage system and a storage node for a storage system |
Also Published As
Publication number | Publication date |
---|---|
EP1521189A3 (fr) | 2007-02-14 |
US6983429B2 (en) | 2006-01-03 |
US20050071793A1 (en) | 2005-03-31 |
EP1521189B1 (fr) | 2018-05-02 |
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