EP1491347A1 - Method and system to reduce printing errors in a mail processing device - Google Patents

Abstract

Method for reducing printing errors during printing of mail items has the following steps: generation of encoder impulses corresponding to the relative movement between print and print medium; up and down counting to determine a state with reduced time interval between encoder impulses; execution of direct memory access (DMA) for accessing binary pixel data and; implementation of a print cycle for the data string with subsequent DMA access to the data string during subsequent print cycles. An independent claim is made for an arrangement for reducing printing errors during printing of moving mail items with a moving print head.

Description

The invention relates to a method for reducing printer errors during printing in a mailing machine, according to the preamble of claim 1 and an arrangement according to the preamble of claim 4. The invention is used in franking machines, addressing machines and other printing mail processing equipment.

The invention is related to unpublished German patent applications 10230678.8 entitled "Arrangement for Controlling Printing in a Mailing Machine" and 10230679.6 entitled "Method for Controlling Printing in a Mailing Machine".

In the field of digital printing, the variable print image share is becoming more extensive and the print resolution is getting higher and higher. For example, the variable printed image portion should be flexible for different postal requirements and is changed from impression to impression. At the same time, the controller is burdened with other tasks. To relieve the control by a microprocessor, it has proven to be advantageous, belonging to a print image column To arrange pixel data in the pixel memory so that variable pixels can be changed by the microprocessor in the available time. Furthermore, it has proven to be advantageous if the responsible for the control of the printing mail processing device or system microprocessor is relieved by a pressure data control in the control of printing. The printing requires a relative movement between a print head and a print carrier, for example a sheet-like object, letter, postcard, packet, franking strip, address label or label.

US Pat. No. 6,457,901 (DE 10032855 A1) proposes a device for printing on a print carrier, which is used in a mail processing device, such as preferably in the franking machine ultimail® of the patent owner Francotyp Postalia AG & Co.KG. The print carriers, for example letter envelopes, franking strips or comparable items to be franked, are transported downstream in the transport direction by means of a driven transport drum, with a non-driven counterpressure device pressing the print carrier against the transport drum in the pressing direction orthogonally to the transport direction. The two ink cartridges partially protrude into the transport drum and carry two inkjet printheads, which perform the printing on the moving print carrier without contact. Both printheads are arranged orthogonal to the transport direction and orthogonal to the pressure direction and with their nozzles close to the edge of the transport drum, wherein the nozzles can produce a complete impression during a passage of the print carrier through the machine. On the front side of the transport drum markings are applied close to the circumference, which are distributed over the circumference of the transport drum. The markings are, for example, reflective lines, which are detected by a reflected light beam or transmitted light barrier of an encoder and converted by the microprocessor of a controller into pressure pulses in the ratio 1: 1. Gradual slow fluctuations in the transport speed thus have no influence on a generated print image if the print cycle is changed accordingly in its duration.

According to the printhead manufacturer, a print cycle should last as much as 90% of the time between two positive encoder edges. The time between the encoder edges can be measured and the pressure cycle time adjusted accordingly. The set value for the print cycle duration, however, becomes effective only after its determination with a delay of at least two encoder clock cycles. Changes in the letter thickness and mechanical vibrations of the encoder scanning system can cause sudden changes in the transport speed. However, the sudden variations in transport speed have a negative impact on a generated print image, i. despite a subsequent adjustment of the print cycle time to the distances between the encoder edges, printer errors must be expected due to insufficient distances between the encoder pulses.

The object of the invention is to provide a method and an arrangement for reducing printer errors during printing on a moving mail in a mailing machine, wherein the printer errors caused by encoder pulses with too short a time interval. A cost-effective solution is to ensure a high print quality even under unfavorable conditions.

The object is achieved with the features of the method according to claim 1 or with the features of the arrangement according to claim 4.

Assuming that encoder pulses are generated and fed to a print data controller in accordance with the relative movement between the printer and a print carrier, with correct encoder pulses at each encoder pulse edge, one cycle of a sequence of DMA cycles and one print cycle are started without printer errors. The print data controller generates print data for portions of each print column from the pixel data and triggers a print cycle for the latter. This relieves the microprocessor of controlling the printing. During each DMA period, binary pixel data of a data string for pressure data control is transmitted from the pixel memory, which binary data depends on the connected printhead type for a print cycle. The invention is therefore based on the consideration that it would be unfavorable for the evaluation of printed security-relevant postal data, if complete print cycles, ie whole print columns missing or printed pixels belonging to a print column are printed offset over several print columns, because the encoder pulses precede the print cycles. This can be lessened by following complete print cycles immediately. It has been found that the failure of only a few pixels from individual printing gaps does not represent a decisive obstacle to the evaluation of security prints with a print image resolution of> 300 dpi, if the failing pixels are distributed over the gaps, ie not immediately after one another. Assuming that a reduction of the encoder period only occurs intermittently, a print cycle is aborted if there are several successive encoder pulses too short a time interval, provided that the encoder period is greater than a period of time with DMA cycles. By subsequently adapting the print cycle duration to the distances between the encoder edges, it is also ensured that this case remains a temporary exception.

• a) Erzeugen von Encoderimpulsen entsprechend der Relativbewegung zwischen Drucker und Druckträger,
• b) Vorwärts- und Rückwärtszählen zur Auswertung eines Zustandes mit verringerten zeitlichen Abstandes benachbarter Encoderimpulse,
• c) Durchführung von direkten Speicherzugriffen (DMA) für einen Datenstring von binären Pixeldaten und
• d) Durchführung eines Druckzyklusses für den vorgenannten Datenstring, wobei während des Druckzyklusses weitere direkte Speicherzugriffe (DMA) für einen nächsten Datenstring erfolgen und wobei nach der Durchführung der direkten Speicherzugriffe (DMA) für den nächsten Datenstring und in Abhängigkeit vom zeitlichen Abstand der Encoderimpulse einer Anzahl von aufeinanderfolgenden Encoderimpulsen der Druckzyklus vollständig ausgeführt wird, solange der Mittelwert der Encoderperiode die eingestellte Dauer eines Druckzyklusses nicht unterschreitet oder wobei bei verringertem zeitlichen Abstand der Encoderimpulse der Anzahl von Encoderimpulsen die Durchführung des Druckzyklusses zum Ausdrucken von binären Pixeldaten eines vorherigen Datenstrings vorzeitig abgebrochen wird.

The procedure for reducing printer errors during printing in a mailing machine includes the following steps:

• a) generating encoder pulses according to the relative movement between the printer and the print carrier,
• b) forward and backward counting for evaluation of a state with reduced time interval of adjacent encoder pulses,
• c) Performing direct memory accesses (DMA) for a data string of binary pixel data and
• d) carrying out a printing cycle for the aforementioned data string, wherein during the printing cycle further direct memory accesses (DMA) are carried out for a next data string and wherein after carrying out the direct memory accesses (DMA) for the next data string and depending on the time interval of the encoder pulses of a number of successive encoder pulses, the printing cycle is carried out completely, as long as the mean value of the encoder period does not fall below the set duration of a printing cycle, or wherein at a reduced temporal Distance of the encoder pulses of the number of encoder pulses the execution of the print cycle for printing out binary pixel data of a previous data string is aborted prematurely.

The print data control is connected on the one hand via a bus with the microprocessor and with a pixel memory for the transmission of the print data and on the other hand with an encoder which detects the movement of the print carrier. At least one print head is connected to the print data controller in a manner known per se via a driver circuit. The print data controller, in a printhead-type dependent sequence, provides the required data to the respective drive circuitry of an associated printhead. It is envisaged that the print data controller has an evaluation unit and a logic for error reduction of printer errors, which encoder pulses are supplied and which contains a resettable encoder clock counter whose count is incremented within a count range smaller than or equal to an upper limit with each leading edge of an encoder pulse whose count is decremented with each print cycle start and the output side outputs a digital count, the latter is evaluated by the evaluation unit with respect to exceeding a set within the count range target value, when not exceeding the aforementioned target value, each pressure cycle completely executed and a running pressure cycle when exceeding the aforementioned target value the condition is aborted that all direct memory accesses (DMA cycles) to the pixel memory are prepared, which prepare the next print cycle ,

The print data control consists, for example, of at least one pixel data processing unit, a DMA controller, an address generator and a printer controller. The pixel data for each current print cycle is alternately stored in one of two buffers of the pixel data preparation unit. The pixel data for the next print cycle are loaded via DMA into a second buffer of the pixel data processing unit, while the pixel data for the current print cycle are transmitted to the respective driver circuit of the associated print head. The address generator provides for this purpose read addresses for pixel data of the pixel data processing unit and the printer controller organizes the serial output of the pixel data to the respective driver circuit in a print cycle in dependence on the encoder pulses. The printer controller according to the invention has a logic for error reduction of printer errors, which are caused by encoder pulses too short a time interval. The aforesaid logic includes a resettable encoder clock counter whose count is incremented within a count range less than the upper limit of each leading edge of an encoder pulse, the count of which is decremented at each print cycle start, and whose outputs are coupled to first and second comparators, the first comparator being reached of the zero count prevents decrement and the second comparator checks to reach the upper limit. The encoder clock counter provides the output side of the aforementioned count and is operatively connected to the address generator, the latter aborts the current print cycle when all pixel data for the next print cycle via DMA have already been loaded into the buffer of the pixel data processing unit and the counter value in the count range of the encoder clock counter a predetermined Setpoint has exceeded.

Figur 1a,

Impuls/Zeit-Diagramm für korrekte Encoderimpulse ohne eine Fehlerreduzierung,

Figur 1b,

Impuls/Zeit-Diagramm für Encoderimpulse, wobei die Encoderimpulse in einem zu geringen zeitlichen Abstand auftreten, und ohne Fehlerreduzierung,

Figur 1c,

Impuls/Zeit-Diagramm für Encoderimpulse ohne Fehlerreduzierung, wobei die Encoderimpulse im zu geringen zeitlichen Abstand über einen längeren Zeitabschnitt auftreten,

Figur 1d,

Impuls/Zeit-Diagramm für korrekte Encoderimpulse mit Fehlerreduzierung,

Figur 1e,

Impuls/Zeit-Diagramm für Encoderimpulse mit einem zu geringen zeitlichen Abstand und mit Fehlerreduzierung,

Figur 1f,

Impuls/Zeit-Diagramm für Encoderimpulse mit Fehlerreduzierung, wobei die Encoderimpulse einen zu geringen zeitlichen Abstand über einen längeren Zeitabschnitt aufweisen,

Figur 2,

Blockschaltbild für die Pixeldatenaufbereitung durch eine Druckdatensteuerung,

Figur 3,

Ausschnitt aus der Schaltungsanordnung nach Fig.2 mit einer Pixeldatenaufbereitungseinheit für den zweiten Druckkopf,

Figur 4,

Druckersteuerung,

Figur 5,

Flussplan zur Ablaufsteuerung der Druckersteuerung,

Figur 6,

Logik zur Druckerfehlerreduzierung,

Figur 7a,

Flussplan zur Druckerfehlerreduzierung,

Figur 7b,

Impuls/Zeit-Diagramm für Druckerfehlerreduzierung,

Figur 8,

Blockschaltbild eines Adressengenerators,

Figur 9,

Blockschaltbild einer DMA-Steuerung,

Figur 10,

Flussplan zur DMA-Steuerung,

Figur 11,

Flussplan zur Adressengenerierung,

Figur 12,

Tabelle zur Adressengenerierung,

Figur 13,

Flussplan der Ausgaberoutine.

Advantageous developments of the invention are characterized in the subclaims or are presented in more detail below together with the description of the preferred embodiment of the invention with reference to FIGS. Show it:

FIG. 1a,

Pulse / time diagram for correct encoder pulses without error reduction,

FIG. 1b,

Pulse / time diagram for encoder pulses, where the encoder pulses occur too short a time interval, and without error reduction,

FIG. 1c,

Pulse / time diagram for encoder pulses without error reduction, wherein the encoder pulses occur in too short a time interval over a longer period of time,

FIG. 1d,

Pulse / time diagram for correct encoder pulses with error reduction,

FIG. 1e,

Pulse / time diagram for encoder pulses with too short a time interval and with error reduction,

FIG. 1f

Pulse / time diagram for encoder pulses with error reduction, wherein the encoder pulses have too short a time interval over a longer period of time,

FIG. 2,

Block diagram for the pixel data processing by a pressure data control,

FIG. 3,

2 shows a section of the circuit arrangement according to FIG. 2 with a pixel data processing unit for the second printhead, FIG.

FIG. 4,

Printer control,

FIG. 5,

Flowchart for the flow control of the printer control,

FIG. 6,

Logic for printer error reduction,

FIG. 7a,

Flowchart for printer error reduction,

FIG. 7b,

Pulse / time diagram for printer error reduction,

FIG. 8,

Block diagram of an address generator,

FIG. 9,

Block diagram of a DMA controller,

FIG. 10,

Flow plan for DMA control,

FIG. 11,

Flowchart for address generation,

FIG. 12,

Table for address generation,

FIG. 13,

Flowchart of the output routine.

FIG. 1a shows a pulse / time diagram for correct encoder pulses without error reduction. Upon the occurrence of each encoder pulse edge, a print cycle and a DMA period are started with DMA cycles when previously a previous print cycle has been completed. The latter is the case with correct encoder pulses.

When printing in a mailing machine, for example, a postage meter, a mail piece is moved in the transport direction under or on at least one print head along. In this case, the print image is generated from columns in a vertical arrangement to the transport direction, each print head with a time-offset printing an associated part of the same column. The time offset in the control of both printheads in order to print one and the same column results, on the one hand, from the distance between the two printheads in the transport direction and, on the other hand, from the transport speed of the print carrier in the transport direction. Since the two print heads are arranged offset in the transport direction to each other and each printhead has at least 300 nozzles, which are also arranged in two spaced in the transport direction nozzle rows, pixels are printed in four spaced pressure columns at the same time driving both printheads at any time. The control of all 300 nozzles of each printhead takes place within a printing cycle in which 22 groups of 14 pixel data are successively transferred to the printhead and printed.

The letter movement is detected by an encoder. After each positive edge of the encoder signal, a print cycle is started, provided that before the occurrence of this encoder edge of the triggered by the previous edge print cycle is completed (Figure 1a). The latter is not the case, however, if a sequence of encoder pulses occurs at too short a time interval because of too short a pulse width or pause (FIG. 1b).

FIG. 1b shows a pulse / time diagram for encoder pulses, where the third to sixth encoder pulses occur in too short a time interval. So not every encoder pulse will trigger a print cycle out. This means that some encoder pulses, especially the third and fifth encoder pulse, now trigger no print cycle and no DMA period, since the time between the second to sixth encoder pulses is too short. The causes are different. The encoder disk used may have an error of up to 10%. It is also necessary to assume additional errors such as a sudden change in the transport speed, which is caused by changes in letter thickness, impacts and mechanical vibrations between the encoder disk and the encoder scanning system. Despite an adjustment of the printing cycle time to the distances between the encoder edges must therefore be expected with printing errors due to insufficient distances between the encoder pulses, if no measures to reduce the error are provided.

FIG. 1c shows a pulse / time diagram for encoder pulses without error reduction, wherein due to too short a pulse width and / or pause, the second to seventh encoder pulses have too short a time interval, so that over a longer period of time, only each one second print cycle and time period is triggered with DMA cycles. For printing, in particular a 2D barcode, printed image errors can be very annoying if the authenticity of a franking imprint is to be detected therewith.

In the case of the occurrence of encoder pulses in too short a time interval only the next following encoder pulse triggers a print cycle, ie in Figure 1b, the fourth and sixth encoder pulse and in Figure 1c, the fourth, sixth and eighth encoder pulse. Thus, the distance between the printed dots in the transport direction is about twice as large as intended. Also, the pixels belonging to a print column are offset over several print columns offset as dots. The print quality deteriorates to the extent that encoder pulses occur in too short a time interval.

FIG. 1 d shows a pulse / time diagram for correct encoder pulses with error reduction. The time between the encoder edges is determined by the microprocessor, which then adjusts the print cycle time according to the specifications of the printhead manufacturer, which is effective with a delay of at least two encoder clocks. According to the printhead manufacturer, a print cycle should last as much as 90% of the time between two positive encoder edges. Together with the aforementioned control of the printing cycle duration, which is effective for encoder pulses with a long time interval, a counter for encoder pulses with insufficient time interval is used according to the invention. The encoder clock counter is used for error reduction. It is reset to the value 'zero' at the beginning of each print cycle and incremented at each encoder pulse, i. set here to the value 'one'. After the start of the DMA control and the address generator, the latter initiating the print cycle for the pixel data of a data string, the encoder clock counter is decremented, i. set here to the value 'zero'.

FIG. 1e shows a pulse / time diagram for encoder pulses with too short a time interval and with error reduction. The time interval between the first two encoder pulses is greater than one print cycle. From the second to the sixth encoder pulse, however, the time interval between adjacent encoder pulses is significantly smaller than a printing cycle. From the sixth encoder pulse, the time interval between adjacent encoder pulses increases again and is greater than one print cycle. According to the invention, the distance of the printing cycles from each other is reduced in dependence on the reduced time interval from a number of encoder pulses until the subsequent printing cycle for printing binary pixel data of a subsequent data string directly follows a completely executed printing cycle for printing out binary pixel data of a previous data string wherein the decreasing occurs as the encoder pulses precede the printing cycles.

FIG. 1f shows a pulse / time diagram for encoder pulses with error reduction, wherein the encoder pulses have too short a pulse width and / or pause over a relatively long period of time. In FIG. 1f, a count value 2 which exceeds a set value Z = 1 results in the seventh encoder pulse in that the current print cycle is aborted prematurely by the region shown hatched and a new print cycle begins.

Figure 2 shows the block diagram of the preferred pixel data conditioning circuitry by a print data controller. A first and a second printhead 1 and 2 are each connected via a driver unit (pen driver board) 11 and 12 to a print data controller 4, which at the input side receives 16 bits of parallel binary print image data from a bus 5 on the input side and serial on the output side binary print image data to the driver units 11 and 12 outputs. At least one microprocessor 6, a pixel memory 7, a nonvolatile memory 8 and a read-only memory 9 are connected in terms of address, data and control via the BUS 5. An encoder 3 is connected to the print data controller 4 to trigger the buffering of the binary pixel data and the printing of the print image columns, each printhead having a clock frequency of max. 6.5 KHz is operated. An inkjet printhead which can be postally secured for a franking imprint and can be actuated via an associated pinning unit (pen driver board), which is arranged in an HP 51645A ink cartridge from Hewlett Packard, is described in detail in the European patent application EP 1 176 016 A2, which discloses the title carries: Arrangement and method for data tracking for warm-up cycles of inkjet printheads. The print data controller 4 has a first and second pixel data processing unit 41 and 42 and the associated controls, such as DMA controller 43, address generator 44 and printer controller 45. The controllers include an evaluation unit 453 and a logic 452, which supplied the encoder pulses e for error reduction of printer errors become. It is provided that a printer controller 45 is connected to at least the DMA controller 43 and the address generator 44 and that the address generator 44 is connected to the pixel data processing unit 41, 42 in terms of control.

The printer controller 45 is connected directly to the microprocessor 6 via the bus 5 and via an interrupt signal control line I. The DMA controller 43 is connected to the microprocessor 6 via a control line for DMA control signals DMA _ACK , DMA _REQ .

FIG. 3 shows a section of the circuit arrangement according to FIG. 2 with the pixel data processing unit 42 for the second print head, with the DMA controller 43 for a direct memory access (DMA) as well as with the address generator 44 and the printer controller 45. The encoder 3 supplies a signal e and is connected to the inventive logic 452 of the printer controller 45. The latter is connected to the DMA controller 43 directly via control lines 46 for first DMA control signals (DMA start and DMA busy), the DMA controller 43 being supplied with the DMA start signal by the printer controller 45, and with the DMA Control 43 outputs the DMA busy signal with the value 'zero' to the printer controller 45 to signal that the DMA cycles have ended. The DMA controller 43 is also connected to the address generator 44 via a DMA busy signal control line 50.

The printer controller 45 is connected to the microprocessor 6 via the bus 5 and via an interrupt signal control line 47, to the address generator 44 via a control line for supplying an address generator start signal AG-start and to the DMA controller 43 via a switching line 49 for a switching signal SO connected. At least the microprocessor 6, the pixel memory 7, the nonvolatile memory 8 and the read-only memory 9 are connected in terms of address, data and control via the bus 5. It is provided that the printer controller 45 has means for generating and outputting a switching signal SO in order to drive the pixel data processing unit 42 thereby selecting the pixel data from the respectively first or the respective second of the two latches 412 and 422 for transmission to the driver unit 12 become. The driver unit 12 can thereby be supplied in groups to the binary pixel data of a further data string. The DMA controller 43 is supplied from the printer controller 45, the switching signal SO. The DMA controller 43 has means for generating and outputting selection signals Sel_2.1, Sel_2.2 as a function of the switching state of the switching signal SO in order to temporarily store the binary pixel data in the respectively first or the second of the two latches 421 or 422, wherein in a transmission of pixel data from the in each case one of the two latches to the driver unit 12, the respective other latches for latching a data string are successively selected by the selection signals. The binary pixel data is provided to the pixel data conditioning unit 42 in the DMA periods in a data string manner, respectively.

The DMA controller 43 outputs the DMA-busy signal with the value 'Zero' to the printer controller 45 to signal that all direct memory accesses have occurred, i. the period is completed with DMA cycles. The printer controller 45 is connected to the address generator 44 via at least one control line for supplying a start signal (AG start). The address generator 44 has - in a manner not shown here - a unit for generating read addresses and means for forming an address read signal AR. If a number of address read signals AR has been generated for an address group A, the address generator 44 outputs a print start signal PS via the control line 48 to the printer controller 45.

After transmission of a 22nd data set all of the 300 binary pixel data are transmitted, which requires a ½ inch inkjet print head for printing per print cycle. The other half of the print image is printed by the first printhead. The pixel data processing unit for the first printhead is constructed in a similar manner.

The printer controller 45 is connected to the microprocessor 6 via a control line 47 for an interrupt signal I and via the bus 5. At least the microprocessor 6, the pixel memory 7, the non-volatile memory 8 and read-only memory 9 are connected in terms of address, data and control via the BUS 5. The printer controller 45 has means for generating and outputting a switching signal SO and is connected via a control line to the DMA controller 43 and to the pixel data processing unit 42. The latter is driven to by means of Switching signal SO one of the latches 412, 422 for a transmission of pixel data to the driver unit 12 to select. The latter can thereby be supplied in groups to the binary pixel data of an already stored data string. The switching signal SO is supplied to the DMA controller 43 to select the other one of the latches 412 and 422 for pixel data loading. The DMA controller 43 has means for generating and outputting selection signals Sel_2.1, Sel_2.2 as a function of the switching state of the switching signal SO in order to buffer the binary pixel data into the respectively first or the respective second of the two latches 421 or 422, wherein in a transfer of pixel data from the respective one of the two latches to the driver unit 12, the respective other latches for buffering a data string are successively selected by the selection signals.

The two pixel data processing units are each connected on the input side to the bus 5, but there only to the low-order 16 bits of the data bus. In the following exemplary embodiments, the terms "data word" and "wordwise" should always be understood to mean a 16-bit wide data word if the data word width is not expressly specified additionally. The pixel data for a ½ inch printhead requires only half the space (at most 320 bits from each data string) in the pixel memory 7, from which this pixel data is provided to the pixel data conditioning unit 42. A data string for both printheads therefore requires that buffering of 20 * 16 bit data words each time be performed twice, for example in the respective first buffer. For successive data strings, the first and second latches 421 and 422 are alternately selected by the selection signals Sel-2.1 and Sel-2.2.

It is envisaged that the DMA controller 43 is control connected to the microprocessor 6 and to the latches 421 and 422, that the DMA controller 43 comprises means for generating and outputting address write signals AW, which in a DMA access to the in Pixel memory 7 stored binary pixel data whose writing into the latches 421, 422 of the pixel data processing unit 42nd allow. The DMA controller 43 supplies a 5-bit address write signal AW for wordwise addressing. The latter is in each case at a separate address input of the first and second buffer memories 421 and 422 for pixel data for the second print head. The DMA controller 43 provides a first select signal Sel_2.1 for pixel data for the second printhead and asserts a separate control input of the first pixel data for the second printhead 421. The DMA controller 43 provides a second select signal Sel_2.2 for pixel data for the second printhead and asserts a separate control input of the second pixel data latch 422 for the second printhead.

It is provided that the address generator 44 has at least means for generating and outputting address signals AR, AP and control signals WR, LD, PS, and wherein the address signals AR, AP and control signals WR, LD of the pixel data processing unit 41, 42 for selecting the cached binary pixel data and their grouping in a predetermined order.

Each pixel data processing unit has two latches, a selector for selecting the binary pixel data, and a shift register for parallel / serial conversion of the binary pixel data provided in a new order. The address read signals AR generated by the address generator 44 are supplied to the latches and the selector of the pixel data processing unit. The primitive address signals AP and the write control signal WR generated by the address generator 44 are supplied to the selector, and a load signal LD is supplied to the shift register. From the printer controller 45, a start signal AG-start is supplied to the address generator 44. The address generator 44 now provides an address read signal AR for selecting the data word with the pixel data destined for the second printhead. For word-by-word addressing, the higher-order bits of the address read signal AR are applied to a separate address input of the first and second buffer memories 421 and 422. The four least significant bits of the address read signal AR are applied to an address input of a second selector 423 and allow addressing within the 16-bit data word. The parallel data outputs of the first and second pixel data for the second printhead 421 and 422 are applied to a first and second input of the selector 423, controlled by the address generator 44 at its output a 14 bit parallel data signal to the parallel data input of a shift register 424 for Pixel data for the second printhead. The shift register 424 is controlled by a shift clock signal SCL of the printer controller 45, and outputs a serial data output signal SERIAL DATA OUT 2. The address generator 44 also generates a primitive address AP for controlling the selector 423 and a write signal WR. The address generator 44 outputs a load signal LD to the shift register 424 and a print start signal PS to the printer controller 45. The latter outputs the Latch and Print2 signals for the control of the Pen Driver Board 12. The printer controller 45 is connected via a control line for the output of the switching signal SO to a corresponding control input of the DMA controller 43 and to the selector 423 of the pixel data processing unit 42. The printer controller 45 has evaluation means for evaluating the address and control signals transmitted via BUS 5, which are evaluated with regard to the occurrence of a print command. The printer controller 45 generates at least the DMA start, AG start and SO signals, stores the latter in registers, and communicates with the DMA controller 43 via DMA start, DMA busy, and SO signal control lines. The SO signal is generated only upon receipt of a print command and triggered by the print command is output from the printer controller 45, a first control signal DMA start to the DMA controller 43, the latter then generates a request signal DMA _REQ and sends to the microprocessor 6. The microprocessor has an internal DMA controller (not shown) which, in the case of a direct memory access, applies a specific address to the pixel memory (RAM) 7, thereby enabling word-wise transmission of binary pixel data via BUS 5 to the latches. An address write signal AW is supplied to the latches by the DMA controller 43 for this purpose. The microprocessor 6 can, for example, via DMA from the pixel memory 7 read out a 16-bit wide data word with pixel data and transmit it to the print data control unit. The microprocessor 6 sends an acknowledgment signal DMA _ACK to the DMA controller 43 to synchronize the generation of the address write signal AW in the DMA controller 43 with the DMA cycle of the microprocessor 6. For each DMA cycle, a 16-bit wide data word with binary pixel data enters a buffer. Each of the four latches can provide a total of 320 bits for further data conditioning after each 20 DMA cycles. To achieve a print resolution of 600 dpi, two of the four buffers each are used for storage during the DMA cycles. When wordwise storing and reading pixel data for the second printhead, the two latches 421 and 422 alternate. Therefore, during the DMA cycles, DMA controller 43 supplies first and second select signals Sel_2.1 or Sel_2.2 alternately for word-wise storing pixel data for the second printhead. By way of example, the DMA controller 43 supplies a first selection signal Sel_2.1 and an address write signal AW for the alternate and wordwise storage of pixel data for the second print head. The number of pixels desired for each print image column requires a maximum of 40 data words to buffer 16 bits in two out of four latches. In the DMA controller 43, circuit means are provided for outputting the second control signal DMA-busy and for realizing at least one cycle counter for a predetermined number of 16-bit data words.

In the same manner-but not shown in detail-the binary pixel data for the first printhead is word-delivered via BUS 5 and applied to a corresponding data input of the first and second latches 411 and 412 for pixel data for the first printhead. The first pixel data processing unit 41 for the first printhead-not shown in detail-also includes first and second latches 411 and 412, which are each connected on the input side to the low-order 16 bits of the data bus of the bus 5. The address write signal supplied from the DMA controller 43 AW is also applied to each of a separate address input of the first and second latches 411 and 412 for pixel data for the first printhead. The DMA controller 43 supplies a first select signal Sel_1.1 for pixel data for the first printhead and asserts a separate control input of the first pixel data stager 411 for the first printhead. The DMA controller 43 provides a second select signal Sel_1.2 for pixel data for the first printhead and asserts a separate control input of the second pixel data for the first printhead.

The address read signal AR provided by the address generator 44 is also applied again to a separate address input of the first and second buffer memories 411 and 412 for pixel data for the first print head and to a first selector 413. The parallel data outputs of the first and second pixel pixel data latches 411 and 412 are applied to first and second inputs of the selector 413, controlled by the address generator 44 at its output, a 14 bit parallel data signal to the parallel data input of a shift register 414 for Provides pixel data for the first printhead. The shift register 414 is controlled by the shift clock signal SCL of the printer controller 45 and outputs a serial data output signal Serial data out 1.

The printer controller 45 outputs a shift clock SCL to the pixel data for the first printhead shift register 414 and signals Latch and Print1 for the control of the pen driver board 11. The printer controller 45 is connected to a corresponding control input of the DMA controller 43 and to the pixel data processing unit 41 via a control line for outputting the signal SO.

The cycle counter of the DMA controller 43 is a word counter for a predetermined number of 16-bit data words, which is started by a DMA start signal. The DMA controller is for example part of an application specific circuit (ASIC), wherein the cycle counter is connected on the one hand to the aforementioned means for generating and output of address write signals AW and on the other hand with means for generating and outputting selection signals, the latter - In a manner not shown - have at least one output means and comparison means. For example, a first comparison means controls the output means as a function of the SO signal in order to reach a first predetermined number of 16-bit data words for the first pixel data processing unit 41 specific selection signal Sel_1.1 or Sel_1.2 and after reaching the first predetermined number of 16-bit data words to output a for the second pixel data processing unit 42 specific selection signal Sel_2.1 or Sel_2.2. Upon reaching a second predetermined number of 40 * 16-bit data words, the first or second comparing means receives a signal which is applied to the cycle counter to terminate the counting of DMA cycles. From the signal, a DMA-busy signal with the value 'zero' is generated and output via a register.

While the pixel data for a data string is loaded by direct memory access (DMA) into the respective first latches 411 and 421 and stored therebetween, the respective second latches 412 and 422 can be read out. By means of the special address generator 44 and the selectors 413, 423, the binary pixel data are read from these latches in the order required by the printheads, collected in groups and then transferred by means of shift registers 414, 424 serially to the two printheads. At least one half of the print image column is printed by the first print head and at least one other half print image column is printed by the second print head.

By this solution, binary pixel data can be stored in the pixel memory in an optimal order, which relieves the microprocessor in the printed image change. Data transfer via DMA also relieves the load on the microprocessor.

The error-reducing encoder pulses logic 542 is a component of the printer controller 45 and the associated evaluation unit (not shown) forms part of the address generator 44. The logic 542 then transmits a more than two-bit wide digital count signal ENC to the address generator 44 on the output side Comparator contains.

In the printer controller 45, a data string counter is further realized (not shown in detail), wherein each data string has a maximum of the above-mentioned number of 40 * 16-bit data words. After the binary pixel data taken from a data string has been printed, the data string counter is incremented when the LH edge of the encoder clock occurs. When a predetermined setpoint U on data strings is reached, printing of the print image is ended.

The entire print data control can preferably be realized with an application specific circuit (ASIC) or programmable logic, such as Spartan II 2.5V FPGA from XILINX ( www.xilinx.com ).

4 shows a block diagram of the printer controller 45, which has a logic 542 for error reduction, which will be explained below with reference to FIG 6 in more detail. The aforementioned logic 542 is operatively connected to a sequencer and processing unit 451 to which a printer control logic 450 and an input / output unit 454 are connected. The printer control logic 450 comprises a number of blocks - not shown in detail - but at least the following blocks, such as a data string count V 4503 for the data string number V reached on printing, a register 4504 for the data string setpoint U, a comparator 4506 for U = V, a memory 4505 for Y and other parameters, a shift pulse generator 4507, a latch pulse generator 4508, a first print pulse generator 4509, and a second print pulse generator 4510.

In the first block 451 with the sequence control and processing unit are - not shown - an encoder filter and an encoder controller included, which provides a start signal for printing a column, an interrupt request with each rising edge of the encoder triggers and the correct time Transmission of print data within a print column supported. The encoder filter suppresses spikes on the encoder signals. In the first block 451 - in a manner not shown - yet another counter and further evaluation circuits included, wherein the counter is a system clock for determining the period of encoder pulses is supplied. The e-input BUS-I / O and other registers of the I / O unit 454 communicate with the microprocessor. A microprocessor-controlled control of the pressure cycle duration causes - in a manner not shown - an adjustment of the printing cycle to a predetermined period of time, preferably about 90% of the time between two positive encoder edges.

The input / output unit 454 also has a number of blocks - not shown in detail - but at least the following blocks, a BUS input / output unit 4541, an input signal 4542 for the encoder signal e, an input 4543 for the DMA busy signal, a DMA start signal register 4544, an AG busy signal input 4545, an AG start signal register 4546, a switching signal SO register 4547, a PS signal input 4550; Output 4551 for the I signal, an output 4553 for the shift-clock signal, an output 4554 for the latch pulse signal, a Print1 pulse output 4555 and a Print2 pulse output 455x. To output the digital count ENC, the input / output unit 454 has an ENC output 4560.

If, for example, the evaluation unit 453 shown in dashed lines is likewise a component of the printer controller 45, then the output signal of the evaluation unit 453 is likewise transmitted to the address generator 44, but only as a bit-wide binary abort signal that is present at the output 4560 is provided.

The printer controller 45 can also be realized in the already explained or in an alternative embodiment, wherein each printer controller 45 - independent of the embodiment - has a data string counter 4503 and is connected to the encoder 3. After each printed data string, the value V of the data string counter is incremented when the encoder clock occurs, whereby the printing of the print image is terminated when a predetermined setpoint U of the data string counter is reached.

FIG. 5 shows a flowchart for the flow control of the printer controller. After switching on in step 101, a step 102 is reached and in the routine 100 of the sequence control, the signals reduction signal DEC_ENC, reset signal Encoderzähler_Reset and selection signals Sel_1.1, Sel_1.2, Sel_2.1, Sel_2.2 set to the value 'zero'. In a first query step 103, a data word transmitted via the bus is evaluated with regard to the occurrence of a command for printing start. If the latter has not yet been issued, then it branches into a waiting loop. On the other hand, after the start of printing in a step 104, the column count value V is set to the value 'zero'. The switching signal SO is set to the value 'one' and output. In a second interrogation step 105, the encoder signal e is now evaluated with regard to the occurrence of an LH edge. If the latter has not yet occurred, a branch is made to a waiting loop. On the other hand, in a step 106, a signal DMA start is output and a subroutine 300 is started which sets certain selection signals Sel_1.1, Sel_1.2, Sel_2.1 or Sel_2.2 to the value 'one' in order to convert the binary pixel data into the Latch the pixel data processing units 41 and 42 to take over what will be explained in more detail later with reference to FIG.

In a third interrogation step 107, the DMA busy signal is now evaluated as to whether it has been set to the value 'zero'. If the latter is not yet the case, then it branches into a waiting loop. However, if the DMA-busy signal has been set to the value 'zero', then in step 108 a signal Encoderzähler_Reset: = 1 is generated. Subsequently, a fourth interrogation step 109 is reached, in which the digital output signal ENC of the encoder clock counter is evaluated with respect to a value deviating from the value 'zero'. For the unambiguous time interval of the encoder pulses, the printing cycle is set to a predetermined period of time between two positive encoder edges. This results in a distance between the individual pressure cycles due to the fourth interrogation step 109 (FIG. 1d). If the digital output signal ENC is not equal to the value 'zero', i. equal to the value 'zero', then it is branched into a waiting loop.

When an LH edge of an encoder signal occurs, the encoder clock counter is incremented and the digital output signal ENC now becomes unlike the value 'zero'. When an LH edge occurs, a branch is thus made from the fourth interrogation step 109 in a step 110, in which the switching signal SO is logically negated and then output.

Subsequently, in step 111, the address generator is activated and a subroutine 400 is started, which generates for the pixel data processing units 41 and 42 specific read addresses AR and control signals such as the switching signal SO, the primitive address AP, the write signal WR and a load signal LD. In step 112, a DMA start signal is output and DMA control is enabled to restart the aforementioned subroutine 300. Both subroutines 300 and 400 are in parallel with each other. Then, in a step 113, the print cycle start is signalized by generating a short pulse or by setting the signal DEC_ENC to the value 'one' in a first substep 113a and the signal DEC_ENC to the value 'zero' in a second substep 113b. Subsequently, in a fifth interrogation step 114, it is evaluated whether the address generator has finished its subroutine 400 and whether the DMA busy signal has been set to the value 'zero'. If the former or the latter is still not the case, then a branch is made in a waiting loop. However, if the address generator has completed its subroutine 400 and the DMA busy signal has been set to the value 'zero', then a step 115 is reached. In step 115, the data string count is incremented by a value 'one' to V: = V + 1. In a sixth interrogation step 116, it is evaluated whether the column count value V has reached a limit value U. If this is not the case, then the fourth query step 109 is branched back. Otherwise, the system branches back to the first interrogation step 103 via a step 117, and the routine restarts when a print start command is detected in the first interrogation step 103. In the aforementioned step 117, a reset signal Encoderzähler_Reset: = 0 is generated and reset the encoder counter to the value 'zero'.

In the embodiment shown in FIG. 4, there is a separate second block 452 which is connected to the flow control and processing unit contained first block 451 of the printer controller 45 is operatively connected. The aforementioned block 452 contains the logic for printer error reduction and is part of the printer controller 45. The connection comprises a plurality of - not shown - lines for analog and / or digital electrical signals. The second block 452, which generates a parallel n-bit wide digital output signal ENC representing a count value, serially feeds an encoder signal e filtered by the first block 451. The connection of the second block 452 to the ENC output of the I / O unit 454 is also via the first block 451 of the printer controller 45. The block 451 is connected to the I / O unit 454 of the printer controller 45. After powering up, the processing unit of the first block 451 sets the decrease signal DEC_ENC and the reset signal Encoder_counter_Reset to the value 'zero'. The printer controller 45 includes a third block 450 with the printer control logic. The latter has parameter Y in parameter memory 4505 as an upper limit for the printer error reduction logic.

Alternatively, a separate second block may be omitted (not shown) if the printer error reduction logic is part of the first block 451 of the printer controller 45.

FIG. 6 shows a block diagram of the logic for reducing printer errors. First and second AND gates 4521, 4522 are connected in output to the inputs of an encoder clock counter 4523, which has a first input CLK_down, a second input CLK_up, and a third input ENC_RESET for the reset signal Encoder Counter_Reset. The decrease signal DEC-ENC is supplied via a first input of the first AND gate 4521. With its second input, the output K of a first digital comparator 4524 is connected. In a simple embodiment (not shown), the first digital comparator 4524 used is an OR gate which combines the digital output signal ENC of the encoder clock counter 4523 and outputs a logic signal 'one' on the output side at ENC ≠ 0.

The filtered encoder signal e is supplied in series via a first input of the second AND gate 4522, to whose second input the output L of a second digital comparator 4525 is connected.

At the respective first inputs of the first and second digital comparators 4524, 4525, the count value is in digital form in that a binary value is output at the, for example, n = 4 outputs Q1, Q2, Q3, Q4 of the encoder clock counter 4523. The encoder clock counter 4523 is shown in the embodiment as a 4-bit counter, but should not be limited to this alone. Rather, embodiments other than n-bit counters are possible. In the preferred embodiment, both digital comparators are the same. For example, n Exclusive OR gates are linked together on the output side via an OR gate, wherein each Exclusive OR gate compares one digit of the n-bit number with a corresponding position of the n-bit comparison number.

At the respective second inputs of the first digital comparator 4524 is an n-bit wide digital data signal with the binary value 'zero'. At the respective second inputs of the second digital comparator 4525 is an n-bit wide digital data signal with the corresponding binary values for an upper limit 'Y', which is supplied via the first block 451 of the printer controller 45. The first block 451 of the printer controller 45 also provides the encoder count_reset signal and the DEC ENC signal. The first digital comparator 4524 operates in a manner known per se and outputs a logic signal, for example TTL. For example, a binary value 'one' at the output K indicates that the condition ENC ≠ 0 is fulfilled. The DEC-ENC signal supplied via a first input of the first AND gate 4521 is consequently switched through to the first input CLK_down of the encoder clock counter 4523 in order to decrement the count value. The second digital comparator 4525 outputs a logic signal having the binary value 'one' at the output L when the condition ENC ≠ Y is satisfied. The filtered encoder signal e supplied via a first input of the second AND gate 4522 is then turned on to the second input CLK_up of the encoder clock counter 4523 to increment the count value. The first and second digital comparators 4524 and 4525 respectively provide a TTL signal with the Value 'zero' if the above condition is not met. In this case, the AND gates 4521 and 4522 are disabled.

FIG. 7 a shows a flowchart for reducing printer errors. The routine 700 is started in step 701. After the start, first in step 702 the count is reset to the value 'zero'. In the following interrogation step 703, in the expectation of an activation by means of a reset signal encoder counter reset with the value 'one', the process is continuously branched back to step 702.

The reset signal encoder counter reset is set to the value 'one' after a first DMA cycle by the processing unit of the block 451 shown in FIG. 4, as can be seen from step 108 of FIG. The aforesaid reset signal is applied to the third input ENC_RESET of the encoder clock count 4523 shown in FIG. If an encoder count reset signal of value 'one' is detected in query step 703, then a second interrogation step 704 is reached in which it is determined whether an encoder LH edge is applied to the second AND gate 4522 via a first input while the second comparator 4525 outputs on the output side a value 'one', with which the latter signals that the condition ENC ≠ Y is fulfilled.

The second AND gate 4522 outputs a value 'one' on the output side to the second input CLK_up of the encoder clock counter, which results in the step 705 being incremented by the value 'one' so that the count value ENC: = ENC +1 is achieved. Subsequently, a branch is made to a third interrogation step 706.

If, however, no encoder LH edge is supplied via a first input to the second AND gate 4522 and the condition ENC ≠ Y is not fulfilled, then the second query step 704 branches to the third query step 706.

In the third interrogation step 706, the first comparator 4524 determines that the count ENC is not equal to the count value 'zero'. In this case, a branch is made to the fourth interrogation step 707. Otherwise it becomes the first query step 703 branches back. In the fourth interrogation step 707, it is checked whether the DEC ENC signal supplied via the first input of the first AND gate 4521 has the value 'one'. In this case, the first AND gate 4521 outputs a value 'one' on the output side to the first input CLK_down of the encoder clock counter, which means that in the following step 708 the count value is decremented by the value 'one', so that the count value ENC : = ENC - 1 is reached. Otherwise, the fourth interrogation step 707 branches back to the first interrogation step 703. Subsequently, branching back from step 708 to the first query step 703.

FIG. 7b shows a pulse / time diagram for the printer error reduction. After the start, in the routine 100 of the printer controller, the reset signal Encoder_zähler_Reset and the decrease signal DEC_ENC are set to the value 'zero'. Several encoder pulses occur in too short a time interval over a longer period of time. In the pulse / time diagram of Figure 7b, however, the aforementioned period is longer than in the pulse / time diagram of Figure 1f.

After a first encoder pulse occurs, a first period begins at time t ₀ to load the pixel data for the first print cycle into the latches via DMA cycles. At the time t ₁ , the aforementioned encoder clock counter 4523 is then enabled by the reset signal Encoderzähler_Reset: = 1 set to the value 'one' (FIG. 5, step 108). With the count value 'zero', the condition ENC ≠ Y is fulfilled, so that the aforementioned encoder clock counter is incremented by the value 'one' with each positive encoder edge of the encoder signal e. At time t ₂ , a second encoder pulse occurs and the aforementioned encoder clock counter is incremented and now has the count value 'one'. The output K of the first comparator 4524 (FIG. 6) then outputs the binary value 'one' which is applied to the input of the first AND gate 4521. The output Q1 or K remain set to the binary value 'one' until the time t ₃ . Depending on the time interval between adjacent encoder pulses either the incrementing is continued as long as a predetermined upper limit value Y is not reached, or the count value can be decremented upon the occurrence of a printing cycle. At time t ₃ , a second period is started with DMA cycles and a first print cycle for the pixel data of a data string loaded in the preceding first DMA period with DMA cycles. A pulse-shaped decrease signal DEC_ENC generated by the printer controller 45 is output to the logic 452, resulting in decrementing and the result that the count value again has the value 'zero'.

From the time t ₃ , the first-mentioned buffer of the print data controller 4 is read out for printing a data string. At the same time, the pixel data for a second print cycle are loaded by DMA into the respective other buffer of the print data controller 4. At time t ₄ , a third encoder pulse already occurs before a third print cycle can be started. The outputs Q1 and K remain set to the binary value 'one' until time t ₅ . At time t ₅ , a second print cycle and a third DMA period are started. The time interval of the subsequent times t ₆ and t ₇ , t ₈ and t ₉ and t ₁₀ and t _{11 increases to the} extent that at time t _{11 of} the seventh encoder pulse before the sixth DMA period is effective. In such a case, the encoder clock counter is no longer decremented to the same extent as it is incremented. As a result, the count increases. Despite a current print cycle, the first comparator 4524 checks the aforementioned logic 452 as to whether the counter contents are nonzero. If this is the case, it is waited for a reduction signal DEC_ENC. When a print cycle is started, the printer controller outputs a decrease signal DEC_ENC. At time t ₁₁ , the encoder clock counter is still incremented before decrementing. The outputs Q1 and K remain set to the binary value 'one' from time t ₁₀ to time t ₁₁ and then change to the value 'zero'. At the same time, the output Q2 changes to the binary value 'one', ie the counter content has risen to the count value 'two' at time t ₁₁ . This counter state stops only until the time t ₁₂ , since at the time t ₁₁ , a reduction signal DEC_ENC with the value 'one' to the encoder clock counter was delivered. Output Q2 returns to binary 'zero' and output Q1 returns to binary 'one' according to the decremented 'one' count. At time t ₁₃ , the eighth encoder pulse is output and there are comparable conditions as at time t ₂ with the exception that the encoder clock count before incrementing is now at the aforementioned value 'one'. Also, the eighth encoder pulse at time t ₁₃ is effective before the seventh DMA period with DMA cycles. Output Q2 returns to binary 'one' and output Q1 returns to binary 'zero' according to the incremented count 'two'. This counter state stops only until the time t ₁₄ , since at the time t ₁₃ also a decrementing signal DEC_ENC with the value 'one' was delivered to the encoder clock counter.

After printing each pixel group, the address generator 44 in the subroutine 400 checks to see if the count has reached a set point Z. If this is the case and the data for the next print cycle is loaded into the buffer by DMA, the current print cycle is aborted. In FIGS. 1f and 7b, a count value-which exceeds the setpoint value Z = 1-causes the current print cycle at the seventh or seventh and eighth encoder impulses to be prematurely terminated by the region shown hatched and a new print cycle to begin.

At time t ₁₅ , the sixth print cycle is ended and a seventh print cycle begins. Therefore, a decrease signal DEC_ENC of value 'one' is output to the encoder clock counter, and the output Q1 returns to the binary value 'zero' corresponding to the decremented count value 'zero'. This counter state will only last until time t ₁₆ , since the ninth encoder pulse has been delivered. Thus, it is again incremented and the output Q1 changes back to the binary value 'one' corresponding to the incremented count 'one'. This continues until a predetermined number of printing cycles has been completed. The count of the encoder clock counter is decremented with each print cycle start (Figures 1d, 1e, 1f, and 7b). This process provides a number of advantages. All encoder pulses with too short a time Start distance printing cycles if the encoder pulse period is greater than the DMA period with DMA cycles. Only with a large number of consecutive encoder pulses of very short time interval is a slight impairment of the print quality to be expected. A resulting offset of the pixel data belonging to a print column is at most equal to the spacing of a print column in the illustrated exemplary embodiment. This ensures that the pixels belonging to each print column are not printed offset across multiple print columns. Since only one running print cycle is aborted prematurely, which is hatched in FIGS. 1f or 7b, fewer pixels are correspondingly missing in the print image than in the extreme case when a complete print cycle is missing.

FIG. 8 shows a block diagram of an embodiment of the address generator. It is provided that the address generator 44 has an input / output logic 444, an evaluation unit 442 and a read address generation unit 441, the latter having a first counter 4410 for the primitive address and an associated first comparator 4411 for comparing a count value P of the primitive address with a first setpoint supplied by a first setpoint register 4412. The unit 441 comprises a second counter 4413 for an address group and an associated second comparator 4414 for comparing a count A of the address group with a second set value supplied by a second setpoint register 4415 and a scheduler 4401. The latter works in conjunction with a calculation unit 4402 for the parameter C, a WR signal generator 4403, an LD signal generator 4404, a PS signal generator 4405, with the aforementioned counters 4410 and 4413, with the comparators 4411, 4414, 4418, with the registers 4412, 4415 4417 and with a AGbusy signaling device 4416.

The evaluation unit 442 includes an inverter 4420 for the DMA busy signal, an AND gate 4423, a register 4422 for at least a third setpoint value Z and a third comparator 4421, the count value the encoder clock counter for comparison with at least one third setpoint Z is supplied. The inverter 4420 and the comparator 4421 are each connected to an input of the AND gate 4423 on the output side. Normally, when only ENC values from 'zero' to 'two' occur, the third setpoint Z = 1. The third comparator 4421 may be simply constructed by checking that neither ENC values are 'zero' nor 'one'. occur. For example, on the one hand, the logic signals output at the Q outputs of the encoder clock counter are linked via an OR gate and on the other hand n Exclusive OR gates on the output side via a second OR gate, whereby each Exclusive OR gate in each case has one position of the n-gate. Bit number with a corresponding position of the n-bit comparison number of the setpoint Z = 1 compares and the OR gate outputs are connected via an AND gate, which outputs the output signal of the third comparator 4421. The AND gate 4423 outputs an abort signal BO having the value 'one' on the output side when the negated DMA busy signal and the output signal of the third comparator 4421 have the value 'one'.

It is further contemplated that the input / output logic 444 of the address generator 44 has an input 4450 for the DMA busy signal, an input 4451 for the ENC signal, an input 4444 for receiving the address generator start signal and a register 4445 for the signal to be sent Addressgeneratorbusysignal comprises.

Alternatively, the printer controller may already include the above-mentioned comparison of the ENC signal with the setpoint value Z, in order to generate an abort signal BO as a result of the comparison. The I / O unit 454 of the printer controller 45 then includes a BO output instead of the ENC output 4560. The input / output logic 444 of the address generator 44 need only contain a BO input instead of the ENC input 4451 which has the abort signal BO instead of the count ENC is supplied. This eliminates the control line 50, the DMA busy input 4450 and the evaluation 442 in the address generator 44. A corresponding evaluation unit 453 is instead realized in the printer controller 45 to perform the above comparison of the ENC signal with the setpoint Z and the result the comparison to generate an abort signal for the printing cycle that is supplied to the address generator 44.

The operation of the address generator 44 will be described in more detail below. After a formation of the address read signal AR and after an incrementation of a count value P for the primitive address by the value 'one', the comparison is made in the first comparator 4411, wherein after successively generates a number of read addresses, exceeding the first setpoint or an overflow of the Counter 4410 for the primitive address is triggered, a load signal LD is output and a subroutine for output is started, the counter 4413 for an address group is incremented by the value 'one', wherein falling below the second setpoint in the comparison in the second comparator 4414, a reset of the count value P of the primitive address to the value 'one' and generating a subsequent read address associated with a further address group and wherein upon the occurrence of a predetermined condition, a running print cycle is aborted prematurely. The latter is the case when, on the one hand, the third setpoint value is exceeded during comparison in the third comparator 4421 and, on the other hand, a DMA busy signal with the value 'zero' is output by the DMA controller, which indicates that all DMA cycles to access the pixel memory 7 are prepared, which prepare the next printing cycle.

The process controller 4401 is provided with a parameter C calculating unit 4402 having a signal generator 4403 for generating a write signal WR, a signal generator 4404 for generating a load signal LD, and another signal generator 4405 for generating a print start signal PS for causing the pixel data to be printed out Data string and connected to the Busy signal generator 4416. The input / output logic 444 also has a register 4446 for the delivery of the primitive address AP, a register 4447 for the write signal WR, a register 4448 for the load signal LD, a register 4449 for the output of the address read signal AR and a register 4440 for the output of the Pressure start signal PS on.

FIG. 9 shows a block diagram of a DMA controller. The DMA controller 43 has at least one scheduler 4301, a word counter 4302, a setpoint register 4303, an input / output logic 4304, a memory 4305, a comparator 4306, and a shift register 4307, which are interconnected to perform DMA cycles. Integrated into the flow control 4301 is a further processing unit to which the aforementioned blocks 4302 to 4307 are connected in circuit and which has further comparators (not shown). In order to ensure the signal flow within the print data controller 4 and between the DMA controller 43 and the microprocessor 6, it is further provided that - not shown - the input / output logic 4304 at least one input 43042 for the received DMA start signal and Registers 43043 to 43046 for the select signals to be transmitted, a DMA busy signal register 43047, a request signal DMA _REQ register 43048, an input acknowledgment signal DMA _ACK input 43049, an input 43050 for the switching signal (SO) and register 43051 for the address write signal AW.

FIG. 10 shows a flowchart for DMA control. Such a subroutine 300 is called when a DMA start signal is output from the printer controller 45 to the DMA controller 43 (step 301). In a step 302 of the subroutine 300, a word count W is set to the value 'zero'. A DMA-busy signal is set to the value 'one' and transmitted to the printer controller 45. In a further step 303 of the subroutine 300, a DMA request _signal DMA _REQ having a value 'zero' is transmitted to the microprocessor 6. The latter transmits an acknowledgment signal DMA _ACK to the DMA controller 43. In a first interrogation step 304 of the subroutine 300, a non-receipt of the acknowledgment signal DMA _ACK branches to a waiting loop with a value 'zero'. From the first interrogation step 304 of the subroutine 300, upon receiving the acknowledgment signal DMA _ACK having a value 'zero', a second interrogation step 305 is skipped, wherein the state of the switching signal SO is determined. If the switching signal SO has the state equal to one, then a branch is made to a third interrogation step 306. Otherwise, the switching signal SO has the state equal to 'zero' and a branch is made to a fourth interrogation step 309. In the third interrogation step 306, it is checked whether the word counter has a value W smaller than twenty. For this case (W <20), a branch is made to a step 307. In step 307, the first selection signal for the first print head Sel_1.1. switched to the value 'one' and the address write signal AW receives the current value W of the word counter. In the subsequent step 312, the pixel data are transferred to the latches of the pixel data modification units 41, 42. Subsequently, in step 313, all selection signals are switched to the value 'zero' and a DMA request _signal DMA _REQ with a value 'one' is transmitted to the microprocessor 6.

Then, in step 314, the word count W is incremented with the value 'one'. In a subsequent query step 315, it is checked whether the word counter has a value W less than forty. For this case, in which the word counter has such a value W <40, a branch back to a step 303. Otherwise, a branch is made to a step 316 to output a signal DMA busy having the value 'zero' before the end (step 317) of the subroutine 300 is reached. Otherwise, if it is determined in the third query step 306 that the word count W is not less than twenty, then a branch is made to a step 308 in which the first selection signal for the second print head Sel_2.1. is switched to the value 'one' and the address write signal AW is replaced by the value 'twenty' reduced current value W of the word counter. In the subsequent step 312, the pixel data are taken back into the buffer.

In the aforementioned fourth interrogation step 309, it is also checked whether the word counter has the predetermined value W <20, it being previously determined in the interrogation step 305 that the binary switching signal SO does not have the value equal to one. If the word counter has the predetermined value W <20, then in step 310, the second selection signal for the first printhead Sel_1.2. switched to the value 'one' and the address write signal AW receives the current value W of the word counter. In the subsequent step 312, the pixel data are taken back into the buffer.

Otherwise, if the word counter does not have the predetermined value W <20, the fourth interrogation step 309 branches to a step 311 in which the second selection signal for the second printhead Sel_2.2 is switched to the value 'one' and the address write signal AW the by the value 'Twenty' reduced actual value W of the word counter receives. In the subsequent step 312, the pixel data are taken back into the buffer.

FIG. 11 shows a flowchart for address generation. The addresses of stored binary pixel data begin at both printheads with the start address zero, which is generated in the following manner for the address read signal AR. After the start in step 401, the initial values are called in step 402, A: = 1 for a counter of the address group, P: = 1 for a counter of the primitive address AP and C: = 255 for a counter of the address read signal AR. In the first query step 403, it is asked if the numerical value P of the counter of the primitive address is equal to the value one. If so, the second query step 404 is reached. Here it is determined whether the counter A has reached the value 8 or 9 or 15 or 16. If this is the case, then the step 406 is executed and the numerical value C is subtracted from the numerical value C of the counter of the address read signal AR. In the subsequent third interrogation step 418, it is determined that the numerical value C of the counter of the address read signal AR is greater than or equal to the value zero and then branches to step 419 for the output of the address read signal AR. Otherwise, a branch is made to step 420 in order to add a numerical value 512 to the negative numerical value. After steps 419 and 420, steps 425, 426 and 427 are traversed.

In step 425, the numerical value for the counter of the primitive address AP is output. Then, in step 426, a write signal WR for the binary pixel data entry is output to a collection register. in the Step 427, the numerical value for the numerator of the primitive address AP is incremented by the value one. Then, a fourth interrogation step 428 is reached and it is determined that the numerical value P of the counter of the primitive address AP has not yet reached the limit value 15. Subsequently, branching back to the first query step 403.

In the first query step 403, it is now determined that the numerical value P of the counter of the primitive address is not equal to the value one and branches to the fifth interrogation step 407. If the numerical value P is odd, then the program branches to the sixth query step 408, in which it is checked whether the counter of the address group has the value 8 or 15. If this is the case, then a branch is made to a step 409 and the numerical value 3 is added to the numerical value C of the counter of the address read signal AR. Otherwise, branching is made from the sixth interrogation step 408 to a step 410, and the numerical value 47 is added to the numerical value C of the counter of the address read signal AR.

If, however, the numerical value P is even, then the fifth query step 407 branches to the seventh query step 415, in which it is checked whether the counter of the address group has the value 8 or 15. If this is the case, then a branch is made to a step 416 and the numerical value 41 is added to the numerical value C of the counter of the address read signal AR. Otherwise, a branch is made from the seventh interrogation step 415 to a step 417 and the numerical value C is subtracted from the numerical value C of the counter of the address read signal AR.

From the aforementioned steps 405, 406, 409, 410, 416 and 417, the third interrogation step 418 is reached again and it is determined whether the numerical value C of the counter of the address read signal AR is greater than or equal to the value zero. After steps 419 and 420, steps 425, 426 and 427 are again run until the fourth interrogation step 428 is reached, in which it is determined whether the numerical value P of the counter of the primitive address AP has already reached the limit value 15. If this is the case, then a branch is made to a step 429 and a charging signal for loading the shift register is output. In order to print out the pixel data, a subroutine 500 is started in step 430, in which inter alia a shift clock signal SCL is applied the shift register is applied to serially output the pixel data from the latter. Subsequently, in step 431, the value of the counter of the address group is incremented by the value one. Then, an eighth query step 432 is reached in which it is determined whether the numerical value A of the counter of the address group has already reached the limit value 23. If this is not the case, then a ninth query step 433 is reached, in which it is determined whether the DMA busy signal with the value 'zero' already exists and whether the numerical value ENC of the counter of the address group exceeds the third setpoint Z. If this is not the case, then the first query step 403 branches back. However, if the third setpoint value Z is exceeded, then a signal AG busy: = 0 is output in step 434 and the subroutine 400 is stopped in step 435.

In an alternative variant, with a corresponding evaluation circuit in the printer controller 45, need only be determined in the ninth query step 433, whether an abort signal already exists.

FIG. 12 shows a table for generating addresses, whose address read signals AR for 22 address groups are generated by the aforementioned routine 400. The address generator 44 preferably generates the address values as a binary number and applies them to the pixel data processing units 41, 42. For example, a binary number may be represented as a hexadecimal number or a decimal number, which requires less space. Only for this reason and for better understanding are decimal numbers entered in the table. The routine 400 first generates a primitive address P: = 1 and a binary number zero as an address read signal AR for a first address group A: = 1. Then, one after the other until the primitive address P: = 14, a corresponding binary number is read as the address read signal AR for the first address group A: = 1 generated. The address read signal AR (address read) is thus generated for 14 binary numbers per address group. One after the other corresponding binary numbers are generated as address read signal AR for 22 address groups. By Each address read signal AR is accessed in the buffer memory for a binary pixel data.

The driver units 11 and 12 ignore the binary pixel data obtained at address values A = 1 with P = 2, A = 7 with P = 13, A = 8 with P = 1 and with P = 14, A = 15 with P = 1 and with P = 14, A = 16 with P = 2 as well as those at A = 22 with P = 14 are read. The address values greater than 500 must therefore not be able to be generated completely as a binary number. To provide binary pixel data, all address values greater than 299 are generated but also not needed for printing.

Routine 400 is executed until all print image columns have been printed or aborted. It has already been explained that the rows of nozzles of a printhead become active alternately for printing image columns. While one of the latches is being loaded with binary pixel data via direct memory access, the other latches are read out to transfer rendered groups of binary pixel data to the driver units. The mutual repetition of the routine 400 and further subsequent steps are caused by the printer controller 45, which under the control of a signal e of the encoder 3 also generates the print signals Print 1 or Print 2.

FIG. 13 shows a flowchart of the output routine 500. At the start thereof, the address generator 44 outputs a print start signal PS to the printer controller 45. For a full print cycle, the issue routine is called twenty-two times as a subroutine in the course of subroutine 400 to drive the shift registers in the print data controller 41, 42 and around the driver units 11, 12. After the start in step 501, a step 502 is reached and a shift clock SCL is generated in order to shift the pixel data loaded in the shift register via the serial data output to the respective drive unit 11, 12. Subsequently, in step 503, a latch signal is generated and output to the driver units 11, 12. Then in step 504 the print signals Print1, Print2 are generated and output to the driver units 11, 12 and in step 505 the subroutine 500 is stopped.

In each data string exists a first and second number of data words, respectively, containing binary pixel data for a first and a second inkjet printhead 1, 2, respectively. Each inkjet printhead 1, 2 prints one-half of each print image column, with odd-numbered pixels on at least one half of a first print image column and even-numbered pixels on at least one half through the first and second nozzle rows of each inkjet printhead a second printed image column to be printed. The first or second number of data words in the data string respectively contain the binary pixel data for both nozzle rows of the first and second inkjet printhead, wherein in each data word of each data string only the first and second pixel data are contained for printing a first or further print image column, so that one of the print image columns is completely printed only after printing out the pixel data, for example, three data strings or at least one further data string. From each data string, the row of nozzles respectively in the transport direction in the first direction is supplied with the binary pixel data for the odd-numbered pixels of the first print image column, while the nozzle row in the transport direction in the second direction is already supplied with the binary pixel data for the even-numbered pixels the subsequent further print image column is supplied. Each print image column half is printed by the first and second nozzle rows of each ink jet print head, each print image column half being completed in time after printing with the second nozzle row by printing with the respective first nozzle row.

The first print image column is thus printed at a distance from the second print image column in the transport direction, with both print image columns being further in some print head types and very close to each other in other types. To increase the horizontal print image resolution, in particular to 600 dpi, it is provided that within the distance further print image columns are in the transport direction. This increases accordingly the number U of data strings, which in the Pixel memory are stored for a printed image. If the parameters Z and Y stored in the printer controller 45 and in the address generator 44 are greater than those mentioned in the aforementioned embodiment, discontinuation of current printing cycles will only take place after an even greater number of consecutive encoder pulses have occurred with a reduced time interval , It must then be a larger offset - as shown - accepted. Pixels associated with a print column would then also be printed across a correspondingly larger number of print columns.

The blocks shown in the block diagrams of Figures 2, 3, 4, 8 and 9 are implemented in a positive digital logic in the specific embodiment. Since the type of logic is in principle arbitrary selectable, there are a variety of suitable design variants. The hardware realization is possible in a manner known per se, for example by an ASIC or advantageously by an FPGA (Field Programmable Gate Array). The invention is not limited to the present embodiment. Thus, obviously other other embodiments of the invention can be developed or used, starting from the same basic idea of the invention, which are encompassed by the appended claims.

Claims (10)

A method of reducing printer errors while printing on a moving mail in a mailing machine characterized by the steps of: a) generating encoder pulses according to the relative movement between the printer and the print carrier, b) forward and backward counting for evaluation of a state with reduced time interval of adjacent encoder pulses, c) Performing direct memory accesses (DMA) for a data string of binary pixel data and d) carrying out a printing cycle for the aforementioned data string, wherein during the printing cycle further direct memory accesses (DMA) are carried out for a next data string and wherein after carrying out the direct memory accesses (DMA) for the next data string and depending on the time interval of the encoder pulses of a number of successive encoder pulses, the printing cycle is carried out completely, as long as the average value of the encoder period does not fall below the set duration of a printing cycle, or with a reduced time interval of the encoder pulses of the number of encoder pulses, the execution of the printing cycle for printing binary pixel data of a previous data string is prematurely terminated. A method according to claim 1, characterized in that depending on the reduced time interval of the encoder pulses from a number of encoder pulses, the distance of the print cycles is reduced to each other until the subsequent print cycle for printing binary pixel data of a subsequent data string immediately to a fully executed print cycle for printing of binary pixel data from a previous data string, the decrement taking place as the encoder pulses precede the print cycles. A method according to claim 1, characterized in that for the unencumbered time interval of the encoder pulses setting the Druckzyklusses to a predetermined period of time between two positive encoder edges so that the individual pressure cycles are spaced from each other and that to determine a shortened time interval of the encoder pulses Incrementing a count at each encoder pulse and decrementing the count at each beginning of a print cycle, and on the one hand under a condition and on the other hand at a count exceeding a predetermined setpoint (Z), the current print cycle is prematurely terminated and a new print cycle begins , wherein the aforementioned condition is that all direct memory accesses (DMA) to the pixel memory (7) are prepared, which prepare the next printing cycle. Arrangement for reducing printing errors during printing in a mailing machine, comprising a print data controller (4) for pixel data processing while printing on a moving mail item having at least one print head, via a bus (5) with at least one microprocessor (6), with a pixel memory (7) and connected to an encoder (3), characterized in that the pressure data control (4) has an evaluation unit (442 or 453) and a logic (452) for error reduction of printer errors, which encoder pulses (e) are supplied and which includes a resettable encoder clock counter (4523) whose count is incremented within a count range less than or equal to an upper limit (Y) with each leading edge of an encoder pulse, the count being decremented at each print cycle start, and output at the output of a digital count (ENC), the latter of the evaluation unit (442 or 453) in terms the exceeding of a setpoint value (Z) is evaluated, whereby, if the setpoint value (Z) is not exceeded, each print cycle is completely executed and if the setpoint value (Z) is exceeded, a running print cycle is aborted under the condition that all direct memory accesses (DMA) to the pixel memory (7) are ready, which prepare the next printing cycle. Arrangement according to claim 4, characterized in that the print data controller (4) comprises a DMA controller (43), an address generator (44), a printer controller (45) and the logic (452) for error reduction of printer errors, the encoder pulses (e ) and the output side outputs a digital count value (ENC) to an address generator (44) and that the address generator (44) has an evaluation unit (442) for canceling a current print cycle, wherein the evaluation unit (442) has a comparator (4421) and Register (4422) for storing the setpoint (Z) contains. Arrangement according to claims 4 to 5, characterized in that the logic (452) for error reduction of printer errors includes a resettable encoder clock counter (4523) whose count value increments within a count range less than or equal to an upper limit value (Y) with each leading edge of an encoder pulse whose count value is decremented with each print cycle start and whose outputs are connected to a first comparator (4524) which prevents decrement on reaching the zero count value and to a second comparator (4525) which checks the reaching of the upper limit value (Y) and the output provides the corresponding count value and is operatively connected to the address generator (44), the latter aborting the current print cycle if all pixel data for the next print cycle are already latched into a buffer of pixel data processing via direct memory accesses (DMA) eit (41, 42) have been loaded and the counter value in the counting range of the encoder clock counter exceeds a predetermined setpoint value (Z). Arrangement according to claims 4 to 6, characterized in that the logic (452) for printer error reduction comprises first and second AND gates (4521, 4522), which are connected in output to the inputs of an encoder clock counter (4523), that the encoder clock counter (4523) has a first input (CLK_down), a second input (CLK_up) and a third input (ENC_RESET) for a reset signal (Encoderzähler_Reset), that a decrease signal (DEC-ENC) via a first input of the first AND gate (4521), to the second input of which the output (K) of the first digital comparator (4524) is connected, that an encoder signal (e) is supplied serially via a first input of the second AND gate (4522), with the second one thereof Input of the output (L) of the second digital comparator (4525) is connected, that at the respective first inputs of the first and second digital comparator (4524, 4525), the count is applied, de r is output at the outputs (Q1, Q2, Q3, Q4) of the encoder clock counter (4523) as an n-bit wide binary value, and that at the second inputs of the first digital comparator (4524) a comparison value 'zero' and at the second inputs of the second digital comparator (4525), an upper setpoint value (Y) is present as an n-bit-wide data signal. Arrangement according to Claims 4 to 7, characterized in that the encoder clock counter (4523) is designed as an n-bit counter. Arrangement according to claims 4 to 7, characterized in that via a first block (451) of the printer controller (45) of the print data controller (4) a filtered encoder signal (e), the reset signal (Encoderzähler_Reset) and the reduction signal (DEC- ENC) as well as the upper setpoint (Y). Arrangement according to claims 4 to 9, characterized in that the pressure data control (4) is implemented as an application-specific circuit or programmable logic.

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