EP1439443B9 - Circuit for the voltage supply and method for producing a supply voltage - Google Patents

Description

Technical area

The invention relates to a circuit for power supply and a method for generating a supply voltage. Both the circuit and the method can be used, for example, for the power supply for an integrated circuit.

The generation of a supply voltage, whereby two voltage sources are available, presents a number of problems. The handling of two voltage sources to generate a supply voltage is more complex and difficult than the generation of a supply voltage when only one voltage source is available.

From D1 = US-B1-6177783 For example, a voltage regulator with inputs from multiple supply circuits is known.

The applicant assumes in internal use of an embodiment for a circuit for generating a power supply, as shown in FIG. 1 is shown. In the circuit shown is selected between two external power sources and formed by means of the selected external supply voltage, the output voltage VDD. To this end, the circuit has a first supply voltage input IN1, to which a first external supply voltage VDDEXT1 is applied, and a second supply voltage input IN2, to which a second external supply voltage VDDEXT2 is applied. The two external supply voltages VDDEXT1 and VDDEXT2 are each fed to a comparator input of a comparator CMP. At the same time are the two external supply voltages VDDEXT1 and VDDEXT2 also at the inputs of two voltage regulators REG1 and REG2. Via an external voltage VDDEXT3, which is applied to a voltage input IN3 of the circuit, the two voltage regulators REG1 and REG2 are controlled. The external voltage VDDEXT3 forms at the same time at the operating voltage connection BA of the comparator CMP the operating voltage for the comparator CMP and also the operating voltage for a downstream inverter INV. The output voltage ENREG1 generated by the comparator CMP serves as an additional control voltage for the first voltage regulator REG1 and at the same time as an input voltage for the inverter INV, which forms an inverted output voltage ENREG22 therefrom. This inverted output voltage ENREG22 serves as an additional control voltage for the second voltage regulator REG2. The two outputs of the voltage regulators REG1 and REG2 are connected to each other and form the supply voltage output O of the circuit for power supply.

To ensure that no reverse current occurs in a system with two supply voltages, the in FIG. 1 shown circuit ensures that only one of the two voltage sources and thus only one of the two external supply voltages VDDEXT1 or VDDEXT2 is activated. The other voltage source is deactivated. In general, the voltage source is selected, which provides the higher supply voltage. This is because in this the probability is higher that the supply voltage provided is greater than the nominal supply voltage VDDnom and thus allows a correct regulation. The comparator CMP decides which of the two external voltage sources provides the higher supply voltage. The comparator CMP therefore compares the first external supply voltage VDDEXT1 with the second external supply voltage VDDEXT2. The higher of the two external supply voltages VDDEXT1 and VDDEXT2 is used to supply the downstream analog components. The following situations may occur.

1. The first external supply voltage VDDEXT1 is greater than the second external supply voltage VDDEXT2:

In this case, the voltage ENREG1 at the comparator output assumes the value of the external voltage VDDEXT3. The inverted voltage ENREG22 at the output of the inverter INV, however, assumes the value zero. The first voltage regulator REG1 regulates the supply voltage VDD to the value of the nominal supply voltage VDDnom. The second voltage regulator REG2, on the other hand, disconnects the second external supply voltage VDDEXT2 from the supply voltage output O because the voltage ENREG22 is 0.

2. The first external supply voltage VDDEXT1 is smaller than the second external supply voltage VDDEXT2:

In this case, the voltage ENREG1 at the output of the comparator CMP assumes the value zero. The inverted output voltage ENREG2 at the output of the inverter INV is then equal to the external voltage VDDEXT3. The second regulator REG2 regulates the output voltage VDD to the value of the nominal voltage VDDnom. The first voltage regulator separates the first external supply voltage VDDEXT1 from the supply voltage output O because the voltage ENREG2 is 0.

In the FIG. 1 However, shown circuit for power supply has a number of disadvantages. If the two external supply voltages VDDEXT1 and VDDEXT2 are greater than the nominal voltage VDDnom, both could be used to control the supply voltage VDD. However, only the voltage which is the higher of the two voltages is used. In a system where a voltage supply is high in voltage but can not provide high current, such a solution is not optimal. In such a solution, it is possible that the voltage source is used, although the higher voltage, but the lower current supplies. Voltage sources which provide a high supply voltage but only a small current can be, for example, magnetic or electric fields. If both voltage sources each supply a supply voltage which is greater than the nominal voltage VDDnom and the voltage source which provides the greater voltage is switched off, the voltage regulator associated with this voltage is also switched off and the other voltage regulator is switched on. It is difficult to generate a stable supply voltage VDD while switching between the voltage regulators REG1 and REG2. Alternatively, if the two supply voltage sources supply supply voltages that are the same size, the two voltage regulators are alternately turned on and off, which may cause the entire control system to malfunction.

From the prior art is, as in FIG. 2 shown another embodiment for a power supply known. In this embodiment, the first external supply voltage VDDEXT1 is fed via the first supply voltage input IN1 and a voltage converter 1 to the first input of a comparator CMP1. The second external supply voltage VDDEXT2 is fed via the second supply voltage input IN2 and a second voltage converter 2 to the first input of a second comparator CMP2. The second inputs of the first comparator CMP1 and the second comparator CMP2 are connected to the output of a reference voltage source 3, so that a reference voltage VREF is applied to them. As with the in FIG. 1 In the embodiment shown in FIG FIG. 2 In the embodiment shown, the external voltage VDDEXT3, which is present at the voltage input IN3, is used to control the two voltage regulators REG1 and REG2 and as the operating voltage for the two comparators CMP1 and CMP2. In addition, the external voltage VDDEXT3 is applied to the input of the voltage source 3, which generates the reference voltage VREF.

At the in FIG. 2 In the embodiment shown, the first external supply voltage VDDEXT1 and the second external supply voltage VDDEXT2 are compared with the reference voltage VREF to avoid a reverse current. For further consideration, it is assumed that the two voltage converters 1 and 2 multiply the external supply voltages VDDEXT1 and VDDEXT2 by a factor k. Furthermore, it is assumed that the reference voltage VREF * k is greater than the nominal voltage VDDnom. During operation, the following conditions may occur.

1. The voltage VDDEXT1 is greater than the reference voltage VREF * k and the voltage VDDEXT2 is also greater than the reference voltage VREF * k:

In this case, both voltage regulators REG1 and REG2 regulate the supply voltage VDD to the value of the nominal voltage VDDnom. A return current can not occur here because the voltage VDDEXT1 is greater than the reference voltage VREF * k and this in turn is greater than the nominal voltage VDDnom and this in turn is greater than or equal to the supply voltage VDD and in addition the voltage VDDEXT2 greater than the reference voltage VREF * k is greater than the nominal voltage VDDnom and in turn greater than or equal to the supply voltage VDD.

2. The voltage VDDEXT1 is smaller than the reference voltage VREF * k and the voltage VDDEXT2 is greater than the reference voltage VREF * k:

In this case, the second voltage regulator REG2 regulates the supply voltage VDD to the value of the nominal voltage VDDnom. The first voltage regulator REG1, however, is turned off.

3. The voltage VDDEXT1 is smaller than the reference voltage VREF * k and the voltage VDDEXT2 is smaller than the reference voltage VREF * k:

In this case both voltage regulators REG1 and REG2 are switched off. The supply voltage VDD floats.

4. The voltage VDDEXT1 is smaller than the reference voltage VREF * k and the voltage VDDEXT2 is greater than the reference voltage VREF * k:

In this case, the first voltage regulator REG1 regulates the supply voltage VDD to the value of the nominal voltage VDDnom. The second voltage regulator REG2, however, is turned off.

At the in FIG. 2 shown embodiment of the circuit for power supply are compared to in FIG. 1 embodiment shown the most disadvantages avoided. In the FIG. 2 However, the embodiment shown has the following disadvantages.

The two voltage regulators REG1 and REG2, the two voltage converters 1 and 2 and the reference voltage source 3 must be exactly matched to each other, so that the value k * VREF is greater than the nominal voltage VDDnom. If this is not the case, for example, if k * VREF is less than the first external supply voltage VDDEXT1, and the nominal voltage VDDnom is again smaller than the nominal voltage VDDnom and which in turn is smaller than the second external supply voltage VDDEXT2, this will be false Tuning both regulators REG1 and REG2 is activated and a return current flows from the second external voltage source via the second supply voltage input IN2 to the supply voltage output O and from there back to the first external supply source at the first supply voltage input IN1.

Often it is the case that the two voltage regulators REG1 and REG2 can be switched between different nominal voltages VDDnom1, VDDnom2, VDDnom3, etc. In this case, it is necessary that the two voltage converters 1 and 2 can switch between different multiplication factors k1, k2, k3, etc. In this case, it becomes all the more difficult to exactly match the two voltage regulators REG1 and REG2, the two voltage converters 1 and 2 and the reference voltage source 3 in the manner already described, for each pair (VDDnom1, k1), (VDDnom2, k2). , (VDDnom3, k3). As a result, the circuit requires more chip area, the power consumption increases and the complexity of the circuit increases.

Presentation of the invention

An object of the invention is to provide a circuit for power supply and a method for generating a supply voltage in which no reverse current occurs. The current should flow from one power source to the supply voltage output of the circuit and not from one power source via the supply voltage output of the circuit back to the other power source.

In addition, the criteria for switching the current paths on and off should be selected so that a correct regulation of the supply voltage is possible in a number of different configurations.

With the circuit according to the invention for the power supply and the method for generating a supply voltage, the disadvantages mentioned in the prior art can advantageously be avoided.

The object is achieved by a circuit for power supply with the features according to claim 1 and a method for generating a supply voltage having the features according to claim 8.

Advantageous developments of the invention will become apparent from the features indicated in the appended claims.

In one embodiment of the circuit according to the invention for voltage supply, a first voltage converter is provided, which is connected between the first supply voltage input and the first comparator. There is also a second one Voltage converter is provided, which is connected between the second power supply input and the second comparator. Thus, the two external supply voltages applied to the first and the second supply voltage input can be multiplied by a certain value or reduced by a certain voltage value.

According to a preferred embodiment of the circuit according to the invention, a third voltage converter is provided, which is connected between the supply voltage output and the first comparator. In addition, a fourth voltage setter is provided, which is connected between the supply voltage output and the second comparator. Thus, the voltage applied to the supply voltage output supply voltage can be multiplied by a certain value or reduced by a certain voltage value.

In a development of the circuit according to the invention for voltage supply, the voltage converter are designed such that the voltage that can be applied to their inputs can be converted into a voltage proportional to this voltage with a defined proportionality factor.

Moreover, in the case of the circuit according to the invention, the voltage converters can be designed in such a way that the voltage which can be applied at their inputs can be converted into a voltage reduced by a specific value.

To solve the problem is also proposed to provide a voltage input which is connected to operating terminals of the comparators and the control inputs of the voltage regulator. Thus, inter alia, the operating voltage for the comparators can be specified.

Finally, in the circuit according to the invention, the first voltage regulator, a first N-channel MOS transistor and the second voltage regulator comprises a second N-channel MOS transistor. The control outputs of the two transistors are fed back to the control inputs of the two transistors.

Short descriptions of the drawings

Figur 1

zeigt eine erste Ausführungsform einer Schaltung zur Spannungsversorgung gemäß dem Stand der Technik.

Figur 2

zeigt eine zweite Ausführungsform einer Schaltung zur Spannungsversorgung gemäß dem Stand der Technik.

Figur 3

zeigt eine mögliche Ausführungsform der erfindungsgemäßen Schaltung zur Spannungsversorgung.

Figur 4

zeigt den prinzipiellen Aufbau eines Spannungsreglers, wie er bei der erfindungsgemäßen Schaltung zur Spannungsversorgung Verwendung finden kann.

In the following the invention will be explained with reference to four figures.

FIG. 1

shows a first embodiment of a circuit for power supply according to the prior art.

FIG. 2

shows a second embodiment of a circuit for power supply according to the prior art.

FIG. 3

shows a possible embodiment of the circuit according to the invention for power supply.

FIG. 4

shows the basic structure of a voltage regulator, as it can be used in the circuit for power supply according to the invention.

Ways to carry out the invention

On the Figures 1 and 2 will not be discussed further below, since their explanation has already been given in the introduction to the description. It is therefore referred to the description introduction at this point.

At the in FIG. 3 shown embodiment of the circuit according to the invention for generating a supply voltage, a first supply voltage input IN1 is provided, which can be connected to a first voltage source, not shown, for generating a first external supply voltage VDDEXT1 is. The first external supply voltage VDDEXT1 applied to the first supply voltage input IN1 is fed via a first voltage converter 1 to a first input of a first comparator CMP1. In addition, the first external supply voltage VDDEXT1 is applied to the input of a voltage regulator REG1. The circuit has a second supply voltage input IN2, which can be connected to a second voltage source, not shown, for generating a second external supply voltage VDDEXT2. The second external supply voltage VDDEXT2 is applied via a second voltage converter 2 to a first input of a second comparator CMP2 and to an input of a second voltage regulator REG2. The first voltage regulator REG1 is controlled via the signal at the output of the first comparator CMP1 with the control voltage ENREG1 and an external voltage VDDEXT3 applied to a third input IN3. The same applies to the second voltage regulator REG2. This is controlled by the output voltage ENREG2 of the second comparator CMP2 and the external voltage VDDEXT3. The outputs of the two voltage regulators REG1 and REG2 are connected to each other and lead on the one hand to the supply voltage output O of the circuit and on the other hand to the inputs of a third and fourth voltage converter 3 and 4, which in turn with the second inputs of the first and the second comparator CMP1 and CMP2 are connected. In operation, the desired supply voltage VDD can be tapped off at the output O of the circuit.

The operation of the power supply circuit according to the invention will now be described. In the solution according to the invention, two supply voltages are not compared with each other or two supply voltages with a reference voltage, but a comparison is made between the internally generated supply voltage VDD with the two external supply voltages VDDEXT1 and VDDEXT2.

To facilitate understanding, it is assumed for the following embodiments that the voltage converter 1 multiplies the first external supply voltage VDDEXT1 by the multiplier k and the voltage converter 3 is bridged by a simple line. The same applies to the second external supply voltage VDDEXT2 and the voltage converter 4.

During operation, the following conditions may occur.

1. The value k * VDDEXT1 is less than the nominal voltage VDDnom and the value k * VDDEXT2 is greater than the nominal voltage VDD:

In this case, the supply voltage VDD is zero when switched on. Therefore, the value k * VDDEXT1 is greater than the supply voltage VDD and also the value k * VDDEXT2 is greater than the supply voltage VDD. The control voltage ENREG1 at the output of the comparator CMP1 then takes the value of the voltage VDDEXT3 and the control voltage ENREG2 at the output of the second comparator CMP2 also assumes the value of the external voltage VDDEXT3, which causes the voltage regulators REG1 and REG2 to regulate. The supply voltage VDD therefore now increases until it reaches the value k * VDDEXT1 and exceeds it. Then the first comparator CMP1 switches over and brings the control voltage ENREG1 to the value zero. As a result, the voltage regulator REG1 is turned off. The supply voltage output O is now disconnected from the first external supply voltage VDDEXT1, which is advantageous since the first external supply voltage VDDEXT1 is smaller than the supply voltage VDD. Otherwise, a current would flow from the supply voltage input IN2 to the supply voltage input IN1. The supply voltage VDD continues to increase until it reaches the value of the nominal voltage VDDnom and is regulated to this value. Because the value k * VDDEXT2 is greater than the nominal supply voltage VDDnom, the control voltage ENREG2 remains at the output of the second comparator CMP2 to the value of the external voltage VDDEXT3.

2. The value k * VDDEXT1 is greater than the nominal voltage VDDnom and the value k * VDDEXT2 is greater than the nominal voltage VDDnom:

In this case, the power supply voltage VDD is zero when the power is turned on, so that the value k * VDDEXT1 is greater than the power supply voltage VDD and the value k * VDDEXT2 is greater than the power supply voltage VDD. The control voltage ENREG1 at the output of the first comparator CMP1 therefore assumes the value of the external voltage VDDEXT3 and the control voltage ENREG2 at the output of the second comparator CMP2 also the value of the external voltage VDDEXT3. Both voltage regulators REG1 and REG2 are now working. The supply voltage VDD now increases until it reaches the desired nominal voltage value VDDnom without one of the two voltage regulators REG1 and REG2 being switched off, because the value k * VDDEXT1 is greater than the nominal voltage VDDnom and, at the same time, the value k * VDDEXT2 is greater as the nominal voltage VDDnom. Therefore, both voltage regulators REG1 and REG2 remain active over the entire time.

3. The value k * VDDEXT1 is smaller than the nominal voltage VDDnom and the value k * VDDEXT2 is smaller than the nominal voltage VDDnom and the first external supply voltage VDDEXT1 is smaller than the second external supply voltage VDDEXT2:

In this case, the supply voltage VDD when switching is equal to zero, so that the value k * VDDEXT1 is greater than the supply voltage VDD and at the same time the value k * VDDEXT2 is greater than the supply voltage VDD. Therefore, the comparator CMP1 brings the control voltage ENREG1 to the value of the external voltage VDDEXT3 and the second comparator CMP2 also applies the control voltage ENREG2 to the value of the external one Voltage VDDEXT2. Both voltage regulators REG1 and REG2 now work and ensure that the supply voltage VDD increases until the value k * VDDEXT1 is reached and exceeded. The first comparator CMP1 now brings the control voltage ENREG1 to the value zero, so that the first voltage regulator REG1 is turned off. The supply voltage VDD continues to increase until it reaches the value k * VDDEXT2. A further increase in the supply voltage VDD does not occur because now the second comparator CMP2 sets the control voltage ENREG2 to the value zero and thus switches off the second voltage regulator REG2.

• 4.a) Der Wert k * VDDEXT2 ist kleiner als die nominelle Spannung VDDnom und der Wert k * VDDEXT1 ist größer als die nominelle Spannung VDDnom;
• 4.b) Der Wert k * VDDEXT2 ist größer als die nominelle Spannung VDDnom und der Wert k * VDDEXT1 ist größer als die nominelle Spannung VDDnom;
• 4.c) Der Wert k * VDDEXT2 ist kleiner als die nominelle Spannung VDDnom und der Wert k * VDDEXT1 ist kleiner als die nominelle Spannung VDDnom und die zweite externe Versorgungsspannung VDDEXT2 ist kleiner als die erste externen Versorgungsspannung VDDEXT1;

If necessary, the in FIG. 3 In the case where the two control voltages ENREG1 and ENREG2 assume the value zero, so that the two voltage regulators REG1 and REG2 are switched off, the supply voltage output O is connected to the higher of the two supply voltages VDDEXT1 and VDDEXT2. In this way, the number of operating states in which the controller system is working correctly can be increased.

• 4.a) The value k * VDDEXT2 is smaller than the nominal voltage VDDnom and the value k * VDDEXT1 is greater than the nominal voltage VDDnom;
• 4.b) The value k * VDDEXT2 is greater than the nominal voltage VDDnom and the value k * VDDEXT1 is greater than the nominal voltage VDDnom;
• 4.c) The value k * VDDEXT2 is smaller than the nominal voltage VDDnom and the value k * VDDEXT1 is smaller than the nominal voltage VDDnom and the second external supply voltage VDDEXT2 is smaller than the first external supply voltage VDDEXT1;

If the circuit is symmetrical, the condition 4.a): k * VDDEXT2 less VDDnom and k * VDDEXT1 greater VDDnom can be used to derive the behavior of the circuit from operating state 1: k * VDDEXT1 smaller VDDnom and k * VDDEXT2 larger VDDnom by the two suffixes 1 and 2 of the two external supply voltages VDDEXT1 and VDDEXT2 are interchanged.

The same applies to the operating states 4.b): k * VDDEXT2 greater than VDDnom and k * VDDEXT1 greater than VDDnom and 4.c): k * VDDEXT2 smaller VDDnom and k * VDDEXT1 smaller VDDnom and VDDEXT2 smaller VDDEXT1.

With the solution according to the invention, the embodiments according to FIGS. 1 and 2 adhering disadvantages avoided. Thus, if the supply voltages VDDEXT1 and VDDEXT2 originating from the two voltage sources are higher than the nominal voltage VDDnom, both voltage sources can be used to regulate the supply voltage VDD.

If both supply voltages VDDEXT1 and VDDEXT2 are greater than the nominal supply voltage VDDnom / k and one of the two voltage sources is switched off, it is easier to keep the supply voltage VDD stable than in the prior art because one of the two voltage regulators REG1 or REG2 remains in operation ,

Oscillating switching between the two voltage sources can only occur if the second external supply voltage VDDEXT2 is equal to the nominal voltage VDDnom or if the first external supply voltage VDDEXT1 is equal to the nominal voltage VDDnom. However, since this is a relatively rare situation, this condition will hardly occur.

In addition, it is advantageous that no adaptation is required between the two voltage regulators REG1 and REG2 and the voltage converters 1 to 4.

In the event that the voltage regulators REG1 and REG2 have to switch between different nominal voltages VDDnom1, VDDnom2, VDDnom3, etc., nothing has to be modified in the circuit according to the invention for the voltage supply.

wobei:

• K eine Technologiekonstante,
• LAMBDA/L die Early-Spannung,
• IGS der Drain-Source-Strom,
• VDS die Drain-Source-Spannung,
• VGS die Gate-Source-Spannung,
• VTH die Schwellenspannung,
• W die Breite des Transistors und
• L die Länge des Transistors ist.

In FIG. 4 a possible embodiment for a voltage regulator is shown. For voltage regulation, as shown, two NMOS transistors 6 and 7 may be used. The size of the two NMOS transistors 6 and 7 should be the same and the gate terminals of the two NMOS transistors 6 and 7 should be connected together. The drain-source current IDS in the saturated operating state results for an NMOS transistor by the following equation: $$\mathrm{IDS}=\mathrm{k}*\mathrm{W}/\mathrm{L}*\left(\mathrm{VGS}-\mathrm{VTH}\right)*\mathrm{2}*\left(\mathrm{1}+\mathrm{LAMBDA}*\mathrm{VDS}/\mathrm{L}\right)$$

in which:

• K is a technology constant,
• LAMBDA / L the early tension,
• IGS the drain-source current,
• VDS the drain-source voltage,
• VGS the gate-source voltage,
• VTH the threshold voltage,
• W is the width of the transistor and
• L is the length of the transistor.

The saturated operating state is given when the voltage VDS is greater than the voltage difference VGS - VTH.

The two transistors 6 and 7 have the same gate-source voltage VGS = NGATE-VDD, that is, the current supplied by the two transistors in the saturated operating state is approximately the same, regardless of the external supply voltages VDDEXT1 and VDDEXT2. NGATE is the voltage at the output of the regulator loop 5. This is especially the case when the Early effect of the NMOS transistors is minimized by making the length of the transistors large. When a voltage source is turned off, the corresponding gate is disconnected from the output of the regulator loop 5 by a circuit (not shown). The supply voltage VDD falls by (√2 - 1) * (VGS - VTH), so that as the width of the NMOS transistor increases, the voltage decreases more slowly.

When using such a controller in the in FIG. 3 As shown, it is possible to achieve a continuous operation of the chip, even if one of the two external voltage sources is switched off.

The two voltage regulators REG1 and REG2 operate in principle in the same way. Therefore, the operation of the first voltage regulator REG1 will be described below by way of example for both. When the control voltage ENREG1 is equal to zero, the resistance in the voltage regulator REG1 between its input, which is connected to the first supply voltage input IN1, and its output, which is connected to the supply output O, infinitely large. When the control voltage ENREG1 assumes the value of the external voltage VDDEXT3 and when the supply voltage VDD is greater than the nominal voltage VDDnom, the resistance in the voltage regulator between its input and output increases until the supply voltage VDD equals the nominal voltage VDDnom. The resistance can rise to infinity. If the control voltage ENREG1 equals the value of the external voltage VDDEXT3 and if the supply voltage VDD is less than the nominal voltage VDDnom, the resistance between the input and the output of the voltage regulator REG1 decreases until the supply voltage VDD equals the nominal voltage VDDnom is. Possibly the resistance drops to zero. The nominal voltage VDDnom is a constant voltage.

Basically, the voltage converter generates at its output either a voltage which is reduced by a constant voltage with respect to the input voltage or a voltage which is the product of a constant multiplier k or proportionality factor with the input voltage. The constant multiplier k lies between the values zero and one.

The comparator generates at its output a voltage which is equal to the operating voltage which is applied to its operating voltage input when the voltage applied to the non-inverting input of the comparator voltage is greater than the voltage applied to its inverting input voltage. Otherwise it generates at its output a voltage with the value zero.

LIST OF REFERENCE NUMBERS

IN1

first supply voltage input

IN 2

second supply voltage input

IN3

voltage input

O

Power Output

1

first voltage converter

2

second voltage converter

3

third voltage converter

4

fourth voltage converter

5

regulator loop

6

NMOS transistor

7

NMOS transistor

NGATE

Voltage at the output of the controller loop

VDDEXT1

first external supply voltage

VDDEXT2

second external supply voltage

VDDEXT3

external voltage

VDD

supply voltage

CMP 1

first comparator

CMP2

second comparator

REG1

first voltage regulator

REG2

second voltage regulator

VREF

reference voltage

ENREG1

Output voltage of the first comparator

ENREG2

Output voltage of the second comparator

ENREG22

inverted output voltage of the first comparator

INV

inverter

BA

Operating connection of the comparator

Claims (8)

1. Voltage supply circuit
   having a first supply voltage input (IN1) which is connected to a first comparator (CMP1) and to a first voltage regulator (REG1), a first external supply voltage (VDDEXT1) being able to be applied to the first supply voltage input (IN1),
   having a second supply voltage input (IN2) which is connected to a second comparator (CMP2) and to a second voltage regulator (REG2), a second external supply voltage (VDDEXT2) being able to be applied to the second supply voltage input (IN2),
   having a supply voltage output (0) which is connected to outputs of the two voltage regulators (REG1, REG2) and is fed back to the two comparators (CMP1, CMP2), an internally generated supply voltage (VDD) being able to be tapped off at the supply voltage output (0), characterized in that
   the first comparator (CMP1) is designed to compare the internally generated supply voltage (VDD) or a voltage derived therefrom with the first external supply voltage (VDDEXT1) or a voltage derived therefrom, and
   to switch off the first voltage regulator (REG1) if the first external supply voltage or the voltage derived therefrom is less than the internally generated supply voltage or the voltage derived therefrom; and
   the second comparator (CMP2) is designed to compare the internally generated supply voltage (VDD) or a voltage derived therefrom with the second external supply voltage (VDDEXT2) or a voltage derived therefrom, and to switch off the second voltage regulator (REG2) if the second external supply voltage or the voltage derived therefrom is less than the internally generated supply voltage or the voltage derived therefrom.
2. Circuit according to Patent Claim 1,
   having a first voltage converter (1) which is connected between the first supply voltage input (IN1) and the first comparator (CMP1), and
   having a second voltage converter (2) which is connected between the second supply voltage input (IN2) and the second comparator (CMP2).
3. Circuit according to Patent Claim 1 or 2,
   having a third voltage converter (3) which is connected between the supply voltage output (0) and the first comparator (CMP1), and
   having a fourth voltage converter (4) which is connected between the supply voltage output (0) and the second comparator (CMP2).
4. Circuit according to Patent Claim 2 or 3,
   in which the voltage converters (1, 2, 3, 4) are designed in such a manner that the voltage (VDDEXT1, VDDEXT2, VDD) which can be applied to their inputs can be converted into a voltage (k*VDDEXT1, k*VDDEXT2, k*VDD) which is proportional to that voltage (VDDEXT1, VDDEXT2, VDD) using a proportionality factor (k).
5. Circuit according to either of Patent Claims 2 and 3,
   in which the voltage converters (1, 2, 3, 4) are designed in such a manner that the voltage (VDDEXT1, VDDEXT2, VDD) which can be applied to their inputs can be converted into a voltage that has been reduced by a particular value.
6. Circuit according to one of Patent Claims 1 to 5, having a voltage input (IN3) which is connected to operating connections (BA) of the comparators and control inputs of the voltage regulators (REG1, REG2).
7. Circuit according to one of Patent Claims 1 to 6, in which the first voltage regulator (REG1) has a first N-channel MOS transistor (7),
   in which the second voltage regulator (REG2) has a second N-channel MOS transistor (6),
   the control outputs of the two transistors (6, 7) being fed back to the control inputs of the two transistors (6, 7).
8. Method for generating a supply voltage (VDD),
   in which a first external supply voltage (VDDEXT1) is applied to a first comparator (CMP1) and to a first voltage regulator (REG1),
   in which a second external supply voltage (VDDEXT2) is applied to a second comparator (CMP2) and to a second voltage regulator (REG2),
   and in which the internally generated supply voltage (VDD) is applied to a supply voltage output (0) which is connected to outputs of the two voltage regulators (REG1, REG2) and is fed back to the two comparators (CMP1, CMP2),
   characterized in that
   the first comparator (CMP1) compares the internally generated supply voltage (VDD) or a voltage derived therefrom with the first external supply voltage (VDDEXT1) or a voltage derived therefrom, and
   switches off the first voltage regulator (REG1) if the first external supply voltage (VDDEXT1) or the voltage derived therefrom is less than the internally generated supply voltage (VDD) or the voltage derived therefrom; and
   the second comparator (CMP2) compares the internally generated supply voltage (VDD) or a voltage derived therefrom with the second external supply voltage (VDDEXT2) or a voltage derived therefrom, and
   switches off the second voltage regulator (REG2) if the second external supply voltage (VDDEXT2) or the voltage derived therefrom is less than the internally generated supply voltage (VDD) or the voltage derived therefrom.

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