EP1095466A1 - Method for determining the start of a pulse in a spread spectrum system - Google Patents

Method for determining the start of a pulse in a spread spectrum system

Info

Publication number
EP1095466A1
EP1095466A1 EP00931164A EP00931164A EP1095466A1 EP 1095466 A1 EP1095466 A1 EP 1095466A1 EP 00931164 A EP00931164 A EP 00931164A EP 00931164 A EP00931164 A EP 00931164A EP 1095466 A1 EP1095466 A1 EP 1095466A1
Authority
EP
European Patent Office
Prior art keywords
circuit
integration
symbol
station
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP00931164A
Other languages
German (de)
French (fr)
Inventor
Olivier Paviot
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cellon France SAS
Original Assignee
Cellon France SAS
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cellon France SAS, Koninklijke Philips Electronics NV filed Critical Cellon France SAS
Priority to EP00931164A priority Critical patent/EP1095466A1/en
Publication of EP1095466A1 publication Critical patent/EP1095466A1/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/69—Spread spectrum techniques
    • H04B1/707—Spread spectrum techniques using direct sequence modulation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/69—Spread spectrum techniques
    • H04B1/707—Spread spectrum techniques using direct sequence modulation
    • H04B1/7073—Synchronisation aspects
    • H04B1/7075—Synchronisation aspects with code phase acquisition
    • H04B1/7077—Multi-step acquisition, e.g. multi-dwell, coarse-fine or validation
    • H04B1/70775—Multi-dwell schemes, i.e. multiple accumulation times
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B2201/00—Indexing scheme relating to details of transmission systems not covered by a single group of H04B3/00 - H04B13/00
    • H04B2201/69—Orthogonal indexing scheme relating to spread spectrum techniques in general
    • H04B2201/707—Orthogonal indexing scheme relating to spread spectrum techniques in general relating to direct sequence modulation
    • H04B2201/70702—Intercell-related aspects

Definitions

  • the invention relates to a station comprising a receiving circuit suitable for a system in which information is transmitted in the form of symbols, which receiving circuit includes a synchronization circuit for producing an indication of the start of a symbol.
  • the invention also relates to a synchronization method for determining the start of a symbol.
  • the invention finds its application in the industry for cellular radiotelephony networks in which the spread spectrum technique is used, notably the CDMA networks.
  • the present invention proposes to simplify to a large extent the synchronization of the receiving stations and to render the synchronization sequences by pilot signal unnecessary.
  • such a station is characterized in that said synchronization circuit comprises: a measuring circuit for measuring the energy of the transmitted signal, a first integration circuit for integrating this energy measurement, - a second integration circuit for integrating the output signal of the first integration circuit, a threshold circuit for producing a start-of-received-symbol signal based on the output signal of the second integration circuit.
  • Fig. 1 represents the diagram of a transmission system comprising a station in accordance with the invention
  • Fig. 2 represents the diagram of an adapted filter co-operating with a differential demodulator
  • Fig. 3 represents the cascade assembly of the two integrators according to the invention
  • Fig. 4 shows the shape of the signals on the input of the first integrator
  • Fig. 5 shows the shape of the signals on the output of this first integrator
  • Fig. 6 shows the shape of the signals on the output of the second integrator
  • Fig. 7 shows a diagram of a processing circuit for establishing the synchronization.
  • Fig. 1 represents a transmission system comprising a first station 1 in accordance with the invention communicating with a second station 2.
  • the stations 1 and 2 comprise a transmitting part 11 and 12 and a receiving part 14 and 15 respectively.
  • Interest particularly goes to the link established by the transmitting part 11 and the receiving part 15.
  • This link transmits symbols and uses three paths Tl, T2, and T3, for example.
  • Each symbol is formed by one binary element or a group of binary elements interrupted by a spread spectrum code CS formed by chips.
  • This code is generated by a code generator 21 at the transmitting end.
  • This same code CS is represented in the receiving part 15 by a filter 22 adapted to this code, arranged at the output of the first stages 23 of this receiving part.
  • This filter 22 is followed by a differential demodulator 25.
  • the adapted filter 22 is formed by two transversal filters 30 and 31 of which each one is assigned to the paths I and Q relating to the in-phase and quadrature phase data respectively, which come from the first stages 23. Only the filter 30 is shown in detail. It comprises a cascade of delay elements 32a, 32b, 32c ... each bringing about a delay equal to one chip period. The various delay elements are multiplied by coefficients C L - ⁇ , C L- , C L - 3 ... Co by means of multipliers 35a, 35b, 35c, ..., 35d. An adder 38 sums the various magnitudes of the outputs of the multipliers 35a, 35b, 35c, ... 35d.
  • the value of these coefficients represents the values of the spread-spectrum code CS.
  • the two filters produce in-phase signals x2I and quadrature signals x2Q which are applied to the differential demodulator 25 formed by a delay line 40 and 41 respectively, for causing a delay equal to one symbol period.
  • Two multipliers 45 and 46 respectively perform the multiplication of the delayed values by the value present on the inputs of the differential demodulator 25. The results produced by these multipliers are then added together by the adder 49 so as to produce the signal A which, for summarizing purposes, is written as:
  • A(n) x2I(n-N).x2I(n)+x2Q(n-N).x2Q(n)
  • "n" represents the current instant and "N” the length of the delay lines 40 and 41 equal to the length of the spreading code and thus to the duration of one symbol.
  • the synchronizing circuit comprises (Fig. 1): a first integration circuit 52 for integrating this energy measurement, a second integration circuit 54 for integrating the output signal of the first integration circuit, a threshold circuit 26 for producing a start-of-received-symbol signal based on the output signal of the second integration circuit.
  • the structure of the integrators 52 and 54 is shown in Fig. 3. These two integrators integrate the produced values with a value of the demodulator 25. Only the structure of integrator 52 is shown, because that of the integrator 54 may be identical.
  • the integrator 52 comprises an accumulator formed by an adder 60 and an accumulation memory 62. This integrator 52 can be re-initialized, the memory 62 is then set to zero under the control of a signal SY.
  • the signal SY is also used, but this re-initialization is effected with the output value of the first integrator, one active edge every two active edges of the signal SY.
  • the signal SY is processed by a processing circuit 58 (Fig. 1) to provide the synchronization.
  • Fig. 4 is shown the shape of the signals A on the output of the demodulator 25.
  • the configuration formed by the peaks PI, P2 and P3 described above, which is produced for a symbol SBl that has a first value, will be reproduced for the symbol SB2 that follows and has the same polarity, while it is admitted that the symbol SB2 has the same value as the symbol SBl.
  • FIG. 5 shows the signal B on the output of the first integrator 52 whose accumulator is reset to zero with each symbol period, as this has already been described above.
  • the signal C present on the output of the integrator 54 it is shown in Fig. 6.
  • the accumulator of this integrator 54 is reset to zero every second symbol period and between these two periods the contents of this accumulator are increased by the output value of the first integrator 52. It is thus noticed that a change of polarity of the peaks calls forth a change of the slope of the curve representing the signal C. This is indicated in Fig. 6 by reference BEG.
  • This signal is processed by the threshold circuit 56 (Fig. 1).
  • Fig. 7 shows the structure of the processing circuit 58.
  • This circuit is formed around a counter 80 counting the signals produced by a clock 81 down from D/2+In to -D/2+1.
  • the value In is the variable that permits the synchronization, as this will be explained in the following, and D is a function of the capacity of the counter and of the accuracy of the synchronization that one wishes to obtain.
  • the active synchronization signal SY appears when the contents of the counter cross zero. It is these contents that in fact prompt the validation of the symbols and thus authorize the re-initialization of the integrators.
  • the value Ibt of the counter is sent to the processing unit 90 while passing through a register 91.
  • Ibtt Ibt for 0> Ibt > -2b
  • Ibtt -2b for Ibt ⁇ -2b
  • b represents a stand-by period that is saved before the appearance of the first expected peak that marks the beginning of a symbol.
  • This value Ibtt may then be filtered into a magnitude Ibttf as a function of the previous filtered value Ibttf(-1) according to a formula of the type:
  • This value In is put in a register 95 to recharge the counter 80 at the end of its count-down cycle, that is to say, after it has reached D/2 - 1.

Abstract

This station comprises a system in which information is transmitted in the form of symbols appearing in symbol periods. The station comprises a receiving circuit in which a synchronizing circuit is provided for producing an indication of the start of a symbol. This synchronizing circuit comprises a measuring circuit for measuring the energy of the transmitted signal, a first integration circuit for integrating this energy measurement, a second integration circuit for integrating this energy measurement as a function of the output signal of the first integration circuit. Finally, a threshold circuit produces a start-of-received-symbol signal based on the output signal of the second integration circuit.

Description

METHOD FOR DETERMINING THE START OF A PULSE IN A SPREAD SPECTRUM SYSTEM
The invention relates to a station comprising a receiving circuit suitable for a system in which information is transmitted in the form of symbols, which receiving circuit includes a synchronization circuit for producing an indication of the start of a symbol.
The invention also relates to a synchronization method for determining the start of a symbol.
The invention finds its application in the industry for cellular radiotelephony networks in which the spread spectrum technique is used, notably the CDMA networks.
A problem posed with this type of system is the synchronization of the receivers. It is imperative that the symbols to be received be phase-adjusted to the local clock. Thus the start of the transmitted symbol is to be determined with much precision. On this subject one may consult United States patent no. 5,712,869. In this patent document the synchronization is obtained by means of a pilot signal.
The present invention proposes to simplify to a large extent the synchronization of the receiving stations and to render the synchronization sequences by pilot signal unnecessary.
Therefore, such a station is characterized in that said synchronization circuit comprises: a measuring circuit for measuring the energy of the transmitted signal, a first integration circuit for integrating this energy measurement, - a second integration circuit for integrating the output signal of the first integration circuit, a threshold circuit for producing a start-of-received-symbol signal based on the output signal of the second integration circuit.
These and other aspects of the invention are apparent from and will be elucidated, by way of non-limitative example, with reference to the embodiment(s) described hereinafter.
In the drawings:
Fig. 1 represents the diagram of a transmission system comprising a station in accordance with the invention, Fig. 2 represents the diagram of an adapted filter co-operating with a differential demodulator,
Fig. 3 represents the cascade assembly of the two integrators according to the invention,
Fig. 4 shows the shape of the signals on the input of the first integrator, Fig. 5 shows the shape of the signals on the output of this first integrator, Fig. 6 shows the shape of the signals on the output of the second integrator, and
Fig. 7 shows a diagram of a processing circuit for establishing the synchronization.
Fig. 1 represents a transmission system comprising a first station 1 in accordance with the invention communicating with a second station 2. The stations 1 and 2 comprise a transmitting part 11 and 12 and a receiving part 14 and 15 respectively. Interest particularly goes to the link established by the transmitting part 11 and the receiving part 15. This link transmits symbols and uses three paths Tl, T2, and T3, for example. Each symbol is formed by one binary element or a group of binary elements interrupted by a spread spectrum code CS formed by chips. This code is generated by a code generator 21 at the transmitting end. This same code CS is represented in the receiving part 15 by a filter 22 adapted to this code, arranged at the output of the first stages 23 of this receiving part. This filter 22 is followed by a differential demodulator 25. In the following articles, observations about these elements 22 and 25 will be found:
"Introduct on to Spread-Spectrum Antimultipath Techniques and their Application to Urban Digital Radio", whose author is G.L. TURIN, which article was published in March 1980 in Proceedings of IEEE, vol. 68, no. 3, pp. 328 to 353. - "An Integrated All Digital Diversity Receiver for Spread Spectrum
Communications over Multipath Fading Channels", whose author is C. MOULEC et al., which article was published in VTC 1994, pp. 367 to 370.
In Fig. 2 is recalled the structure of these elements. The adapted filter 22 is formed by two transversal filters 30 and 31 of which each one is assigned to the paths I and Q relating to the in-phase and quadrature phase data respectively, which come from the first stages 23. Only the filter 30 is shown in detail. It comprises a cascade of delay elements 32a, 32b, 32c ... each bringing about a delay equal to one chip period. The various delay elements are multiplied by coefficients CL-ι, CL- , CL-3 ... Co by means of multipliers 35a, 35b, 35c, ..., 35d. An adder 38 sums the various magnitudes of the outputs of the multipliers 35a, 35b, 35c, ... 35d. The value of these coefficients represents the values of the spread-spectrum code CS. The two filters produce in-phase signals x2I and quadrature signals x2Q which are applied to the differential demodulator 25 formed by a delay line 40 and 41 respectively, for causing a delay equal to one symbol period. Two multipliers 45 and 46 respectively, perform the multiplication of the delayed values by the value present on the inputs of the differential demodulator 25. The results produced by these multipliers are then added together by the adder 49 so as to produce the signal A which, for summarizing purposes, is written as:
A(n) = x2I(n-N).x2I(n)+x2Q(n-N).x2Q(n) In this formula, "n" represents the current instant and "N" the length of the delay lines 40 and 41 equal to the length of the spreading code and thus to the duration of one symbol. Based on the data produced by the demodulator 25, and after processing, the useful data are created in a user circuit 26.
As a result of the multiple paths Tl, T2, T3 ... and other disturbances, it is hard to synchronize on reception the received data with the locally generated spreading code. To facilitate the synchronization, the synchronizing circuit comprises (Fig. 1): a first integration circuit 52 for integrating this energy measurement, a second integration circuit 54 for integrating the output signal of the first integration circuit, a threshold circuit 26 for producing a start-of-received-symbol signal based on the output signal of the second integration circuit.
Thus, based on this start-of-pulse signal it becomes possible to ensure the synchronization of the receiver by utilizing a processing circuit 58.
The structure of the integrators 52 and 54 is shown in Fig. 3. These two integrators integrate the produced values with a value of the demodulator 25. Only the structure of integrator 52 is shown, because that of the integrator 54 may be identical. The integrator 52 comprises an accumulator formed by an adder 60 and an accumulation memory 62. This integrator 52 can be re-initialized, the memory 62 is then set to zero under the control of a signal SY. For re-initializing the integrator 54, the signal SY is also used, but this re-initialization is effected with the output value of the first integrator, one active edge every two active edges of the signal SY. The signal SY is processed by a processing circuit 58 (Fig. 1) to provide the synchronization.
In Fig. 4 is shown the shape of the signals A on the output of the demodulator 25. Each path Tl, T2, and T3 respectively, gives a correlation peak PI , P2 and P3. It is admitted that the propagation parameters do not change too fast. The configuration formed by the peaks PI, P2 and P3 described above, which is produced for a symbol SBl that has a first value, will be reproduced for the symbol SB2 that follows and has the same polarity, while it is admitted that the symbol SB2 has the same value as the symbol SBl. As the symbol SB3 that follows has a different value, there is thus a negative peak configuration. Fig. 5 shows the signal B on the output of the first integrator 52 whose accumulator is reset to zero with each symbol period, as this has already been described above. As regards the signal C present on the output of the integrator 54, it is shown in Fig. 6. The accumulator of this integrator 54 is reset to zero every second symbol period and between these two periods the contents of this accumulator are increased by the output value of the first integrator 52. It is thus noticed that a change of polarity of the peaks calls forth a change of the slope of the curve representing the signal C. This is indicated in Fig. 6 by reference BEG. This signal is processed by the threshold circuit 56 (Fig. 1).
Fig. 7 shows the structure of the processing circuit 58. This circuit is formed around a counter 80 counting the signals produced by a clock 81 down from D/2+In to -D/2+1. The value In is the variable that permits the synchronization, as this will be explained in the following, and D is a function of the capacity of the counter and of the accuracy of the synchronization that one wishes to obtain. The active synchronization signal SY appears when the contents of the counter cross zero. It is these contents that in fact prompt the validation of the symbols and thus authorize the re-initialization of the integrators. When a change of slope BEG is detected, the value Ibt of the counter is sent to the processing unit 90 while passing through a register 91. This unit in a first step determines a value Ibtt so that: ibtt = 0 for Ibt > 0
Ibtt = Ibt for 0> Ibt > -2b
Ibtt = -2b for Ibt < -2b where b represents a stand-by period that is saved before the appearance of the first expected peak that marks the beginning of a symbol.
This value Ibtt may then be filtered into a magnitude Ibttf as a function of the previous filtered value Ibttf(-1) according to a formula of the type:
Ibttf = Ibtt.α+(l-α)Ibttf(-l) where α is a filter constant lower than 1. Then the value In is calculated, which is the correction value to be taken to the down-counter: ibttfer _ In = +r where T is a value that is comparable to the gain of the loop that is formed by the synchronization.
If the filtering is not used, In may have the following values:
This value In is put in a register 95 to recharge the counter 80 at the end of its count-down cycle, that is to say, after it has reached D/2 - 1.

Claims

CLAIMS:
1. A station comprising a receiving circuit suitable for a system in which information is transmitted in the form of symbols appearing in symbol periods, in which receiving circuit is provided a synchronizing circuit for producing an indication of the start of a symbol, characterized in that said synchronizing circuit comprises: - a measuring circuit for measuring the energy of the transmitted signal, a first integration circuit for integrating this energy measurement, a second integration circuit for integrating this energy measurement as a function of the output signal of the first integration circuit, a threshold circuit for producing a start-of-received-symbol signal based on the output signal of the second integration circuit.
2. A station as claimed in claim 1, characterized in that the threshold circuit detects a change of slope.
3. A station as claimed in claim 1 or 2, characterized in that the first integration circuit is reset to zero every symbol period.
4. A station as claimed in claim 1 or 2, characterized in that the second integration circuit is reset to zero at least every second symbol period and between these resets to zero is recharged with the output value of the first integration circuit.
5. A method of determining the start of a symbol-defining pulse, utilized in a station as claimed in one of the claims 1 to 4, characterized in that it comprises the following steps: - measuring the received energy of the signal transmitting a pulse, a first integration of this energy during a symbol period, a second integration of this energy during at least two symbol periods, determining the start of the pulse by detecting a change of slope of the output signal, obtained via the second integration.
6. A method as claimed in claim 5, characterized in that it comprises a reinitialization step for re-initializing the first integration periodically and for re-initializing the second integration of the value of this first integration in different periods of the re- initialization of the first integration.
7. A transmission system comprising a station as claimed in one of the claims 1 to 4.
EP00931164A 1999-05-04 2000-05-01 Method for determining the start of a pulse in a spread spectrum system Withdrawn EP1095466A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP00931164A EP1095466A1 (en) 1999-05-04 2000-05-01 Method for determining the start of a pulse in a spread spectrum system

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
EP99401088 1999-05-04
EP99401088 1999-05-04
EP00931164A EP1095466A1 (en) 1999-05-04 2000-05-01 Method for determining the start of a pulse in a spread spectrum system
PCT/EP2000/004189 WO2000067387A1 (en) 1999-05-04 2000-05-01 Method for determining the start of a pulse in a spread spectrum system

Publications (1)

Publication Number Publication Date
EP1095466A1 true EP1095466A1 (en) 2001-05-02

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EP00931164A Withdrawn EP1095466A1 (en) 1999-05-04 2000-05-01 Method for determining the start of a pulse in a spread spectrum system

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EP (1) EP1095466A1 (en)
JP (1) JP2002543734A (en)
KR (1) KR20010053361A (en)
CN (1) CN1302483A (en)
TW (1) TW503630B (en)
WO (1) WO2000067387A1 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SG121741A1 (en) * 2002-10-30 2006-05-26 Stmicooelectronics Asia Pacifi Method and apparatus for a control signal generating circuit
TWI314115B (en) 2007-09-27 2009-09-01 Ind Tech Res Inst Method and apparatus for predicting/alarming the moving of hidden objects
CN102468865A (en) * 2010-11-18 2012-05-23 中兴通讯股份有限公司 Method and device of cell search coarse synchronization

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Publication number Priority date Publication date Assignee Title
US5499273A (en) * 1995-05-11 1996-03-12 Motorola, Inc. Method and apparatus for symbol clock recovery from signal having wide frequency possibilities
US5627855A (en) * 1995-05-25 1997-05-06 Golden Bridge Technology, Inc. Programmable two-part matched filter for spread spectrum

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO0067387A1 *

Also Published As

Publication number Publication date
JP2002543734A (en) 2002-12-17
CN1302483A (en) 2001-07-04
WO2000067387A1 (en) 2000-11-09
TW503630B (en) 2002-09-21
KR20010053361A (en) 2001-06-25

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