EP1060512A1 - Vertically integrated circuit system - Google Patents

Vertically integrated circuit system

Info

Publication number
EP1060512A1
EP1060512A1 EP99964450A EP99964450A EP1060512A1 EP 1060512 A1 EP1060512 A1 EP 1060512A1 EP 99964450 A EP99964450 A EP 99964450A EP 99964450 A EP99964450 A EP 99964450A EP 1060512 A1 EP1060512 A1 EP 1060512A1
Authority
EP
European Patent Office
Prior art keywords
integrated circuit
circuits
control device
vertically integrated
integrated circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP99964450A
Other languages
German (de)
French (fr)
Inventor
Martin Bader
Michael Smola
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1060512A1 publication Critical patent/EP1060512A1/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/74—Masking faults in memories by using spares or by reconfiguring using duplex memories, i.e. using dual copies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H01L23/556—Protection against radiation, e.g. light or electromagnetic waves against alpha rays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the invention relates to a vertically integrated circuit arrangement according to claim 1.
  • Such external interference can be triggered, for example, by quantum mechanically detectable particles.
  • the likelihood of such "impacts” caused by external influences increases in particular to the extent that the semiconductor structures, as is customary in space technology, leave the protective earth atmosphere.
  • Electronic circuits are therefore usually covered with gold and silver foils in these applications to cause at least some absorption of the above particles.
  • the invention is therefore based on the task of integrated
  • control device determines a statistical result of redundant functionalities.
  • At least two integrated circuits are provided according to the invention, which are formed on two semiconductor chips 1 and 2 lying one above the other.
  • the semiconductor chips 1 and 2 have an active zone la or 2a on one of their surfaces, in which the integrated circuits are formed using conventional technology. So that the arrangement shown can work as a whole as a vertically integrated circuit arrangement, contacts are provided which are shown only once in the figure by way of example, but are to be formed in the necessary number.
  • the active areas 1 a and 2 a have contact points 1 b and 2 b lying one above the other.
  • a through opening 7 is formed in the semiconductor chip 1, which opening is filled with a conductive material 6 and in this way connects the contacts 1b and 2b to one another.
  • the two semiconductor chips 1 and 2 now have largely identical functionality in their respective active regions 1 a and 2 a. This is in the form of an integrated circuit.
  • a control device is additionally provided in at least one of the active regions of the two semiconductor chips. This controls the cooperation between the two integrated circuits in the two semiconductor chips 1 and 2.
  • the first procedure is described below. For example, find data processing processes in both semi- terchips, which have identical functionality as described above, take place in parallel, the control device determines a statistical result from the two processes running in parallel. This is more likely if you assume a random interference from particle bombardment.
  • the probability is additionally increased by more than two semiconductor chips lying one on top of the other.
  • control device which is not shown in detail but is arranged as an integrated circuit in one of the active regions la or 2a of the first or second semiconductor chips 1 or 2, distributes the work of the further integrated circuits with the same functionality according to a specific procedure. Since the functionality of the two is the same, a circuit analysis cannot determine the manner in which processes take place on the semiconductor chip 1 or on the semiconductor chip 2. Rather, seen that the control device can carry out data processing, for example, on the semiconductor chip 1 or on the semiconductor chip 2 by means of a random control.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Storage Device Security (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

The invention relates to a vertically integrated circuit system comprising at least one first integrated circuit and a second integrated circuit which are positioned on top of each other, identical functionalities being configured on the two integrated circuits. At least one of the integrated circuits is provided with a control device which controls the cooperation of the circuits with identical functionalities.

Description

Beschreibungdescription
Vertikal integrierte SchaltungsanordnungVertically integrated circuit arrangement
Die Erfindung betrifft eine vertikal integrierte Schaltungsanordnung gemäß Patentanspruch 1.The invention relates to a vertically integrated circuit arrangement according to claim 1.
Moderne Herstellungsverfahren in der Halbleitertechnik und neuartige Technologien führen fortlaufend zu einer Miniaturi- sierung der damit erzeugten Strukturen. Die Miniaturisierung basiert dabei größtenteils auf einer Verkleinerung der Kanal- breiten von MOS-Transistoren, so daß die für ein Bauelement benötigte Fläche quadratisch abnimmt. Derzeit werden bereits Strukturen mit 0,35 μm Kanalbreite und kleiner (0,25 mm) er- reicht. Es ist jedoch bereits absehbar, daß Strukturen in einer Größenordnung von 0,1 μm angewendet werden.Modern manufacturing processes in semiconductor technology and new technologies continuously lead to a miniaturization of the structures created with them. The miniaturization is largely based on a reduction in the channel widths of MOS transistors, so that the area required for a component decreases quadratically. Structures with a channel width of 0.35 μm and smaller (0.25 mm) are currently being achieved. However, it is already foreseeable that structures on the order of 0.1 μm will be used.
Mit immer kleiner werdenden Halbleiterstrukturen nimmt expo- nentiell zur Miniaturisierung die Gefahr der Einwirkung von Fremdstörung zu. Derartige Fremdstörungen können beispielsweise durch quantenmechanisch erfaßbare Teilchen ausgelöst werden.With semiconductor structures getting smaller and smaller, the risk of external interference increases exponentially for miniaturization. Such external interference can be triggered, for example, by quantum mechanically detectable particles.
Die Teilchen durchdringen die Gehäuse die die integrierten Schaltungsanordnungen auf sogenannten Halbleiterchips umgeben und führen nicht nur zur Beschädigung der drauf ausgebildeten Halbleiterstrukturen, sondern auch zur Generation von Elektronen oder zur Absorption von Elektronen. Hierdurch kann ein dauerhaftes oder zwischenzeitliches Fehlfunktionieren der Halbleiterstrukturen ausgelöst werden. Die Wahrscheinlichkeit derartiger durch Fremdeinwirkung bewirkten „Einschläge" nimmt insbesondere in dem Maße zu, daß die Halbleiterstrukturen, wie es bei der Raumfahrttechnik üblich ist die schützende Erdatmosphäre verlassen. Bei diesen Anwendungen werden elek- tronische Schaltungen daher in der Regel mit Gold- und Silberfolien ummantelt, um zumindest eine gewisse Absorption der oben genannten Teilchen zu bewirken. Mit zunehmender Miniaturisierung kann dabei jedoch nicht verhindert werden, daß auch die zuvor erwähnte Ummantelung mit Gold- und Silberfolie keinen ausreichenden Schutz gewährlei- sten, so daß die Gefahr durch die zuvor geschriebenen „Einschläge" beziehungsweise Störwirkungen zunehmen. Diese Gefahr gewinnt auch bei der üblichen terrestrischen Anwendung zunehmend an Bedeutung.The particles penetrate the housing which surround the integrated circuit arrangements on so-called semiconductor chips and lead not only to damage to the semiconductor structures formed thereon, but also to the generation of electrons or to the absorption of electrons. This can trigger a permanent or intermittent malfunction of the semiconductor structures. The likelihood of such "impacts" caused by external influences increases in particular to the extent that the semiconductor structures, as is customary in space technology, leave the protective earth atmosphere. Electronic circuits are therefore usually covered with gold and silver foils in these applications to cause at least some absorption of the above particles. However, with increasing miniaturization, it cannot be prevented that the above-mentioned sheathing with gold and silver foil does not guarantee adequate protection, so that the risk from the previously described "impacts" or disturbing effects increases. This risk also increases with the usual terrestrial application is becoming increasingly important.
Der Erfindung liegt somit die Aufgabe zugrunde, integrierteThe invention is therefore based on the task of integrated
Schaltungsanordnungen vorzusehen, die auch bei Anwendungen in der Raumfahrttechnik einen sicheren Betrieb gewährleisten.To provide circuit arrangements that ensure safe operation even in applications in space technology.
Diese Aufgabe wird erfindungsgemäß durch eine Anordnung gemäß Patentanspruch 1 gelöst.This object is achieved by an arrangement according to claim 1.
Dadurch, daß eine vertikal integrierte Schaltungsanordnung wie angegeben vorgesehen ist, ist durch die identische Funktionalität auf zumindest zwei übereinanderliegenden inte- grierten Schaltungen, und einer Steuereinrichtung die zurDue to the fact that a vertically integrated circuit arrangement is provided as indicated, the identical functionality on at least two integrated circuits lying one above the other and a control device means that
Verfügung stehende Redundanz für einen sicheren Betrieb ausnutzt ein Betrieb mit erhöhter Sicherheit gewährleistet.Redundancy available for safe operation takes advantage of operation with increased safety.
In einer vorteilhaften Weiterbildung, wie sie im Anspruch 2 angegeben ist, wird dies dadurch unterstützt, daß die Steuereinrichtung ein statistisches Ergebnis redundanter Funktionalitäten ermittelt. Durch die zuvor beschriebene Anordnung ist es möglich sicherheitsrelevante Vorgänge der Datenverarbeitung mittels der Steuereinrichtung zufällig oder gezielt auf die übereinanderliegende integrierten Schaltungen zu verteilen, so daß ein unerlaubter Zugriff auf sicherheitsrelevante Daten beziehungsweise Vorgänge verhindert ist.In an advantageous development, as specified in claim 2, this is supported in that the control device determines a statistical result of redundant functionalities. The arrangement described above makes it possible to randomly or specifically distribute security-related data processing operations by means of the control device to the superimposed integrated circuits, so that unauthorized access to security-relevant data or operations is prevented.
Nachfolgend wird die Erfindung anhand eines Ausführungsbei- spiels unter Bezugnahme auf die Figur im Einzelnen erläutert.The invention is explained in detail below using an exemplary embodiment with reference to the figure.
Es zeigen: In der Figur ist ein erfindungsgemäßes Ausführungsbeispiel schematisch im Querschnitt dargestellt.Show it: In the figure, an embodiment of the invention is shown schematically in cross section.
Wie in der Figur dargestellt ist, sind erfindungsgemäß zumindest zwei integrierte Schaltungen vorgesehen, die auf zwei übereinanderliegenden Halbleiterchips 1 und 2 ausgebildet sind. Die Halbleiterchips 1 und 2 weisen an einer ihrer Oberflächen eine aktive Zone la beziehungsweise 2a auf, in denen die integrierten Schaltungen in einer üblichen Technologie ausgebildet sind. Damit die dargestellte Anordnung insgesamt als vertikal integrierte Schaltungsanordnung arbeiten kann, sind Kontakte vorgesehen, die exemplarisch in der Figur nur einmal dargestellt sind, jedoch in der notwendigen Anzahl auszubilden sind. Hierbei weisen die aktiven Bereiche la beziehungsweise 2a übereinanderliegende Kontaktstellen lb beziehungsweise 2b auf. Im Halbleiterchip 1 ist eine Durch- gangsδffnung 7 ausgebildet, die durch ein leitendes Material 6 ausgefüllt ist und auf diese Weise die Kontakte lb und 2b miteinander verbinden.As shown in the figure, at least two integrated circuits are provided according to the invention, which are formed on two semiconductor chips 1 and 2 lying one above the other. The semiconductor chips 1 and 2 have an active zone la or 2a on one of their surfaces, in which the integrated circuits are formed using conventional technology. So that the arrangement shown can work as a whole as a vertically integrated circuit arrangement, contacts are provided which are shown only once in the figure by way of example, but are to be formed in the necessary number. Here, the active areas 1 a and 2 a have contact points 1 b and 2 b lying one above the other. A through opening 7 is formed in the semiconductor chip 1, which opening is filled with a conductive material 6 and in this way connects the contacts 1b and 2b to one another.
Nunmehr weisen die beiden Halbleiterchips 1 und 2 in ihren jeweiligen aktiven Bereichen la beziehungsweise 2a eine weitgehende identische Funktionalität auf. Diese ist in Form ei- ner integrierten Schaltung jeweils ausgebildet.The two semiconductor chips 1 and 2 now have largely identical functionality in their respective active regions 1 a and 2 a. This is in the form of an integrated circuit.
In zumindest einem der aktiven Bereiche der beiden Halbleiterchips ist zusätzlich eine nicht dargestellte Steuereinrichtung vorgesehen. Diese steuert die Zusammenarbeit zwi- sehen den beiden integrierten Schaltungen in den beiden Halbleiterchips 1 und 2.A control device, not shown, is additionally provided in at least one of the active regions of the two semiconductor chips. This controls the cooperation between the two integrated circuits in the two semiconductor chips 1 and 2.
Es gibt hierbei zwei grundsätzlich unterschiedliche Vorgehensweisen, die jedoch auch miteinander kombinierbar sind.There are two fundamentally different procedures here, but they can also be combined with one another.
Nachfolgend wird die erste Vorgehensweise beschrieben. Finden beispielsweise Datenverarbeitungsprozesse in beiden Halblei- terchips, die wie zuvor beschrieben identische Funktionalität aufweisen, parallel statt, so ermittelt die Steuereinrichtung aus den beiden jeweils parallel laufenden Prozessen ein statistisches Ergebnis. Dieses hat, wenn man von einer zufälligen Störung durch Teilchenbeschuß ausgeht, eine höhere Wahrscheinlichkeit .The first procedure is described below. For example, find data processing processes in both semi- terchips, which have identical functionality as described above, take place in parallel, the control device determines a statistical result from the two processes running in parallel. This is more likely if you assume a random interference from particle bombardment.
Erhöht wird die Wahrscheinlichkeit zusätzlich durch mehr als zwei übereinander!iegenden Halbleiterchips.The probability is additionally increased by more than two semiconductor chips lying one on top of the other.
Da wie zuvor erläutert die Beeinträchtigung elektronischer Schaltung durch Teilchenbeschuß auch auf der Erde im höheren Maße an Bedeutung gewinnen, kann man die beschriebene Anordnung sinnvollerweise auch für den Einsatz in sicherheitsrele- vanten Schaltungen verwenden. Diese finden als spezielle Bausteine beispielsweise in sogenannten „Chip-Cards" beziehungsweise „Smart-Cards" oder auch als Bausteine in Lesegeräten für die zuvor erwähnten Anordnungen Verwendung. Bei diesen Anwendungen sind im zunehmenden Maße sicherheitsrelevante Da- ten, wie beispielsweise Schlüsselwörter vor dem unerlaubtenSince, as explained above, the impairment of electronic circuitry by particle bombardment is also gaining in importance to a greater extent on earth, the arrangement described can usefully also be used for use in safety-relevant circuits. These are used as special building blocks, for example in so-called “chip cards” or “smart cards”, or also as building blocks in reading devices for the aforementioned arrangements. In these applications, security-relevant data, such as keywords before the unauthorized, are becoming increasingly important
Zugriff zu schützen. Dies kann dadurch erfolgen, daß die Verarbeitung beziehungsweise die Verwendung dieser Sicherheits- relevanten Daten nur auf einem Halbleiterchip stattfindet, der durch einen anderen abgedeckt ist . Dies erfolgt gemäß der Figur dadurch, daß sicherheitsrelevante Daten auf dem Halbleiterchip 2 allein bearbeitet werden.Protect access. This can be done in that the processing or use of this security-relevant data only takes place on a semiconductor chip which is covered by another. According to the figure, this is done by processing security-relevant data on the semiconductor chip 2 alone.
Weiterhin ist vorgesehen, daß die nicht im einzelnen dargestellte aber als integrierte Schaltung in einer der aktiven Bereiche la beziehungsweise 2a des ersten beziehungsweise zweiten Halbleiterchips 1 beziehungsweise 2 angeordnete Steuereinrichtung die Arbeit der weiteren integrierten Schaltungen mit gleicher Funktionalität nach einer bestimmten Vorgehensweise verteilt. Da die Funktionalität beider gleich ist, kann durch eine Schaltungsanalyse nicht ermittelt werden, in welcher Weise Vorgänge auf dem Halbleiterchip 1 beziehungsweise auf dem Halbleiterchip 2 stattfinden. Vielmehr ist vor- gesehen, daß die Steuereinrichtung durch eine Zufallssteuerung Datenverarbeitung beispielsweise auf den Halbleiterchip 1 beziehungsweise auf den Halbleiterchip 2 durchführen läßt.Furthermore, it is provided that the control device, which is not shown in detail but is arranged as an integrated circuit in one of the active regions la or 2a of the first or second semiconductor chips 1 or 2, distributes the work of the further integrated circuits with the same functionality according to a specific procedure. Since the functionality of the two is the same, a circuit analysis cannot determine the manner in which processes take place on the semiconductor chip 1 or on the semiconductor chip 2. Rather, seen that the control device can carry out data processing, for example, on the semiconductor chip 1 or on the semiconductor chip 2 by means of a random control.
Da auf diese Weise nicht vorhersehbar ist, in welcher der integrierten Schaltungen bestimmte Vorgänge ablaufen, ist die Analyse der verarbeitenden Daten stark erschwert . Since it is not possible in this way to predict in which of the integrated circuits certain processes will take place, the analysis of the processing data is very difficult.

Claims

Patentansprüche claims
1. Vertikal integrierte Schaltungsanordnung mit zumindest einer ersten integrierten Schaltung (1, la) und einer zweiten integrierten Schaltung (2, 2a), die übereinanderliegend angeordnet sind, wobei in beiden integrierten Schaltungen eine identisches Funktionalität ausgebildet ist und wobei zumindest in einer der integrierten Schaltungen eine Steuereinrichtung vorgesehen ist, die ein Zusammenarbeiten der Schal- tungen mit identischer Funktionalität steuert.1. Vertically integrated circuit arrangement with at least a first integrated circuit (1, la) and a second integrated circuit (2, 2a), which are arranged one above the other, with identical functionality being formed in both integrated circuits and with at least one of the integrated circuits a control device is provided which controls the cooperation of the circuits with identical functionality.
2. Vertikal integrierte Schaltungsanordnung nach Anspruch 1, bei der zumindest ein Teil der identischen Funktionalität gleichzeitig betrieben wird und von der Steuereinrichtung ein statistisches Ergebnis ermittelt wird.2. Vertically integrated circuit arrangement according to claim 1, in which at least part of the identical functionality is operated simultaneously and a statistical result is determined by the control device.
3. Vertikal integrierte Schaltungsanordnung nach einem der vorgehenden Ansprüche, bei der die integrierten Schaltungen zur Datenverarbeitung ausgebildet sind und sicherheitsrele- vante Daten nur in der integrierten Schaltung verarbeitet werden, auf der eine weitere integrierte Schaltung aufliegt. 3. Vertically integrated circuit arrangement according to one of the preceding claims, in which the integrated circuits are designed for data processing and safety-relevant data are only processed in the integrated circuit on which a further integrated circuit rests.
EP99964450A 1998-12-30 1999-12-21 Vertically integrated circuit system Withdrawn EP1060512A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19860817 1998-12-30
DE19860817 1998-12-30
PCT/DE1999/004055 WO2000041240A1 (en) 1998-12-30 1999-12-21 Vertically integrated circuit system

Publications (1)

Publication Number Publication Date
EP1060512A1 true EP1060512A1 (en) 2000-12-20

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EP (1) EP1060512A1 (en)
JP (1) JP2002534808A (en)
KR (1) KR20010083778A (en)
CN (1) CN1292151A (en)
BR (1) BR9908393A (en)
WO (1) WO2000041240A1 (en)

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Publication number Priority date Publication date Assignee Title
US10958451B2 (en) 2014-04-09 2021-03-23 Ictk Holdings Co., Ltd. Authentication apparatus and method

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Publication number Priority date Publication date Assignee Title
JPS5588356A (en) * 1978-12-27 1980-07-04 Hitachi Ltd Semiconductor device
KR900008647B1 (en) * 1986-03-20 1990-11-26 후지쓰 가부시끼가이샤 A method for manufacturing three demensional i.c.
EP0454447A3 (en) * 1990-04-26 1993-12-08 Hitachi Ltd Semiconductor device assembly
EP0695494B1 (en) * 1993-04-23 2001-02-14 Irvine Sensors Corporation Electronic module comprising a stack of ic chips
EP0732107A3 (en) * 1995-03-16 1997-05-07 Toshiba Kk Circuit substrate shielding device
US5824571A (en) * 1995-12-20 1998-10-20 Intel Corporation Multi-layered contacting for securing integrated circuits

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Title
See references of WO0041240A1 *

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Publication number Publication date
BR9908393A (en) 2000-10-31
CN1292151A (en) 2001-04-18
KR20010083778A (en) 2001-09-01
JP2002534808A (en) 2002-10-15
WO2000041240A1 (en) 2000-07-13

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