EP1051877A1

EP1051877A1 - Multiple-channel subscriber line card

Info

Publication number: EP1051877A1
Application number: EP99904201A
Authority: EP
Inventors: William M. Plummer; Rudolph B. Klecka, Iii
Original assignee: Alcatel USA Sourcing Inc
Current assignee: Alcatel USA Sourcing Inc
Priority date: 1998-01-27
Filing date: 1999-01-21
Publication date: 2000-11-15
Also published as: AU2465199A; JP2002502167A; TW407414B; WO1999038352A1

Abstract

A telecommunications channel unit card including a subscriber bus interface for communicating subscriber bus signals with a digital loop carrier matrix, a mapping circuit for mapping between subscriber bus signals and wideband telecommunications signals, a plurality of spans for communicating wideband telecommunications signals with an external network, and a processor node for controlling operation of the mapping circuit and the plurality of span interfaces.

Description

- 1 - MULTIPLE-CHANNEL SUBSCRIBER LINE CARD

Background This invention is related to multiple-channel subscriber line card used in telecommunications. In the early days of telecommunications, a copper wire was used to carry a single information channel. Because the large majority of cost is in the materials and construction of the physical link, telephony engineers since have developed ways to pack multiple communications channels onto a single physical link. Frequency division multiplexing (FDM) and time division multiplexing (TDM) have been devised to multiplex multiple streams of analog and pulse code modulation (PCM) digital signals, respectively, into a single stream. For digital signals, the time division multiplexing hierarchy is represented as DSO (Digital Signal) through DS4, where a DSO is a single 0.064 Mb/s channel, a DS1 is 24 DSOs multiplexed together, a DS2 is 96 DSOs multiplexed together, a DS3 is 672 DSOs multiplexed together, and a DS4 is 4,032 DSOs multiplexed together. The hierarchy DS1 through DS4 also is referred to as Tl, T2, T3, and T4 when using a copper medium for transmission.

A similar time division multiplexing scheme, based on International Telecommunication Union CCITT's G.700 Series Recommendations, uses a 32- channel format referred to as El, or CEPT-1, where each channel corresponds to a DSO (0.064 Mb/s) signal. Thus, a El signal is based on 32 DSOs multiplexed together, a E2 is 128 DSOs multiplexed together, a E3 is 512 DSOs multiplexed together, and a E4 is 2,048 DSOs multiplexed together.

A digital loop carrier (DLC) at a central terminal (CT) is a multiplexor which can multiplex multiple analog and digital signals from subscriber telephone lines into a single multiple digital signal such as a Tl/El signal. A mirror DLC located at a remote terminal (RT) can decode the multiplexed Tl/El signal into a form suitable for transmission over subscriber telephone lines. This data flow also occurs in the opposite direction from RT to CT. Each DLC essentially is a special purpose computer containing standard control, memory, power, etc. components but also a number of interface cards (line cards) for converting analog and digital signals from subscriber telephone lines into formatted digital data signals. Different types of interface cards service different types of subscriber telephone lines. Examples of interface cards include POTS (Plain Old Telephone Service) cards for analog telephone lines, FOX cards for fiber optic lines, ISDN (Integrated Services Digital Network) cards for ISDN lines, and a number of other wideband service option cards. After the appropriate interface cards convert the subscriber telephone line signals into formatted digital data signals, a DLC at a central terminal constructs a single El signal by means of time division multiplexing. At a remote terminal, the DLC decodes the El signal to deliver formatted digital data back to the interface cards. Interface cards convert the formatted digital data into a form suitable for transmission over subscriber telephone lines. The most mature technology for transmitting over these lines (e.g, standard unshielded twisted pair) is HDSL. HDSL, which involves special electronics at both the central office and the customer premise, allows the provisioning of Tl/El local loop circuits much more quickly and at a much lower cost than through conventional means.

Summary In general, in various implementations, the invention may include one or more of the following features. A multiple-channel subscriber line card includes a subscriber bus interface for communicating subscriber bus signals with a digital loop carrier matrix, a mapping circuit for mapping between subscriber bus signals and wideband telecommunications signals, a plurality of spans for communicating wideband telecommumcations signals with an external network, and a processor node for controlling operation of the mapping circuit and the plurality of span interfaces.

The spans can recover the wideband telecommunications signals from incoming signals received from the external network. The spans can perform framing and formatting functions for wideband telecommunications signals to be sent over the external network.

The mapping circuit can map inbound wideband telecommunications signals into subscriber bus signals using a plurality of odd and even channels. In general, in another aspect, the mapping circuit also can map inbound wideband telecommunications signals into subscriber bus signals by combining up to three even channels and by preserving corresponding odd channels.

The mapping circuit can map outbound subscriber bus signals into wideband telecommunications signals by separating one even channel and by preserving corresponding odd channels.

The mapping circuit can be implemented as an application-specific integrated circuit (ASIC).

The wideband telecommunications signals can comprise El or Tl signals. The digital loop carrier matrix can comprise a bandwidth, processor and timing (BPT) card.

In general, in another aspect, a telecommunications channel unit card comprise first communicating means for communicating subscriber bus signals with a digital loop carrier matrix, means for mapping between subscriber bus signals and wideband telecommunications signals, second communicating means for communicating wideband telecommumcations signals with an external network, and means for controlling operation of the mapping means and the first and second communicating means.

The second communicating means can recover the wideband telecommunications signals from incoming signals received from the external network.

The second communicating means can perform framing and formatting functions for wideband telecommunications signals to be sent over the external network. - 4 -

The mapping means can map inbound wideband telecommunications signals into subscriber bus signals using a plurality of odd and even channels.

The mapping means can map inbound wideband telecommunications signals into subscriber bus signals by combining up to three even channels and by preserving corresponding odd channels.

The mapping means can map outbound subscriber bus signals into wideband telecommunications signals by separating one even channel and by preserving corresponding odd channels.

The mapping means can be implemented as an application-specific integrated circuit (ASIC).

The wideband telecommunications signals can comprise El or Tl signals.

The digital loop carrier matrix can comprise a bandwidth, processor and timing (BPT) card. In general in another aspect, a method of configuring a telecommunications channel unit card comprises providing a subscriber bus interface for communicating subscriber bus signals with a digital loop carrier matrix; providing a mapping circuit for mapping between subscriber bus signals and wideband telecommunications signals, providing a plurality of spans for communicating wideband telecommunications signals with an external network, and providing a processor node for controlling operation of the mapping circuit and the plurality of span interfaces.

In various implementations, the invention may provide one or more of the following advantages. The setup of the hardware and software as described here increases the capacity of each card. Each remote or central terminal is able to increase its capacity without a significant hardware or software upgrade, thus lowering the cost per line.

In addition, three El lines can share one processor and one ASIC. Also, fewer channels are used in transmission and reception of subscriber bus interface (SBI) signals. In the conventional arrangement, sending three El signals costs six - 5 - channels, but using the techniques described here sending three El signals costs only four channels. Maintaining four lines is more economical than maintaining six. Furthermore, there is no reduction of quality. Being message-based, the multiple-channel card has even better quality of service than the CAS system. Additional features and advantages of the invention will become apparent from the following description, drawings and claims.

Brief Description of the Drawings FIG. 1 is a block diagram of a distributed local services switching system. FIG. 2 is a partial block diagram of a digital loop earner.

FIG. 3 is a functional block diagram of a channel unit card. FIG. 4 is a functional block diagram of a span interface. FIG. 5 is a functional block diagram of a processor node. FIG. 6 is a functional block diagram of an application specific integrated circuit (ASIC).

FIG. 7 illustrates the conversion of a generic El signal to SBI format. FIG. 8 illustrates one format of a message-oriented SBI signal generated by an El card.

Detailed Description As shown in FIG. 1, a telecommunications system 2 includes a digital loop carrier (DLC) 4. The digital loop carrier 4 includes a central office terminal (CT) 6 coupled to one or more remote terminals (RT) 8, 10 via metallic, fiber or other suitable communication media 12. The digital loop carrier 4 acts as a delivery unit for the system 2 by delivering call control and management signals. Subscriber devices, such as telephone service equipment 14, 16, 18, can be coupled to the central office terminal 6 and to the remote terminals 8, 10, respectively. The central office terminal 6 also is coupled to a local exchange carrier (LEC) network 22. The central office terminal 6 may be coupled to the LEC network 22 through - 6 - a switch 20, such as a class 5 switch. In different implementations, the switch 20 and LEC network 22 operate according to a protocol that uses either message- oriented signaling, such as the International Telecommunications Union Telecommunications standard, or bit-oriented signaling, such as Channel Associated Signaling (CAS). Other message-oriented and bit-oriented protocols can be used instead or in addition.

As shown in FIG. 2, the central office terminal 6 and the remote terminals, such as terminal 8, have one or more channel unit card slots, such as slots 26, 36, respectively. Slots 26, 36 accommodate channel unit cards which cany data signals to and from subscriber lines 48 and LEC network lines 46. The subscriber lines 48 are coupled to subscriber devices, such as the telephone 16 (FIG. 1). The LEC network lines 46 are coupled to the LEC network 22 (FIG. 1). Channel unit cards convert incoming subscriber line data signals into formatted digital data and convert formatted digital data into data signals suitable for transmission over the subscriber lines.

Different channel unit cards serve different kinds of nanowband (e.g., POTS, COIN, UVG/EWG, Four- Wire E&M, Universal Four- Wire, Basic Rate Interface Unit) and wideband (ISDN, DS1U, T1U, ADS1U, AT1U, El, El Short Haul, El Long Haul and ElConc) subscriber lines. As shown in FIG. 2, for example, a POTS card 50 is inserted in one of the channel unit card slots 36 at the remote terminal 8 for connection to a subscriber device. Similarly, an El card 52 is inserted into one of the channel unit card slots 26 at the central office terminal 6 for coupling signals to the LEC network 22. An El card is a 2-Megabit card that uses thirty-two channels in which each channel, or time slot, conesponds to a 64 kilobit per second (Kb/s), or DSO, signal. The slots 26, 36 also can accommodate additional channel unit cards of the same or different types.

As further shown in FIG. 2, each of the central office terminal 6 and the remote terminal 8 also includes one or more transmission card slots 30, 40 to accommodate transmission cards. Transmission cards enable the terminals 6, 8 to communicate over the communication medium 12. The transmission cards handle - 7 - the conversion between the communication medium 12 signals and electric signals that the terminals 6, 8 can understand and process.

Different transmission cards support different communication media. El cards, for example, can be used to support communications over metallic media, and optical line unit cards can be used for fiber optic communications. The El format can be used, for example, with time division mutiplexing (TDM) techniques based on the International Telecommunication Union CCITT's G.700 Series Recommendations.

The central office terminal 6 and the remote terminals 8 each includes at least one bandwidth allocator, processor and timing unit (BPT) card 28, 38. Each BPT card 28, 38 collects formatted digital signals from its respective channel unit cards in the slots 26 or 36 and multiplexes them into a time domain multiplexed (TDM) signal. The multiplexed signal then can be sent over the transmission medium 12 via transmission cards in the slots 30 and 40, respectively. The BPT cards 28, 38 also receive TDM signals from their respective transmission cards. The BPT cards 28, 38 demultiplex the received TDM signals and route them for delivery to their respective channel unit cards in slots 26, 36. Respective subscriber bus interfaces 32, 42 are used to send signals between the channel unit cards in the slots 26 or 36 and their conesponding BPT cards 28 or 38. Similarly, octal buses 34, 44 are used to send signals between the transmission cards in the slots 30, 40 and their conesponding BPT cards 28 or 38.

In general, each BPT card, such as the BPT card 28, includes a processor 54, such as a microprocessor or a microcontroller, as well as various forms of associated memory 56. The memory 56 may include flash memory 58 such as electrically erasable programmable read only memory (EEPROM) as well as other types of memory, such as random access memory (RAM) and read only memory (ROM). The BPT card 38 may be similar to the BPT card 28. Additional details of the BPT cards 28, 38 are described, for example, in a U.S. Patent Application, entitled "Telecommunications Terminal" and filed on November 14, - 8 -

1997, which is assigned to the assignee of the present invention and which is incorporated herein by reference in its entirety.

As shown in FIG. 3, an El card receives signals in the El format and remaps them into subscriber bus interface (SBI) format and vice versa. The El card includes an application specific integrated circuit (ASIC) 100 which serves as the standard El interface between a subscriber bus interface(SBI) 110, 108, a processor node 116, and a span interface 114. "Span" refers to that portion of a high-speed digital system that connects one central office to another central office or one terminal office to another terminal office. Each card can support up to three El spans, utilizing up to either four single density SBIs or two double density SBIs. The card has an outbound SBI bus 102 and an inbound SBI bus 104 to transmit and receive El signals accordingly. Both buses are managed by a SB clock and control 106. A protection bus 108, usually in standby mode, serves as backup to a main bus 110. If the main bus 110 becomes unavailable, signals would be routed through the protection bus 108. Additionally, the ASIC 100 provides an 8KHz synchronization reference 112 to one of the BPT cards 28, 38 (FIG. 2) and provides external interrupts 150 to the processor node 116. Furthermore, the ASIC 100 generates a subscriber bus data link (SBDL), which is a data link layer protocol used by the subscriber bus, and a reset detect. The ASIC 100 also optionally performs companding conversion (A-law to u-law and u-law to A-law) and programmable transmission level point (TLP) adjust via an EEPROM 302 (FIG. 5).

The span interface 114 includes three identical circuits for transmitting and receiving three El signals 118. Upon being received, the three El signals 118 are processed (e.g., digitized, framed, and time division multiplexed). Then, the processed signals are sent to the ASIC 100 via six inbound TDM buses 122. In the outbound case, the SBI signal 102 from the ASIC 100 travels to the span interface via six outbound TDM buses 120. The clocks and control are sent by the ASIC 100 to the span interface via the clocks and control bus 124. The span interface - 9 -

114 also provides the receive clocks 126 and framer interrupts 128 to the ASIC 100.

The processor node 116 functions mainly as the controller of this card. This node interfaces with the span interface 114 and the ASIC 100 to provision and control their functionality, monitor status, and communicate with one of the BPT cards 28, 38 (FIG. 2) over the SBDL via a microprocessor control bus 137 and an address bus 136. The Data for provisioning and control travels among the processor node, ASIC, and span interface on a microprocessor data bus 138. For message-based applications, the ASIC 100 remaps the software selectable channels of the El spans to and from the TDM bus 130. High level data link control

(HDLC) could be used for this type of applications. HDLC is a link layer protocol standard for point to point and multi-point communications where the control information is always placed in the same position and specific bit patterns used for control differs dramatically from those used in representing data, so that enors are less likely to occur. HDLC protocol messages, which are in the data streams being transmitted and received by the ASIC 100, are direct memory accessed (DMA) to memory, and an interrupt is generated. This process is maintained by a TDM clocks and control bus 132. A flash control 312, flash address 308, and flash data 310 allow the ASIC 100 to access the EEPROM 302. Interrupts 150 are sent from the ASIC 100 to the processor node 116. The processor node 116 also controls the front panel LEDs 140 via the LED controls 142.

A power supply monitor/reset generator 144 provides a reset pulse 148 on power up and low voltage conditions. The generator 144 also provides a hard reset 146 to the processor 116. As shown in FIG. 4, the span interface 114 includes three identical circuits (span A, B, and C) each of which includes a line interface unit (LIUyframer 200 and a front end 202. Because the three circuits are identical, only one will be described herein, with the understanding the same description applies to the other two. - 10 - In the transmit direction, the outbound TDM bus 120 from the ASIC 100 are input to the LiU/framer 200. The framer portion and the LIU portion could be on a single chip. The framer inserts framing bits so the receiver can identify the channels and time slots, and the LIU allows the framer to interface with the physical lines. The TDM data and signaling are converted and routed to the LIU transmitter, and outputted 210 to the front end 202 as differential alternate mark inversion (AMI) data which is an analog form of the El signal. The AMI is sent over a span transmit 212 to a transmitting medium such as the LEC network lines 46 (FIG. 2). In the receive direction, the LIU receiver receives the AMI data inputs 214 from the front end 202 via the span receive 216. The framer portion of the LIU/framer 200 then formats the resulting data and signaling information into a TDM stream and sends the stream over the inbound TDM bus 218. The front end 202 protects the transmit and receiving lines from an exposed environment. The recovery line rate clock 126, used for system synchronization, and the span interrupt 128 are outputted to the ASIC 100. The ASIC 100 (FIG. 3) is controlled through a register set accessible via the microprocessor control bus 137, address bus 136, and data bus 138. The clocks and control 124 signal from the ASIC 100 provides synchronization for all three spans. A ONESEC bus which canies a ONESEC signal 224 from span A's framer and delivers it to span B and C. The signal is used to synchronize the spans' status report.

As shown in FIG. 5, the Processor node 116 (FIG. 3) includes a microprocessor 300 such as a Motorola MC68MH360 Quad Integrated Communications Controller (QUICC), an EEPROM 320 such as a 512 kb flash EEPROM, and a DRAM 304 such as a 4 Mb DRAM. A clock 306, for example a 4 MHz oscillator, is input to the microprocessor 300. The microprocessor 300 controls the memory with eight general purpose chip selects. The ASIC 100 uses the microprocessor 300 for interfacing to all memory and peripherals. Thus, the hardware need not provide fixed address decoding because the base address memory map is configured via software. EEPROM 302 contains configuration memory and lookup tables for the ASIC 100. The EEPROM 302 also contains the - 11 - boot code and non-volatile configuration storage for the microprocessor 300. The configuration address and data pins are connected to the Flash address bus 308 and flash data 310 bus. The ASIC 100 uses the flash control bus 312 to control access to the various components. The DRAM 304 provides the microprocessor 300 with volatile code and data storage.

As shown in FIG. 6, the ASIC 100 is divided into seven blocks: data 402, signaling 404, communications 406, processor support 408, SBI 410, timeslot mux/demux 412, and network synchronization 414.

The data block 402 interfaces with the EEPROM 302 through the data 310, address 308, and control 312 buses and maps the TDM data channels between the SBI format and the El format. TDM mapping will be described below.

The signaling block 404 contains signaling translation RAM, signaling data RAM, and mapping of the signal between El and SBI. This block inserts the necessary CAS bits. This block is not used for message-based signaling (e.g. V5.1). When CAS is used, El bus 434 carries the CAS signaling bits.

The communications block 406 performs a timeslot interchange (TSI). Any channel of any El or any SBI can be mapped to any of the 64 channels of the two TDM buses 130. In addition to setting up the TSI, software also provisions each mapped channel either as transparent (e.g., SBDL) or HDLC. If provisioned for SBDL, the ASIC 100 (FIG. 3) does appropriate SBDL processing. The ASIC 100 (FIG. 3) can be provisioned by software to handle up to three SBDL channels for the three primary SBIs. The communications block also maps the El and SBI communications channels. These channels are used to communicate between the ASIC 100 and processor node 116 (FIG. 3) in a message-based system. The processor support block 408 is used during setup, address decode, and memory decode. This block processes interrupts which includes the interrupts generated by the framer 128 and microprocessor interface. It also manages the status and control registers. Processor support block 408 communicates with the microprocessor 300 (FIG. 5) through the microprocessor control and address buses 136, 137 and sends interrupts 150 and data 138 as described above. - 12 -

The timeslot mux/demux block 412 maps the internal TDM paths, as shown in Fig. 6, using a combination of channel counters and software provisional control. For example, a customer's voice/data travels the path in the following order: El Proper 120, 122, El data 436, SBI data 438, and SBI proper 440. The signaling bus 434, 444, carrying El and SBI signaling bits, and the communications bus 130, 442, carrying the El and SBI communications bits are inserted translated as needed.

The synchronization block 414 performs three main functions: (1) it takes the receive clock from the software selected span and divides the receive clock down to an 8KHz signal which is sent both to the main and to the protect buses 112; (2) it generates microprocessor clock and frame 430; and (3) it generates El clock and frame 432. The synchronization block 414 also accepts clock signals from the SPAN 126 and the SBI 434.

The SBI 410 is a serial bus by which interprocessor communications, signaling, and customer voice/data are passed between the line card 100 and a matrix (e.g., BPT 28, 38). The SBI main 110 and protect 108 buses connect the SBI to the matrix.

As shown in FIG. 7, a generic SBI signal is placed in odd 500 and even 510 channels. All the timeslots of the SBI signal are mapped from conesponding El timeslots. Because certain timeslots are reserved, some frames do not have conesponding time slots available (i.e., 0, 4, 12, 16, 20, 24, 28). Those frames are placed in the even channel 510 as shown in Fig. 7, which represents the SBI signal format for a single El.

As shown in FIG. 8, triple El mapping occurs in the ASIC block 100 using the software and hardware support of the previously described blocks. In general terms, triple El mapping maps the three even El channels to one SBI channel. The reserve, SBDL, SBI service request (SRQ), and signaling timeslots of the channels are set up substantially in the same manner as in the single El case. The three odd SBI channels are remapped the same way as if they were single El channels. Because frames 2, 3, 6, 7, etc. on the even channels were unused in the - 13 - single El case, the three El signals now share the same even channel. The displaced timeslots of the second El signal are remapped to frames 2 and 6, etc., and the third El signal uses frames 3 and 7, etc. As a result, three El spans are transmitted using four lines in SBI format.

The methods and techniques described here also could be applied to other signals in other configurations, such as a Tl system comprising a Tl LIU/Framer and a suitable variation of the software. Other embodiments are within the scope of the following claims.

What is claimed is:

Claims

- 14 -

1. A telecommunications channel unit card comprising: a subscriber bus interface for communicating subscriber bus signals with a digital loop carrier matrix; a mapping circuit for mapping between subscriber bus signals and wideband telecommumcations signals; a plurality of spans for communicating wideband telecommunications signals with an external network; and a processor node for controlling operation of the mapping circuit and the plurality of span interfaces.

2. The telecommunications channel unit card of claim 1 wherein the spans recover the wideband telecommunications signals from incoming signals received from the external network.

3. The telecommunications channel unit card of claim 1 wherein the spans perform framing and formatting functions for wideband telecommunications signals to be sent over the external network.

4. The telecommunications channel unit card of claim 1 wherein the mapping circuit maps inbound wideband telecommunications signals into subscriber bus signals using a plurality of odd and even channels.

5. The telecommunications channel unit card of claim 1 wherein the mapping circuit maps inbound wideband telecommunications signals into subscriber bus signals by combining up to three even channels and by preserving conesponding odd channels. - 15 -

6. The telecommunications channel unit card of claim 1 wherein the mapping circuit maps outbound subscriber bus signals into wideband telecommunications signals by separating one even channel and by preserving conesponding odd channels.

7. The telecommunications channel unit card of claim 1 wherein the mapping circuit is implemented as an application-specific integrated circuit (ASIC).

8. The telecommunications channel unit card of claim 1 wherein the wideband telecommunications signals comprise El or Tl signals.

9. The telecommunications channel unit card of claim 1 wherein the digital loop carrier matrix comprises a bandwidth, processor and timing (BPT) card.

10. A telecommunications channel unit card comprising: first communicating means for communicating subscriber bus signals with a digital loop earner matrix; means for mapping between subscriber bus signals and wideband telecommunications signals; second communicating means for communicating wideband telecommunications signals with an external network; and means for controlling operation of the mapping means and the first and second communicating means.

11. The telecommunications channel unit card of claim 10 wherein the second communicating means recovers the wideband telecommunications signals from incoming signals received from the external network. - 16 -

12. The telecommunications channel unit card of claim 10 wherein the second communicating means performs framing and formatting functions for wideband telecommunications signals to be sent over the external network.

13. The telecommunications channel unit card of claim 10 wherein the mapping means maps inbound wideband telecommunications signals into subscriber bus signals using a plurality of odd and even channels.

14. The telecommunications channel unit card of claim 10 wherein the mapping means maps inbound wideband telecommunications signals into subscriber bus signals by combining up to three even channels and by preserving conesponding odd channels.

15. The telecommunications channel unit card of claim 10 wherein the mapping means maps outbound subscriber bus signals into wideband telecommunications signals by separating one even channel and by preserving conesponding odd channels.

16. The telecommunications channel unit card of claim 10 wherein the mapping means is implemented as an application-specific integrated circuit (ASIC).

17. The telecommunications channel unit card of claim 10 wherein the wideband telecommunications signals comprise El or Tl signals.

18. The telecommunications channel unit card of claim 10 wherein the digital loop carrier matrix comprises a bandwidth, processor and timing (BPT) card. - 17 -

19. A method of configuring a telecommunications channel unit card comprising: providing a subscriber bus interface for communicating subscriber bus signals with a digital loop carrier matrix; providing a mapping circuit for mapping between subscriber bus signals and wideband telecommunications signals; providing a plurality of spans for communicating wideband telecommunications signals with an external network; and providing a processor node for controlling operation of the mapping circuit and the plurality of span interfaces.

20. The method of configuring the telecommunications channel unit card of claim 19 wherein the spans recover the wideband telecommunications signals from incoming signals received from the external network.

21. The method of configuring the telecommunications channel unit card of claim 19 wherein the spans perform framing and formatting functions for wideband telecommunications signals to be sent over the external network.

22. The method of configuring the telecommunications channel unit card of claim 19 wherein the mapping circuit maps inbound wideband telecommunications signals into subscriber bus signals using a plurality of odd and even channels.

23. The method of configuring the telecommunications channel unit card of claim 19 wherein the mapping circuit maps inbound wideband telecommunications signals into subscriber bus signals by combining up to three even channels and by preserving conesponding odd channels. - 18 -

24. The method of configuring the telecommunications channel unit card of claim 19 wherein the mapping circuit maps outbound subscriber bus signals into wideband telecommunications signals by separating one even channel and by preserving conesponding odd channels.

25. The method of configuring the telecommunications channel unit card of claim 19 wherein the mapping circuit is implemented as an application- specific integrated circuit (ASIC).

26. The method of configuring the telecommunications channel unit card of claim 19 wherein the wideband telecommunications signals comprise El or Tl signals.

27. The method of configuring the telecommunications channel unit card of claim 19 wherein the digital loop carrier matrix comprises a bandwidth, processor and timing (BPT) card.