EP1008169B1 - Producing microstructures or nanostructures on a support - Google Patents

Producing microstructures or nanostructures on a support Download PDF

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EP1008169B1
EP1008169B1 EP98939717A EP98939717A EP1008169B1 EP 1008169 B1 EP1008169 B1 EP 1008169B1 EP 98939717 A EP98939717 A EP 98939717A EP 98939717 A EP98939717 A EP 98939717A EP 1008169 B1 EP1008169 B1 EP 1008169B1
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Prior art keywords
crystalline
lattice
wafer
defects
wafers
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EP1008169A1 (en
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Michel Bruel
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Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185—Joining of semiconductor bodies for junction formation

Definitions

  • the present invention relates to the production of microstructures or nanostructures on a support.
  • microstructures and the nanostructures for still smaller dimensions, are in the form of a network of microvolumes of material obtained on the surface of a support.
  • microvolume means, for example, volumes of parallelepiped shape, preferably smaller than one micrometer.
  • microstructures in semiconductor material and in particular in silicon, AsGa, III-V compounds and SiC.
  • conducting materials such as metals, and dielectric materials such as SiO 2 .
  • micro- or nanostructures are intended for the production of electronic, optical or optoelectronic devices.
  • this type of structure allows the realization of a quantum dot array (called “quantum dots” in the English terminology), or electronic devices called mono-electron or Coulomb blocking (“Coulomb blockade”) or else light emitting devices.
  • microstructures When we want to make microstructures, we use the techniques today in the field of microelectronics. In particular, the principles of lithography combined with dry or wet etching, ion implantation, deposition and heat treatment operations are used. For example, if one wants to make a square network of parallelepiped microvolumes monocrystalline silicon, each microvolume having 1 micron side to 0.2 microns thick, microvolumes being spaced from each other by 0.5 microns, can start from a SSI (Silicon On Insulator) wafer having a 0.2 micron thick monocrystalline silicon layer.
  • SSI Silicon On Insulator
  • a layer of photosensitive resin is applied to the silicon layer of the wafer and is insulated by means of an Electron Beam Pattern Generator ("Electron Beam Pattern Generator") so as to inscribe in the resin a matrix of rows and columns 0.5 ⁇ m wide representing the spaces between the microvolumes.
  • the development of the resin releases the exposed parts, exposing the silicon layer corresponding to the array of rows and columns.
  • the wafer is then subjected to a plasma etching treatment selectively attacking the silicon with respect to the resin. The etching process ends when the underlying silica layer is reached.
  • an array of microvolumes each having 1 ⁇ m ⁇ 1 ⁇ m ⁇ 0.2 ⁇ m in size and spaced 0.5 ⁇ m apart is obtained. If necessary, the spaces between microvolumes can then be filled by a dielectric layer such as SiO 2 , or by using a thermal oxidation process or a CVD type deposit.
  • microstructures with microvolumes of much smaller dimensions for example a few tens of nanometers
  • condensation nuclei randomly distributed on the surface can be obtained.
  • microstructures are multiple and depend on the particular properties of each. These properties are related to a size effect on the electronic states of carriers in these materials, surface effects, interface effects, the existence or not of intergranular phases, etc.
  • a particular application is the production of light emitters, in particular from materials such as silicon which, in the solid monocrystalline state, are not emitters (see the article by T. KOMOKA already cited).
  • Another application is the realization of electronic devices based on the quantum confinement of electronic carriers in microvolumes of the structure or Coulomb blocking effects. This application is described in the article " Modeling the Multiplicity of Conductance Structures in Clusters of Silicon Quantum Dots by DW BOERINGER and R. TSU, published in Mat. Res, Soc Symp, Proc Vol 358, pp. 569-574, 1995. , Materials Research Society.
  • the present invention has been designed to allow the production of microstructures that may include microvolumes of dimensions significantly smaller than microvolumes currently achievable, for example a few tens of nm, economically and over large areas.
  • these microstructures are organized according to a predetermined plan instead of being randomly distributed.
  • the invention proposes a process for producing micro- or nanostructures, which applies to crystalline materials, whether they are semiconductors, conductors or dielectrics.
  • the disagree parameter can be constituted by a given angle of offset in rotation of the crystal lattices presented by said faces.
  • the network of defects obtained, called “twist” is a network of dislocations to character screws.
  • the disagreement parameter can also be constituted by a difference in crystal lattice parameter between the crystalline materials of the faces of the wafers put in contact with the resulting defect network is called "misfit".
  • the detuning parameter can also be constituted by a determined angle according to which the face of at least one of the platelets is offset with respect to the single crystallographic plane of direction corresponding to this face.
  • the disoriented crystalline faces (one or both) with respect to a simple crystallographic plane are called vicinal.
  • the fault network is called "miscut”.
  • mismatch parameters are possible, for example by gluing two different materials and offset in rotation. Several networks are then formed.
  • the contacting may preferably be hydrophobic type, that is to say, direct bonding of the faces of said wafers. It may be of the hydrophilic type, that is to say involving a thin intermediate layer, for example an oxide layer formed naturally on one face of a wafer or on the faces of the wafers.
  • the method also comprises at least one heat treatment step intended either to complete the formation of the crystal defect network and / or the constraint network if the contacting is insufficient to complete it, or to complete it completely.
  • this treatment may be able to reinforce the interatomic bonds between the faces of the platelets put in contact.
  • This heat treatment can be performed before or after the thinning step.
  • the thinning step may be carried out using a technique chosen from grinding, mechanical abrasion or chemical abrasion.
  • the thinning step may also be carried out by cleaving one of the platelets which, before the contacting step has been subjected, through its contacting face, to an ion implantation step intended to create, at a determined depth and corresponding to the desired thinning, a layer of microcavities capable of generating a cleavage plane during a subsequent heat treatment step.
  • the ion implantation can be carried out by means of hydrogen ions.
  • the thinning step it can be provided at least one heat treatment step simultaneously making it possible to complete or complete the formation of the lattice of crystalline defects and / or the network of stresses, to reinforce the interatomic bonds between the faces of the platelets contacted and generate the cleavage plane.
  • the micro- or nanostructure after the thinning step, it may be provided a step of selectively treating the lattice of crystalline defects and / or the stress network with respect to said crystalline zone .
  • This selective treatment step may consist of conductive crystalline defects and / or the network of stresses so that said crystalline zone forms crystalline pads electrically connected to each other. In this case, it is possible to carry out a phosphorus diffusion which diffuses preferentially at the level of the crystalline defects.
  • the selective treatment step may also consist of electrical insulation so that said crystalline zone forms crystalline pads electrically insulated from each other.
  • the chemical etching may be preceded by a crystalline defects decoration phase and / or the stress network by precipitation of metal impurities or dopants.
  • the network of defects produced by the techniques indicated above extends a small thickness on either side of the bonding surface of the two wafers.
  • the stresses induced by these defects extend on each side of the interface, in the wafers, over distances of the order of magnitude of the dislocation period.
  • the thinning of one of the platelets can be done by stopping the operation at a distance from the interface which is of the same order of magnitude.
  • the surface stress field is nonuniform and is in the image of the underlying defect network.
  • the selective treatment step can then consist in depositing, for example by epitaxy, a crystalline crystal detuned crystalline material with the crystalline material revealed by the thinning step, this deposited crystalline material forming an ordered set of islands in correspondence with the lattice of underlying crystal defects.
  • the electrical isolation of the selective treatment may be of the type where electrical conduction can take place by a physical effect such as the tunnel effect or the Fowler-Nordheim effect.
  • the selective treatment step can also consist in treating the crystalline defects and / or the network of stresses so that said crystalline zone forms crystalline pads connected to each other by semiconductor zones or having a potential barrier.
  • the subject of the invention is also a micro- or nanostructure on a support, characterized in that it is obtained according to the method described above from platelets whose faces to be in contact are made of semiconductor materials. At least one of these faces to be contacted may be SiC or III-V semiconductor material such as AsGa or GaAlAs.
  • the subject of the invention is also a micro-or nanostructure on a support, characterized in that it is obtained according to the method described above, one of the wafers consisting of a silicon-on-insulator wafer, Another wafer being made of silicon and constituting the thinned wafer, the method making it possible to obtain a micro- or nanostructure consisting of microvolumes of silicon on an insulating layer.
  • FIGS. 1A, 1B and 1C illustrate three variants of implementation of the method according to the present invention.
  • X 1 , X 2 and X 3 represent the crystallographic axes.
  • the parameter that adjusts the defect density (or the average distance between defects) is the angle of rotation ⁇ existing between the crystal lattices presented by the faces contacted platelets 1 and 2.
  • the parameter which regulates the density of defects (or the average distance between defects) is the angle of rotation ⁇ existing between the crystallographic planes of the plates 101 and 102 contacted.
  • the parameter that adjusts the defect density (or the average distance between defects) is the mesh mismatch f 1 between the two crystalline materials of the platelets 201 and 202 contacted.
  • one of the platelets can be prepared with a vicinal side shifted in the ⁇ 100> direction of 0.8 ° and glued on a non-vicinal silicon wafer (100).
  • the densities of nanostructures obtained are then 2.7 ⁇ 10 15 / m 2 .
  • a silicon wafer (100) is adhered to a second wafer having a SiGe layer on its surface. Since the mismatch f 1 is 2.1%, a 20 nm corner dislocation interface grating is formed. After thinning the wafer comprising the SiGe layer to approximately 10 nm, and after revelation by one of the described techniques, a density of nanostructures of the same order of magnitude as above is obtained. The bonding of a germanium wafer would produce a double clash and thus a density of nanostructures four times higher.
  • Faces other than faces (100) may be used.
  • the faces (111) produce at their interface hexagonal or triangular networks of dislocations.
  • Faces (110) produce rectangular gratings.
  • the Figure 1A shows two platelets 1 and 2 in silicon of crystallographic plane (1,0,0) when they come into contact and having plane faces, respectively 3 and 4, facing each other.
  • the flat faces 3 and 4 received a surface treatment to make them hydrophobic. This will ensure an intimate and adherent contact of the faces 3 and 4.
  • This surface treatment comprises a chemical cleaning step ending for example by a hydrofluoric acid etching step.
  • the faces 3 and 4 are brought into contact with adhesion by molecular adhesion, for example at ambient temperature, ensuring that the crystal lattices presented by the two faces are offset relative to one another by an angle ⁇ determined, for example 0.6 °.
  • the assembly constituted by these two inserts is then subjected to a heat treatment at a temperature of about 950 ° C for about 30 minutes. During this heat treatment, stronger and more numerous interatomic bonds are established between the two platelets. Due to the torsion angle existing between the two crystal lattices, an array of crystal defects, for example a dislocation lattice, is established in the vicinity of the interface between the two platelets, in a thin layer (a few tens to a few hundred nm) centered on the interface. This is schematically represented on the figure 2 where the reference 5 designates this interface, the crystalline defects (or dislocations) being represented under the reference 6.
  • the spacing between two adjacent dislocations is a function of the ⁇ rotation angle of the crystal lattices of the two platelets.
  • a surface treatment can then be implemented to differentiate, more specifically, the crystalline defects of the surrounding crystalline zone 8.
  • Lateral dielectric isolation of microvolumes 9 can be performed.
  • the oxide layer deposited on the microstructure 7 may be leveled, as shown in FIG. figure 4 , to keep only a deposit of insulation 11 between the microvolumes 9. In this case, we obtain a network of insulating material replacing the dislocation network.
  • dislocation network conductive can also be carried out to make the dislocation network conductive, insulative, or even semiconductor depending on the intended application. This makes it possible to make the microvolumes or pads crystalline, either electrically connected to one another by conductive bonds, or electrically isolated, or connected by semiconductor zones or having a potential barrier. With regard to the electrical insulation, insulations such as electrical conduction through the insulating parts can also take place by tunnel effect for example, or by the Fowler-Nordheim effect or by any other physical effect. To make the dislocation network conductive, it is possible to carry out a phosphorus diffusion which diffuses preferentially at the level of the dislocations.
  • Another possibility of carrying out the thinning step consists in applying the process described in the document FR-A-2,681,472 in order to obtain a cleavage of the wafer concerned.
  • protons are implanted in this wafer to obtain a layer of microcavities at the desired depth of the face to be brought into contact. This face undergoes the cleaning and bonding treatment. The heat treatment is then applied. It allows to generate simultaneously the creation of dislocations and cleavage according to the layer of microcavities.
  • One of the wafers may be an SSI (Silicon-On-Insulator) wafer called SOI ("Silicon on Insulator") in the English terminology and the other wafer may be a solid substrate. of silicon.
  • SOI Silicon-On-Insulator
  • the method according to the invention then provides a network of microvolumes of silicon on an insulating layer.
  • the two platelets of crystalline material may be of a different nature, for example a silicon wafer and a gallium arsenide wafer, or a silicon wafer and a germanium wafer.
  • platelets are not necessarily homogeneous. It suffices simply that the faces to be brought into contact are of crystalline material, the rest of the wafers may have other structures.
  • the micro- or nanostructure can still be obtained from a network of constraints.
  • This network of constraints can be revealed by various techniques.
  • the constraint network can be revealed by deposition, by an epitaxial process (MOCVD, MBE, liquid phase epitaxy ...), on the thinned plate of a crystalline mesh detuned crystalline material.
  • MOCVD epitaxial process
  • MBE liquid phase epitaxy
  • the preferential nucleation sites provided by the zones in compression (respectively in tension) will be favorable for the smaller (respectively larger) mesh deposits than the thinned plate.
  • An ordered set of islands of size corresponding to the underlying network will thus be formed.
  • This deposit can be illustrated from the variant of the process illustrated by the figure 1C .
  • An assembly has been prepared according to this variant, as described above, from an orientation silicon wafer (100) and a wafer comprising the SiGe layer. After thinning, we obtain the assembly represented at figure 5 where reference 202 designates the silicon wafer and the reference 201 'remains of the SiGe layer.
  • a deposit of pure germanium is carried out under Stranski-Krastanov growth conditions. Nano-sized germanium islands 210 are nucleated vertically above the nodes of the dislocation network, in the stress-stress zones.

Abstract

The invention concerns a method for producing microstructures or nanostructures on a support, comprising the following steps: contacting one surface of a first wafer (1) in crystalline material with a surface of a second wafer (2) in crystalline material, so that the two crystalline lattices of said surfaces have at least one misalignment parameter for forming a crystalline fault network (6) and/or a stress network within the crystalline zone (8) extending on either side of the interface of the two wafers, at least one of said networks defining a microstructure or a nanostructure; thinning one (1) of the two wafers to expose the fault network and/or the stress network on a support (10) constituted by the other wafer.

Description

Domaine techniqueTechnical area

La présente invention concerne la réalisation de microstructures ou de nanostructures sur un support.The present invention relates to the production of microstructures or nanostructures on a support.

Les microstructures, et les nanostructures pour des dimensions encore inférieures, se présentent sous la forme d'un réseau de microvolumes de matériau obtenus à la surface d'un support. Par microvolume, on entend par exemple des volumes de forme parallélépipédique, de dimensions préférentiellement inférieures au micromètre.The microstructures, and the nanostructures for still smaller dimensions, are in the form of a network of microvolumes of material obtained on the surface of a support. By microvolume means, for example, volumes of parallelepiped shape, preferably smaller than one micrometer.

Généralement, on s'intéresse à des microstructures en matériau semiconducteur et en particulier en silicium, en AsGa, en composés III-V et en SiC. Cependant, on s'intéresse également aux matériaux conducteurs, tels que les métaux, et aux matériaux diélectriques tels que SiO2.Generally, one is interested in microstructures in semiconductor material and in particular in silicon, AsGa, III-V compounds and SiC. However, there is also interest in conducting materials, such as metals, and dielectric materials such as SiO 2 .

Ces micro- ou nanostructures sont destinées à la réalisation de dispositifs électroniques, optiques ou optoélectroniques. En particulier, ce type de structures permet la réalisation d'un réseau de boîtes quantiques (appelées "quantum dots" dans la terminologie anglo-saxonne), ou de dispositifs électroniques dits mono-électrons ou à blocage de Coulomb ("Coulomb blockade") ou encore de dispositifs émetteurs de lumière.These micro- or nanostructures are intended for the production of electronic, optical or optoelectronic devices. In particular, this type of structure allows the realization of a quantum dot array (called "quantum dots" in the English terminology), or electronic devices called mono-electron or Coulomb blocking ("Coulomb blockade") or else light emitting devices.

Etat de la technique antérieureState of the art

Lorsque l'on veut réaliser des microstructures, on utilise les techniques aujourd'hui classiques du domaine de la micro-électronique. En particulier, on utilise les principes de la lithographie combinée avec des opérations de gravure sèche ou humide, d'implantation ionique, de dépôts et de traitement thermique. Par exemple, si l'on veut réaliser un réseau carré de microvolumes parallélépipédiques en silicium monocristallin, chaque microvolume ayant 1 µm de côté pour 0,2 µm d'épaisseur, les microvolumes étant espacés les uns des autres de 0,5 µm, on peut partir d'une plaquette SSI (Silicium Sur Isolant) présentant une couche de silicium monocristallin de 0,2 µm d'épaisseur. On applique sur la couche de silicium de la plaquette une couche de résine photosensible que l'on insole grâce à une machine d'insolation à faisceau d'électrons ("Electron Beam Pattern Generator") de façon à inscrire dans la résine une matrice de lignes et de colonnes de largeur 0,5 µm représentant les espaces entre les microvolumes. Le développement de la résine dégage les parties exposées, mettant à nu la couche de silicium correspondant à la matrice de lignes et de colonnes. La plaquette est alors soumise à un traitement de gravure plasma attaquant sélectivement le silicium par rapport à la résine. Le procédé de gravure se termine quand la couche de silice sous-jacente est atteinte. Après enlèvement de la résine, on obtient un réseau de microvolumes ayant chacun 1 µm × 1 µm × 0,2 µm de dimensions et espacées de 0,5 µm. Si nécessaire, les espaces entre microvolumes peuvent être ensuite comblés par une couche diélectrique telle que SiO2, soit en utilisant un procédé d'oxydation thermique, soit un dépôt du type CVD.When we want to make microstructures, we use the techniques today in the field of microelectronics. In particular, the principles of lithography combined with dry or wet etching, ion implantation, deposition and heat treatment operations are used. For example, if one wants to make a square network of parallelepiped microvolumes monocrystalline silicon, each microvolume having 1 micron side to 0.2 microns thick, microvolumes being spaced from each other by 0.5 microns, can start from a SSI (Silicon On Insulator) wafer having a 0.2 micron thick monocrystalline silicon layer. A layer of photosensitive resin is applied to the silicon layer of the wafer and is insulated by means of an Electron Beam Pattern Generator ("Electron Beam Pattern Generator") so as to inscribe in the resin a matrix of rows and columns 0.5 μm wide representing the spaces between the microvolumes. The development of the resin releases the exposed parts, exposing the silicon layer corresponding to the array of rows and columns. The wafer is then subjected to a plasma etching treatment selectively attacking the silicon with respect to the resin. The etching process ends when the underlying silica layer is reached. After removal of the resin, an array of microvolumes each having 1 μm × 1 μm × 0.2 μm in size and spaced 0.5 μm apart is obtained. If necessary, the spaces between microvolumes can then be filled by a dielectric layer such as SiO 2 , or by using a thermal oxidation process or a CVD type deposit.

La réalisation d'un réseau de microvolumes peut aussi être obtenue en utilisant un procédé de lithographie par interférométrie ou holographie comme le divulgue l'article " Scalable Fabrication and Optical Characterization of nm Si Structures" par S.H. ZAIDI et al., paru dans Mat. Res. Soc. Symp. Proc. Vol. 358, pages 957-968 , Materials Research Society.The realization of a network of microvolumes can also be obtained by using a method of lithography by interferometry or holography as the article discloses it Scalable Fabrication and Optical Characterization of Si Si Structures by SH ZAIDI et al., Published in Mat., Res, Soc Symp., Vol 358, pages 957-968 , Materials Research Society.

L'utilisation de ces techniques permet la réalisation de microstructures pour des dimensions de l'ordre du micromètre ou de quelques dixièmes de micromètre. Pour obtenir les meilleures résolutions en terme de lithographie, on utilise l'insolation par faisceau d'électrons ou un photorépéteur sur tranche fonctionnant avec une longueur d'onde de 248 nm ou 193 nm.The use of these techniques allows the production of microstructures for dimensions of the order of a micrometer or a few tenths of a micrometer. To obtain the best resolution in terms of lithography, electron beam irradiation or a wafer photorépéteur operating at a wavelength of 248 nm or 193 nm is used.

Pour réaliser des microstructures avec des microvolumes de dimensions bien inférieures (par exemple quelques dizaines de nanomètres), il n'existe pas de moyens connus dès lors que l'on souhaite obtenir, de façon économiquement acceptable et sur de grandes surfaces, des microstructures organisées selon un plan d'organisation prédéterminé.To make microstructures with microvolumes of much smaller dimensions (for example a few tens of nanometers), there are no known means when it is desired to obtain, economically acceptable and over large areas, organized microstructures. according to a predetermined organization plan.

On peut noter cependant que l'on peut réaliser des microvolumes d'un premier matériau à l'intérieur d'une matrice d'un deuxième matériau, par exemple en introduisant dans cette matrice, par implantation ionique, des atomes du premier matériau en une concentration telle et avec un traitement thermique tel que ces atomes se rassemblent en précipités à l'intérieur de la matrice. On peut ainsi obtenir des précipités de silicium dans une matrice de SiO2 de l'ordre de 10 nm. Une telle technique est décrite par exemple dans l'article " Control of and Mechanisms for Room Temperature Visible Light Emission from Silicon Nanostructures in SiO2 Formed by Si+ Ion Implantation" de T. KOMODA et al., paru dans Mat. Res. Soc. Symp. Proc. Vol. 358, pages 163-168, 1995 , Materials Research Society. Cependant, les précipités obtenus sont répartis au hasard dans la matrice.It may be noted, however, that it is possible to produce microvolumes of a first material inside a matrix of a second material, for example by introducing in this matrix, by ion implantation, atoms of the first material into a such concentration and with a heat treatment such that these atoms collect into precipitates inside the matrix. It is thus possible to obtain silicon precipitates in an SiO 2 matrix of the order of 10 nm. Such a technique is described for example in the article " Control of and Mechanisms for Temperature Visible Light Emission from Silicon Nanostructures in SiO2 Formed by Si + Ion Implantation of T. KOMODA et al., Published in Mat., Res., Symp., Proc Vol 358, pp. 163-168. 1995 , Materials Research Society. However, the precipitates obtained are randomly distributed in the matrix.

De façon analogue, en réalisant un dépôt (par exemple, par évaporation) sur une surface, on peut obtenir des noyaux de condensation répartis au hasard sur la surface. L'article " Generation and Structural Analysis of Silicon Nanoparticles" de PING LI et K. SATTLER, paru dans Mat. Res. Soc. Symp. Proc. Vol. 358, pages 123-126, 1995 , Materials Research Society, divulgue l'évaporation de silicium sur une surface de silicium ou de graphite.Similarly, by depositing (for example, by evaporation) on a surface, condensation nuclei randomly distributed on the surface can be obtained. The article Generation and Structural Analysis of Silicon Nanoparticles by PING LI and K. SATTLER, published in Mat., Res, Soc Symp, Proc Vol 358, pp. 123-126, 1995. , Materials Research Society, discloses the evaporation of silicon on a surface of silicon or graphite.

Les applications de ces microstructures sont multiples et dépendent des propriétés particulières de chacune. Ces propriétés sont liées à un effet de taille sur les états électroniques des porteurs dans ces matériaux, aux effets de surface, d'interface, à l'existence ou non de phases intergranulaires, etc. Une application particulière est la réalisation d'émetteurs de lumière, notamment à partir de matériaux tels que le silicium qui, à l'état monocristallin massif ne sont pas émetteurs (voir l'article de T. KOMOKA déjà cité). Une autre application est la réalisation de dispositifs électroniques basés sur le confinement quantique des porteurs électroniques dans les microvolumes de la structure ou à des effets de blocage de Coulomb. Cette application est décrite dans l'article " Modelling the Multiplicity of Conductance Structures in Clusters of Silicon Quantum Dots" de D. W. BOERINGER et R. TSU, paru dans Mat. Res. Soc. Symp. Proc. Vol. 358, pages 569-574, 1995 , Materials Research Society.The applications of these microstructures are multiple and depend on the particular properties of each. These properties are related to a size effect on the electronic states of carriers in these materials, surface effects, interface effects, the existence or not of intergranular phases, etc. A particular application is the production of light emitters, in particular from materials such as silicon which, in the solid monocrystalline state, are not emitters (see the article by T. KOMOKA already cited). Another application is the realization of electronic devices based on the quantum confinement of electronic carriers in microvolumes of the structure or Coulomb blocking effects. This application is described in the article " Modeling the Multiplicity of Conductance Structures in Clusters of Silicon Quantum Dots by DW BOERINGER and R. TSU, published in Mat. Res, Soc Symp, Proc Vol 358, pp. 569-574, 1995. , Materials Research Society.

Dans l'article de M.Benamara et al, Materials Science and Engineering B42, (1996), pages 164-167 , on étudie le réseau de défauts formé par le collage de 2 substrats cristallins dont les réseaux sont décalés.In the article of M.Benamara et al, Materials Science and Engineering B42, (1996), pages 164-167 , we study the defect network formed by the bonding of 2 crystalline substrates whose networks are shifted.

Exposé de l'inventionPresentation of the invention

La présente invention a été conçue afin de permettre la réalisation de micro-structures pouvant comporter des microvolumes de dimensions nettement inférieures aux microvolumes réalisables actuellement, par exemple quelques dizaines de nm, de façon économique et sur de grandes surfaces. En outre, ces microstructures sont organisées selon un plan prédéterminé au lieu d'être réparties au hasard.The present invention has been designed to allow the production of microstructures that may include microvolumes of dimensions significantly smaller than microvolumes currently achievable, for example a few tens of nm, economically and over large areas. In addition, these microstructures are organized according to a predetermined plan instead of being randomly distributed.

L'invention propose un procédé de réalisation, de micro- ou de nanostructures, qui s'applique à des matériaux cristallins, qu'ils soient semiconducteurs, conducteurs ou diélectriques.The invention proposes a process for producing micro- or nanostructures, which applies to crystalline materials, whether they are semiconductors, conductors or dielectrics.

L'invention a donc pour objet un procédé de réalisation de micro- ou de nanostructure sur un support, caractérisé en ce qu'il comporte les étapes suivantes :

  • collage par mise en contact d'une face d'une première plaquette en matériau cristallin avec une face d'une deuxième plaquette en matériau cristallin, de façon que les réseaux cristallins présentés par lesdites faces présentent au moins un paramètre de désaccord apte à permettre la formation d'un réseau de défauts cristallins et/ou d'un réseau de contraintes au sein d'une zone cristalline s'étendant de part et d'autre de l'interface des deux plaquettes, au moins l'un desdits réseaux définissant la micro- ou la nanostructure,
  • amincissement de l'une des deux plaquettes pour faire apparaître le réseau de défauts et/ou le réseau de contraintes sur un support constitué par l'autre plaquette et traitement sélectif du réseau de défauts cristallins et/ou du réseau de contraintes.
The subject of the invention is therefore a process for producing a micro- or nanostructure on a support, characterized in that it comprises the following steps:
  • bonding by contacting a face of a first wafer of crystalline material with a face of a second wafer of crystalline material, so that the crystal lattices presented by said faces have at least one detuning parameter capable of enabling the forming a network of crystalline defects and / or a network of stresses within a crystalline zone extending on either side of the interface of the two wafers, at least one of said networks defining the micro- or nanostructure,
  • thinning of one of the two wafers to reveal the network of defects and / or the network of constraints on a support constituted by the other wafer and selective treatment of the lattice of crystalline defects and / or the network of constraints.

Le paramètre de désaccord peut être constitué par un angle déterminé de décalage en rotation des réseaux cristallins présentés par lesdites faces. Le réseau de défauts obtenu, dit de "twist" est un réseau de dislocations à caractère vis.The disagree parameter can be constituted by a given angle of offset in rotation of the crystal lattices presented by said faces. The network of defects obtained, called "twist" is a network of dislocations to character screws.

Le paramètre de désaccord peut aussi être constitué par une différence de paramètre de maille cristalline entre les matériaux cristallins des faces des plaquettes mises en contact le réseau de défauts obtenu est dit de "misfit".The disagreement parameter can also be constituted by a difference in crystal lattice parameter between the crystalline materials of the faces of the wafers put in contact with the resulting defect network is called "misfit".

Le paramètre de désaccord peut encore être constitué par un angle déterminé selon lequel la face d'au moins l'une des plaquettes est décalée par rapport au plan cristallographique simple de direction correspondant à cette face. Les faces cristallines désorientées (une seule ou les deux) par rapport à un plan cristallographique simple sont dites vicinales. Le réseau de défaut est dit de "miscut".The detuning parameter can also be constituted by a determined angle according to which the face of at least one of the platelets is offset with respect to the single crystallographic plane of direction corresponding to this face. The disoriented crystalline faces (one or both) with respect to a simple crystallographic plane are called vicinal. The fault network is called "miscut".

Toutes les combinaisons de paramètres de désaccord sont possibles, par exemple en collant deux matériaux différents et décalés en rotation. Plusieurs réseaux sont alors formés.All combinations of mismatch parameters are possible, for example by gluing two different materials and offset in rotation. Several networks are then formed.

La mise en contact peut être préférentiellement du type hydrophobe, c'est-à-dire à collage direct des faces desdites plaquettes. Elle peut être du type hydrophile, c'est-à-dire impliquant une fine couche intermédiaire, par exemple une couche d'oxyde formée naturellement sur une face d'une plaquette ou sur les faces des plaquettes.The contacting may preferably be hydrophobic type, that is to say, direct bonding of the faces of said wafers. It may be of the hydrophilic type, that is to say involving a thin intermediate layer, for example an oxide layer formed naturally on one face of a wafer or on the faces of the wafers.

Avantageusement, le procédé comporte en outre au moins une étape de traitement thermique destinée soit à compléter la formation du réseau de défauts cristallins et/ou du réseau de contraintes si la mise en contact est insuffisante pour l'achever, soit à l'achever complètement. De plus, ce traitement peut être apte à renforcer les liaisons interatomiques entre les faces des plaquettes mises en contact. Ce traitement thermique peut être réalisé avant ou après l'étape d'amincissement.Advantageously, the method also comprises at least one heat treatment step intended either to complete the formation of the crystal defect network and / or the constraint network if the contacting is insufficient to complete it, or to complete it completely. . In addition, this treatment may be able to reinforce the interatomic bonds between the faces of the platelets put in contact. This heat treatment can be performed before or after the thinning step.

L'étape d'amincissement peut être réalisée au moyen d'une technique choisie parmi la rectification, l'abrasion mécanique ou l'abrasion chimique.The thinning step may be carried out using a technique chosen from grinding, mechanical abrasion or chemical abrasion.

L'étape d'amincissement peut aussi être réalisée par clivage de l'une des plaquettes qui, avant l'étape de mise en contact a été soumise, au travers de sa face à mettre en contact, à une étape d'implantation ionique destinée à créer, à une profondeur déterminée et correspondant à l'amincissement désirée, une couche de microcavités susceptible de générer un plan de clivage lors d'une étape postérieure de traitement thermique. L'implantation ionique peut être réalisée au moyen d'ions hydrogène. Dans le cas où l'étape d'amincissement est ainsi réalisée, il peut être prévu au moins une étape de traitement thermique permettant simultanément de compléter ou d'achever la formation du réseau de défauts cristallins et/ou du réseau de contraintes, de renforcer les liaisons interatomiques entre les faces des plaquettes mises en contact et de générer le plan de clivage.The thinning step may also be carried out by cleaving one of the platelets which, before the contacting step has been subjected, through its contacting face, to an ion implantation step intended to create, at a determined depth and corresponding to the desired thinning, a layer of microcavities capable of generating a cleavage plane during a subsequent heat treatment step. The ion implantation can be carried out by means of hydrogen ions. In the case where the thinning step is thus performed, it can be provided at least one heat treatment step simultaneously making it possible to complete or complete the formation of the lattice of crystalline defects and / or the network of stresses, to reinforce the interatomic bonds between the faces of the platelets contacted and generate the cleavage plane.

En fonction des utilisations auxquelles la micro- ou la nanostructure est destinée, après l'étape d'amincissement, il peut être prévu une étape consistant à traiter sélectivement le réseau de défauts cristallins et/ou le réseau de contraintes par rapport à ladite zone cristalline. Ceci permet en particulier d'accentuer la différence de comportement physique/électrique ou optoélectronique des défauts cristallins par rapport à ladite zone cristalline ou, de façon plus générale, de délimiter des micro- ou nanovolumes dans ou au-dessus de la zone cristalline. Cette étape de traitement sélectif peut consister à rendre conducteurs les défauts cristallins et/ou le réseau de contraintes de manière que ladite zone cristalline forme des plots cristallins reliés électriquement entre eux. Dans ce cas, on peut procéder à une diffusion de phosphore qui diffuse préférentiellement au niveau des défauts cristallins. L'étape de traitement sélectif peut aussi consister en une isolation électrique afin que ladite zone cristalline forme des plots cristallins isolés électriquement entre eux. Dans ce cas, on peut procéder à une attaque chimique du réseau de défauts cristallins et/ou du réseau de contraintes, éventuellement suivie du dépôt d'un isolant électrique. L'attaque chimique peut être précédée d'une phase de décoration de défauts cristallins et/ou du réseau de contraintes par précipitation d'impuretés métalliques ou dopantes.Depending on the uses for which the micro- or nanostructure is intended, after the thinning step, it may be provided a step of selectively treating the lattice of crystalline defects and / or the stress network with respect to said crystalline zone . This makes it possible in particular to accentuate the difference in physical / electrical or optoelectronic behavior of the crystalline defects with respect to said crystalline zone or, more generally, to delimit micro- or nanovolumes in or above the crystalline zone. This selective treatment step may consist of conductive crystalline defects and / or the network of stresses so that said crystalline zone forms crystalline pads electrically connected to each other. In this case, it is possible to carry out a phosphorus diffusion which diffuses preferentially at the level of the crystalline defects. The selective treatment step may also consist of electrical insulation so that said crystalline zone forms crystalline pads electrically insulated from each other. In this case, it is possible to etch the crystal defect network and / or the stress network, possibly followed by the deposition of an electrical insulator. The chemical etching may be preceded by a crystalline defects decoration phase and / or the stress network by precipitation of metal impurities or dopants.

Le réseau de défauts produit par les techniques indiquées ci-dessus s'étend une faible épaisseur de part et d'autre de la surface de collage des deux plaquettes. Par contre, les contraintes induites par ces défauts s'étendent de chaque côté de l'interface, dans les plaquettes, sur des distances de l'ordre de grandeur de la période des dislocations. Ainsi, l'amincissement de l'une des plaquettes peut se faire en arrêtant l'opération à une distance de l'interface qui est du même ordre de grandeur. A la surface ainsi exposée, et avant d'être parvenu sur les défauts cristallins, le champ de contraintes en surface est non uniforme et est à l'image de réseau de défauts sous-jacent. L'étape de traitement sélectif peut alors consister à déposer, par exemple par épitaxie, un matériau cristallin désaccordé en maille cristalline avec le matériau cristallin révélé par l'étape d'amincissement, ce matériau cristallin déposé formant un ensemble ordonné d'îlots en correspondance avec le réseau de défauts cristallins sous-jacent.The network of defects produced by the techniques indicated above extends a small thickness on either side of the bonding surface of the two wafers. On the other hand, the stresses induced by these defects extend on each side of the interface, in the wafers, over distances of the order of magnitude of the dislocation period. Thus, the thinning of one of the platelets can be done by stopping the operation at a distance from the interface which is of the same order of magnitude. At the surface thus exposed, and before reaching the crystalline defects, the surface stress field is nonuniform and is in the image of the underlying defect network. The selective treatment step can then consist in depositing, for example by epitaxy, a crystalline crystal detuned crystalline material with the crystalline material revealed by the thinning step, this deposited crystalline material forming an ordered set of islands in correspondence with the lattice of underlying crystal defects.

L'isolation électrique du traitement sélectif peut être du type où une conduction électrique peut y avoir lieu par un effet physique tel que l'effet tunnel ou l'effet Fowler-Nordheim.The electrical isolation of the selective treatment may be of the type where electrical conduction can take place by a physical effect such as the tunnel effect or the Fowler-Nordheim effect.

L'étape de traitement sélectif peut aussi consister à traiter les défauts cristallins et/ou le réseau de contraintes de manière que ladite zone cristalline forme des plots cristallins reliés entre eux par des zones semiconductrices ou présentant une barrière de potentiel.The selective treatment step can also consist in treating the crystalline defects and / or the network of stresses so that said crystalline zone forms crystalline pads connected to each other by semiconductor zones or having a potential barrier.

L'invention a aussi pour objet une micro- ou nanostructure sur un support, caractérisée en ce qu'elle est obtenue selon le procédé décrit ci-dessus à partir de plaquettes dont les faces à mettre en contact sont en matériaux semiconducteurs. Au moins l'une de ces faces à mettre en contact peut être en SiC ou en matériau semiconducteur III-V tel que AsGa ou GaAlAs.The subject of the invention is also a micro- or nanostructure on a support, characterized in that it is obtained according to the method described above from platelets whose faces to be in contact are made of semiconductor materials. At least one of these faces to be contacted may be SiC or III-V semiconductor material such as AsGa or GaAlAs.

L'invention a encore pour objet une micro-ou nanostructure sur un support, caractérisée en ce qu'elle est obtenue selon le procédé décrit ci-dessus, l'une des plaquettes étant constituée d'une plaquette Silicium-Sur-Isolant, l'autre plaquette étant en silicium et constituant la plaquette amincie, le procédé permettant l'obtention d'une micro- ou d'une nanostructure constituée de microvolumes de silicium sur une couche d'isolant.The subject of the invention is also a micro-or nanostructure on a support, characterized in that it is obtained according to the method described above, one of the wafers consisting of a silicon-on-insulator wafer, Another wafer being made of silicon and constituting the thinned wafer, the method making it possible to obtain a micro- or nanostructure consisting of microvolumes of silicon on an insulating layer.

L'invention est telle que définie dans les revendications.The invention is as defined in the claims.

Brève description des dessinsBrief description of the drawings

L'invention sera mieux comprise et d'autres avantages et particularités apparaîtront à la lecture de la description qui va suivre, donnée à titre d'exemple non limitatif, accompagnée des dessins annexés parmi lesquels :

  • la figure 1A représente deux plaquettes de matériau cristallin lors de leur mise en contact, selon une première variante du procédé de réalisation de la présente invention,
  • la figure 1B représente deux plaquettes de matériau cristallin lors de leur mise en contact, selon une seconde variante du procédé de réalisation de la présente invention,
  • la figure 1C représente deux plaquettes de matériau cristallin lors de leur mise en contact, selon une troisième variante du procédé de réalisation de la présente invention,
  • la figure 2 est une vue de côté d'un ensemble formé des deux plaquettes de la figure 1A après leur mise en contact,
  • la figure 3 est une vue de côté de l'ensemble représenté à la figure 2, après l'étape d'amincissement du procédé selon la présente invention,
  • la figure 4 est une vue de côté d'une microstructure obtenue par la présente invention,
  • la figure 5 est une vue de côté d'une autre microstructure obtenue par la présente inivention.
The invention will be better understood and other advantages and particularities will appear on reading the description which follows, given as a non-limiting example, accompanied by the appended drawings among which:
  • the Figure 1A represents two platelets of crystalline material when they come into contact, according to a first variant of the embodiment method of the present invention,
  • the Figure 1B represents two platelets of crystalline material when they come into contact, according to a second variant of the embodiment method of the present invention,
  • the figure 1C represents two platelets of crystalline material when they come into contact, according to a third variant of the embodiment method of the present invention,
  • the figure 2 is a side view of a set of two platelets of the Figure 1A after they are put in contact,
  • the figure 3 is a side view of the assembly shown in the figure 2 after the step of thinning the process according to the present invention,
  • the figure 4 is a side view of a microstructure obtained by the present invention,
  • the figure 5 is a side view of another microstructure obtained by the present invention.

Description détaillée de modes de réalisation de l'inventionDETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

Les figures 1A, 1B et 1C illustrent trois variantes de mise en oeuvre du procédé selon la présente invention. X1, X2 et X3 représentent les axes cristallographiques. Dans le cas de la figure 1A, le paramètre qui règle la densité de défauts (ou la distance moyenne entre défauts) est l'angle de rotation β existant entre les réseaux cristallins présentés par les faces mises en contact des plaquettes 1 et 2. Dans le cas de la figure 1B, le paramètre qui règle la densité de défauts (ou la distance moyenne entre défauts) est l'angle de rotation α existant entre les plans cristallographiques des plaquettes 101 et 102 mises sen contact. Dans le cas de la figure 1C, le paramètre qui règle la densité de défauts (ou la distance moyenne entre défauts) est le désaccord de maille f1 entre les deux matériaux cristallins des plaquettes 201 et 202 mises en contact.The FIGS. 1A, 1B and 1C illustrate three variants of implementation of the method according to the present invention. X 1 , X 2 and X 3 represent the crystallographic axes. In the case of Figure 1A , the parameter that adjusts the defect density (or the average distance between defects) is the angle of rotation β existing between the crystal lattices presented by the faces contacted platelets 1 and 2. In the case of the Figure 1B the parameter which regulates the density of defects (or the average distance between defects) is the angle of rotation α existing between the crystallographic planes of the plates 101 and 102 contacted. In the case of figure 1C , the parameter that adjusts the defect density (or the average distance between defects) is the mesh mismatch f 1 between the two crystalline materials of the platelets 201 and 202 contacted.

Le tableau ci-dessous donne les valeurs de l'angle de rotation β, de l'angle de désorientation α et du désaccord de maille f1 en fonction de la période p du réseau de défauts à l'interface (cas du silicium 100). Période (nm) 76 38,4 19,2 9,6 3,8 α ((°) 0,2 0,4 0,8 1,6 4 β(°) 0,29 0,6 1,2 2,4 6 f1 (%) 0,5 1 2 4 10 The table below gives the values of the angle of rotation β, the disorientation angle α and the mesh mismatch f 1 as a function of the period p of the defect network at the interface (case of silicon 100) . Period (nm) 76 38.4 19.2 9.6 3.8 α ((°) 0.2 0.4 0.8 1.6 4 β (°) 0.29 0.6 1.2 2.4 6 f 1 (%) 0.5 1 2 4 10

A titre d'exemple, pour la variante du procédé illustré par la figure 1A, deux plaquettes de silicium (100) collées avec une rotation β de 1,2° forment à leur interface un réseau de dislocations vis carré de période 19,2 nm. Après amincissement de l'une des plaquettes jusqu'à p/2 = 9,6 nm et après révélation par l'une des techniques décrites, on obtient une densité de nanostructures de 2,7.1015/m2 et ayant une taille inférieure à 9,6 nm.By way of example, for the variant of the process illustrated by the Figure 1A , two silicon wafers (100) bonded with a β rotation of 1.2 ° form at their interface a 19.2 nm square screw dislocation lattice. After thinning of one of the platelets up to p / 2 = 9.6 nm and after revelation by one of the techniques described, a density of nanostructures of 2.7 × 10 15 / m 2 and having a size less than 9.6 nm.

Pour obtenir une période de 19,2 nm avec la variante du procédé illustrée par la figure 1B, on peut préparer l'une des plaquettes avec une face vicinale décalée dans la direction <100> de 0,8° et collée sur une plaquette de silicium (100) non vicinale. Les densités de nanostructures obtenues sont alors de 2,7.1015/m2.To obtain a period of 19.2 nm with the variant of the process illustrated by the Figure 1B one of the platelets can be prepared with a vicinal side shifted in the <100> direction of 0.8 ° and glued on a non-vicinal silicon wafer (100). The densities of nanostructures obtained are then 2.7 × 10 15 / m 2 .

Pour la variante du procédé illustrée par la figure 1C, une plaquette de silicium (100) est collée à une deuxième plaquette comportant en surface une couche de SiGe. Le désaccord f1 étant de 2,1% il se forme un réseau d'interface de dislocation coin de période 20 nm. Après amincissement de la plaquette comportant la couche de SiGe jusqu'à environ 10 nm, et après révélation par l'une des techniques décrites, on obtient une densité de nanostructures du même ordre de grandeur que précédemment. Le collage d'une plaquette de germanium produirait un désaccord double et donc une densité de nanostructures quatre fois plus élevé.For the variant of the process illustrated by the figure 1C a silicon wafer (100) is adhered to a second wafer having a SiGe layer on its surface. Since the mismatch f 1 is 2.1%, a 20 nm corner dislocation interface grating is formed. After thinning the wafer comprising the SiGe layer to approximately 10 nm, and after revelation by one of the described techniques, a density of nanostructures of the same order of magnitude as above is obtained. The bonding of a germanium wafer would produce a double clash and thus a density of nanostructures four times higher.

Des faces autres que des faces (100) peuvent être utilisées. Par exemple les faces (111) produisent à leur interface des réseaux hexagonaux ou triangulaires de dislocations. Des faces (110) produisent des réseaux rectangulaires. Deux faces d'orientations différentes, collées l'une sur l'autre, produisent également des réseaux périodiques ou quasi-périodiques.Faces other than faces (100) may be used. For example, the faces (111) produce at their interface hexagonal or triangular networks of dislocations. Faces (110) produce rectangular gratings. Two faces of different orientations, glued to one another, also produce periodic or quasi-periodic networks.

La variante du procédé illustré par la figure 1A va maintenant être décrite plus en détail.The variant of the process illustrated by the Figure 1A will now be described in more detail.

Pour simplifier la description, on considère un réseau de défauts cristallins étant bien entendu qu'il est généralement associé à un réseau de contraintes et que des traitements sélectifs peuvent être également faits sur le réseau de contraintes.To simplify the description, consider a network of crystal defects being of course that it is generally associated with a network of constraints and that selective processing can also be done on the constraint network.

La figure 1A montre deux plaquettes 1 et 2 en silicium de plan cristallographique (1,0,0) lors de leur mise en contact et présentant des faces planes, respectivement 3 et 4, en regard. Les faces planes 3 et 4 ont reçu un traitement de surface pour les rendre hydrophobes. Ceci assurera une mise en contact intime et adhérent des faces 3 et 4. Ce traitement de surface comprend une étape de nettoyage chimique se terminant par exemple par une étape d'attaque à l'acide fluorhydrique. Pour plus de détails, on pourra se reporter au chapitre " Silicon Surface Chemical Composition and Morphology" par Gregg S. HIGASHI et Yves J. CHABAL, pages 433 et suivantes de l'ouvrage " Handbook of Semiconductor Wafer Cleaning Technology", publié sous la direction de Werner KERN chez Noyes Publications, Park Ridge, New Jersey, USA .The Figure 1A shows two platelets 1 and 2 in silicon of crystallographic plane (1,0,0) when they come into contact and having plane faces, respectively 3 and 4, facing each other. The flat faces 3 and 4 received a surface treatment to make them hydrophobic. This will ensure an intimate and adherent contact of the faces 3 and 4. This surface treatment comprises a chemical cleaning step ending for example by a hydrofluoric acid etching step. For more details, we can refer to the chapter " Silicon Surface Chemical Composition and Morphology "by Gregg S. HIGASHI and Yves J. CHABAL, pages 433 and following of the book " Handbook of Semiconductor Wafer Cleaning Technology ", edited by Werner KERN at Noyes Publications, Park Ridge, New Jersey, USA .

On effectue une mise en contact des faces 3 et 4 avec collage par adhésion moléculaire, par exemple à température ambiante, en veillant que les réseaux cristallins présentés par les deux faces soient décalés l'un par rapport à l'autre d'un angle β déterminé, par exemple 0,6°.The faces 3 and 4 are brought into contact with adhesion by molecular adhesion, for example at ambient temperature, ensuring that the crystal lattices presented by the two faces are offset relative to one another by an angle β determined, for example 0.6 °.

L'ensemble constitué par ces deux plaquettes solidarisées est alors soumis à un traitement thermique à une température de l'ordre de 950°C pendant environ 30 minutes. Lors de ce traitement thermique, des liaisons interatomiques plus fortes et plus nombreuses s'établissent entre les deux plaquettes. En raison de l'angle de torsion existant entre les deux réseaux cristallins, un réseau de défauts cristallins, par exemple un réseau de dislocations, s'établit au voisinage de l'interface entre les deux plaquettes, dans une couche de faible épaisseur (quelques dizaines à quelques centaines de nm) centrée sur l'interface. Ceci est représenté schématiquement sur la figure 2 où la référence 5 désigne cette interface, les défauts cristallins (ou dislocations) étant figurés sous la référence 6.The assembly constituted by these two inserts is then subjected to a heat treatment at a temperature of about 950 ° C for about 30 minutes. During this heat treatment, stronger and more numerous interatomic bonds are established between the two platelets. Due to the torsion angle existing between the two crystal lattices, an array of crystal defects, for example a dislocation lattice, is established in the vicinity of the interface between the two platelets, in a thin layer (a few tens to a few hundred nm) centered on the interface. This is schematically represented on the figure 2 where the reference 5 designates this interface, the crystalline defects (or dislocations) being represented under the reference 6.

L'expérience montre que ces dislocations forment un réseau régulier bidimensionnel (carré dans l'exemple donné ici) de pas d'environ 40 nm. Ces faits sont expliqués de manière théorique dans l'article " TEM Observations on Grain Boundaries in Sintered Silicon" de H. FOLL et D. AST, paru dans la revue Philosophical Magazine A, 1979, vol. 40, N° 5, pages 589-610 . La page 596 de cet article reproduit une photographie d'un tel réseau de dislocations.Experience shows that these dislocations form a regular two-dimensional network (square in the example given here) of steps of about 40 nm. These facts are explained theoretically in the article " TEM Observations on Grain Boundaries in Sintered Silicon "by H. FOLL and D. AST, published in the journal Philosophical Magazine A, 1979, vol 40, No. 5, pages 589-610 . Page 596 of this article reproduces a photograph of such a network of dislocations.

L'espacement entre deux dislocations adjacentes est fonction de l'angle β de rotation des réseaux cristallins des deux plaquettes. La valeur de cet espacement varie comme l'inverse de sin(β/2). Pour β= 5°, on obtient un espacement entre dislocations adjacentes de 4,4 nm.The spacing between two adjacent dislocations is a function of the β rotation angle of the crystal lattices of the two platelets. The value of this spacing varies as the inverse of sin (β / 2). For β = 5 °, a spacing between adjacent dislocations of 4.4 nm is obtained.

Pour obtenir une microstructure à partir de l'ensemble représenté à la figure 2, il suffit alors d'abraser (par rectification, abrasion mécanique ou chimique) l'une des deux plaquettes en arrêtant l'opération d'abrasion lorsque la zone de dislocations est atteinte. C'est ce que montre la figure 3 où la microstructure est désignée sous la référence 7. Elle repose sur un support 10 constitué par la plus grande partie de la plaquette 2.To obtain a microstructure from the assembly shown in FIG. figure 2 it is then sufficient to abrade (by grinding, mechanical or chemical abrasion) one of the two plates by stopping the abrasion operation when the dislocation zone is reached. This is what the figure 3 where the microstructure is designated as 7. It rests on a support 10 constituted by the greater part of the wafer 2.

Un traitement de surface peut ensuite être mis en oeuvre pour différencier, de manière plus spécifique, les défauts cristallins de la zone cristalline 8 environnante.A surface treatment can then be implemented to differentiate, more specifically, the crystalline defects of the surrounding crystalline zone 8.

On peut, par exemple, au moyen d'un bain chimique attaquer sélectivement les défauts cristallins 6 sans attaquer la zone cristalline 8 adjacente. Dans l'exemple de réalisation donné ici, on peut utiliser les bains chimiques SECCO® ou WRIGHT®. On obtient alors un réseau de microvolumes de silicium de forme carrée, suivant un réseau au pas p de 40 nm, isolés les uns des autres par des espacements.It is possible, for example, by means of a chemical bath to selectively attack the crystalline defects 6 without attacking the adjacent crystalline zone 8. In the exemplary embodiment given here, it is possible to use the SECCO ® or WRIGHT ® chemical baths. A square-shaped silicon microvolume array is then obtained, following a 40 nm pitch network, isolated from each other by spacings.

Une isolation diélectrique latérale des microvolumes 9 peut être effectuée. Pour cela on peut, par exemple, oxyder thermiquement la microstructure 7
ou effectuer un dépôt CVD. Pour certaines applications, la couche d'oxyde déposée sur la microstructure 7 peut être arasée, comme cela est représenté sur la figure 4, pour ne garder qu'un dépôt d'isolant 11 entre les microvolumes 9. Dans ce cas, on obtient un réseau de matériau isolant se substituant au réseau de dislocations.Lateral dielectric isolation of microvolumes 9 can be performed. For this purpose, it is possible, for example, to thermally oxidize the microstructure 7
or make a CVD deposit. For some applications, the oxide layer deposited on the microstructure 7 may be leveled, as shown in FIG. figure 4 , to keep only a deposit of insulation 11 between the microvolumes 9. In this case, we obtain a network of insulating material replacing the dislocation network.

Le traitement de surface peut aussi être mené pour rendre le réseau de dislocations conducteur, isolant, voire semiconducteur en fonction de l'application visée. Ceci permet de rendre les microvolumes ou plots cristallins, soit reliés électriquement entre eux par des liaisons conductrices, soit isolés électriquement, soit reliés par des zones semi-conductrices ou présentant une barrière de potentiel. Concernant l'isolation électrique, on comprend aussi des isolations telles que la conduction électrique à travers les parties isolantes peut avoir lieu par effet tunnel par exemple, ou par effet Fowler-Nordheim ou par tout autre effet physique. Pour rendre conducteur le réseau de dislocations, on peut réaliser une diffusion de phosphore qui diffuse préférentiellement au niveau des dislocations.Surface treatment can also be carried out to make the dislocation network conductive, insulative, or even semiconductor depending on the intended application. This makes it possible to make the microvolumes or pads crystalline, either electrically connected to one another by conductive bonds, or electrically isolated, or connected by semiconductor zones or having a potential barrier. With regard to the electrical insulation, insulations such as electrical conduction through the insulating parts can also take place by tunnel effect for example, or by the Fowler-Nordheim effect or by any other physical effect. To make the dislocation network conductive, it is possible to carry out a phosphorus diffusion which diffuses preferentially at the level of the dislocations.

Une autre possibilité de réaliser l'étape d'amincissement consiste à appliquer le procédé décrit dans le document FR-A-2 681 472 de manière à obtenir un clivage de la plaquette concernée. Pour cela, on implante par exemple des protons dans cette plaquette pour obtenir une couche de microcavités à la profondeur voulue de la face à mettre en contact. Cette face subit le traitement de nettoyage et de collage. Le traitement thermique est ensuite appliqué. Il permet de générer simultanément la création de dislocations et le clivage selon la couche de microcavités.Another possibility of carrying out the thinning step consists in applying the process described in the document FR-A-2,681,472 in order to obtain a cleavage of the wafer concerned. For this purpose, for example, protons are implanted in this wafer to obtain a layer of microcavities at the desired depth of the face to be brought into contact. This face undergoes the cleaning and bonding treatment. The heat treatment is then applied. It allows to generate simultaneously the creation of dislocations and cleavage according to the layer of microcavities.

L'une des plaquettes, celle destinée à constituer le support, peut être une plaquette SSI (Silicium-Sur-Isolant) appelée SOI ("Silicon on Insulator") dans la terminologie anglo-saxonne et l'autre plaquette peut être un substrat massif de silicium. Le procédé selon l'invention procure alors un réseau de microvolumes de silicium sur une couche d'isolant.One of the wafers, that intended to constitute the support, may be an SSI (Silicon-On-Insulator) wafer called SOI ("Silicon on Insulator") in the English terminology and the other wafer may be a solid substrate. of silicon. The method according to the invention then provides a network of microvolumes of silicon on an insulating layer.

Les deux plaquettes de matériau cristallin peuvent être de nature différente, par exemple une plaquette de silicium et une plaquette d'arséniure de gallium, ou une plaquette de silicium et une plaquette de germanium. Par ailleurs, les plaquettes ne sont pas forcément homogènes. Il suffit simplement que les faces à mettre en contact soient en matériau cristallin, le reste des plaquettes pouvant présenter d'autres structures.The two platelets of crystalline material may be of a different nature, for example a silicon wafer and a gallium arsenide wafer, or a silicon wafer and a germanium wafer. In addition, platelets are not necessarily homogeneous. It suffices simply that the faces to be brought into contact are of crystalline material, the rest of the wafers may have other structures.

Comme il a été dit plus haut, la micro- ou la nanostructure peut encore être obtenue à partir d'un réseau de contraintes. Ce réseau de contraintes peut être révélé par diverses techniques.As mentioned above, the micro- or nanostructure can still be obtained from a network of constraints. This network of constraints can be revealed by various techniques.

Le réseau de contraintes peut être révélé par dépôt, par un procédé d'épitaxie (MOCVD, MBE, épitaxie en phase liquide...), sur la plaquette amincie d'un matériau cristallin désaccordé en maille cristalline. Dans le mode de croissance en îlots, les sites de nucléation préférentiels fournis par les zones en compression (respectivement en tension) seront favorables pour les dépôts à mailles plus petites (respectivement plus grandes) que la plaquette amincie. Il sera ainsi formé un ensemble ordonné d'îlots de taille correspondant au réseau sous-jacent.The constraint network can be revealed by deposition, by an epitaxial process (MOCVD, MBE, liquid phase epitaxy ...), on the thinned plate of a crystalline mesh detuned crystalline material. In the island growth mode, the preferential nucleation sites provided by the zones in compression (respectively in tension) will be favorable for the smaller (respectively larger) mesh deposits than the thinned plate. An ordered set of islands of size corresponding to the underlying network will thus be formed.

Ce dépôt peut être illustré à partir de la variante du procédé illustrée par la figure 1C. Un ensemble a été préparé selon cette variante, comme décrit plus haut, à partir d'une plaquette de silicium d'orientation (100) et une plaquette comportant la couche de SiGe. Après amincissement, on obtient l'ensemble représenté à la figure 5 où la référence 202 désigne la plaquette de silicium et la référence 201' ce qui reste de la couche de SiGe. Un dépôt de germanium pur est effectué en conditions de croissance de Stranski-Krastanov. Des îlots de germanium nanométriques 210 sont nucléés à l'aplomb des noeuds du réseau de dislocations, dans les zones de contraintes en tension.This deposit can be illustrated from the variant of the process illustrated by the figure 1C . An assembly has been prepared according to this variant, as described above, from an orientation silicon wafer (100) and a wafer comprising the SiGe layer. After thinning, we obtain the assembly represented at figure 5 where reference 202 designates the silicon wafer and the reference 201 'remains of the SiGe layer. A deposit of pure germanium is carried out under Stranski-Krastanov growth conditions. Nano-sized germanium islands 210 are nucleated vertically above the nodes of the dislocation network, in the stress-stress zones.

Claims (25)

  1. Method for producing a micro or nanostructure on a substrate, characterized in that it comprises the following steps :
    - bonding by placing one surface (3) of a first wafer (1) in crystalline material in contact with one surface (4) of a second wafer (2) in crystalline material, such that the crystalline lattices presented by said surfaces offer at least one mismatch parameter able to allow the formation of a lattice of crystalline defects (6) and/or a lattice of strains within a crystalline zone (8) extending either side of the interface of the two wafers, at least one of said lattices determining the micro or nanostructure,
    - thinning one of the two wafers to expose the lattice defects and/or lattice strains on a substrate (10) formed by the other wafer,
    - selective treatment of the lattice crystalline defects (6) and/or lattice strains in relation to said crystalline zone (8).
  2. Method according to claim 1, characterized in that said mismatch parameter is formed by a determined angle of rotational shift (θ) in the crystalline lattices presented by said surfaces.
  3. Method according to claim 1, characterized in that said mismatch parameter is formed by a difference in crystalline mesh parameter between the crystalline materials of the contacted surfaces of the wafers.
  4. Method according to claim 1, characterized in that said mismatch parameter is formed by a determined angle (α) according to which the surface of at least one of the wafers is shifted in relation to the ordinary crystallographic plane direction corresponding to this surface.
  5. Method according to any one of claims 1 to 4, characterized in that the contacting is of hydrophobic type.
  6. Method according to any one of claims 1 to 4, characterized in that the contacting is of hydrophilic type.
  7. Method according to any one of claims 1 to 6, characterized in that, during the contacting step, the first wafer and second wafer are submitted to at least one of the following operations : heat treatment, pressurizing, application of an electric field.
  8. Method according to any one of claims 1 to 7, characterized in that it also comprises at least one heat treatment step intended to complete or end the formation of the lattice of crystalline defects and/or lattice strains.
  9. Method according to any one of claims 1 to 8, characterized in that the thinning step is conducted by means of a technique chosen from among grinding, mechanical polishing or chemical polishing.
  10. Method according to any one of claims 1 to 8, characterized in that the thinning step is conducted by cleavage of one of the wafers which, before the contacting step, is subjected via its contacting surface to an ion implantation step intended, at a determined depth corresponding to the required thinning, to create a layer of microcavities able to generate a cleavage plane during a subsequent heat treatment step.
  11. Method according to claim 10, characterized in that ion implantation is made by means of hydrogen ions.
  12. Method according to either of claims 10 or 11, when dependent on claim 7, characterized in that at least one heat treatment step is planned making it possible simultaneously to complete or end the formation of a lattice of crystalline defects and/or lattice of strains and to generate the cleavage plane.
  13. Method according to any of claims 1 to 12, characterized in that the selective treatment step consists of making conductive the crystalline defects (6) and/or the lattice strains such that said crystalline zone (8) forms crystalline pads electrically connected to one another.
  14. Method according to claim 13, characterized in that the crystalline defects (6) are made conductive by phosphorus diffusion.
  15. Method according to any of claims 1 to 12, characterized in that the selective treatment step consists of electric insulation (11) so that said crystalline zone forms crystalline pads (9) electrically insulated from one another.
  16. Method according to claim 15, characterized in that the selective treatment consists of chemically etching the crystalline defects and/or lattice strains.
  17. Method according to claim 16, characterized in that said chemical etching is preceded by a decoration phase of the crystalline defects and/or lattice strains by precipitation of metallic or doping impurities.
  18. Method according to claim 16, characterized in that chemical etching is followed by the depositing of an electric insulator.
  19. Method according to claim 15, characterized in that said electric insulation is of the type in which electric conduction may take place therein by means of a physical effect such as the tunnelling effect or the Fowler-Nordheim effect.
  20. Method according to any of claims 1 to 12, characterized in that the selective treatment step consists of treating the crystalline defects and/or lattice strains such that said crystalline zone forms crystalline pads connected together by semiconductor zones or having a potential barrier.
  21. Method according to any of claims 1 to 12, characterized in that the selective treatment step consists of depositing, by epitaxy, a crystalline material having crystalline mesh mismatch with the crystalline material exposed by the thinning step, this deposited crystalline material forming an arranged set of islands corresponding to the lattice of crystalline defects and/or underlying lattice strains.
  22. Micro or nanostructure on a substrate, characterized in that it is obtained according to any one of claims 1 to 21 from wafers (1,2), one of which has been thinned, these wafers having contacting surfaces(3,4) in semiconductor material, the crystalline lattices presented by said surfaces offering at least one mismatch parameter, the thinned wafer presenting on its surface a lattice of crystalline defects and/or lattice of strains from which arises said micro- or nanostructure.
  23. Micro or nanostructure on a substrate according to claim 22, characterized in that at least one of said contacting surfaces is in SiC.
  24. Micro or nanostructure on a substrate according to claim 21, characterized in that at least one of said contacting surfaces is in III-V semiconductor material such as AsGa or GaAlAs.
  25. Micro or nanostructure on a substrate, characterized in that it is obtained according to any one of claims 1 to 21, one of the wafers being formed by a Silicon-On-Insulator wafer, the other wafer being in silicon and forming the thinned wafer, the method enabling a micro or nanostructure to be obtained made up of silicon microvolumes on an insulator layer.
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