EP0986026A1

EP0986026A1 - Fractal coding of data in the DCT domain

Info

Publication number: EP0986026A1
Application number: EP98830522A
Authority: EP
Inventors: Danilo Pau; Roberto Sannino; Andrea Capasso; Pasqualina Fragneto
Original assignee: STMicroelectronics SRL; SGS Thomson Microelectronics SRL
Current assignee: STMicroelectronics SRL
Priority date: 1998-09-07
Filing date: 1998-09-07
Publication date: 2000-03-15
Also published as: US7233623B1

Abstract

A method of calculating the discrete cosine transform (DCT) of blocks of pixels of a picture includes the steps of defining first subdivision blocks called range blocks, having a fractional and scaleable size N/2ⁱ*N/2ⁱ , where i is an integer number, in respect to a maximum pre-defined size of N*N pixels of blocks of division of said picture, referred to as domain blocks, shiftable by intervals of N/2ⁱ pixels, and of calculating the DCT on 2ⁱ range blocks of subdivision of a domain block of N*N pixels of said picture, in parallel.

Description

FIELD OF APPLICATION OF THE INVENTION

This invention relates in general to digital processing systems for recording and/or transmitting pictures, and more in particular to systems for compressing and coding pictures by calculating the discrete cosine transform (DCT) of blocks of pixels of a picture.

The invention is particularly useful in video coders according to the MPEG2 standard though it is applicable also to other systems.

BACKGROUND OF THE INVENTION

The calculation of the discrete cosine transform (DCT) of a pixel matrix of a picture is a fundamental step in processing picture data. A division by a quantization matrix is performed on the results of the discrete cosine transform for reducing more or less drastically the amplitude of the DCT coefficients, as a precondition to data compression which occurs during a coding phase, according to a certain transfer protocol of video data to be transmitted or stored.

Typically, the calculation of the discrete cosine transform is carried out on blocks or matrices of pixels, in which a whole picture is subdivided for processing purposes.

Increasing speed requisites of picture processing systems for storing and/or transmitting them, impose the use of hardware architectures to speed up various processing steps among which, primarily, the step of discrete cosine transform calculation by blocks of pixels.

Use of hardware processing imposes a pre-definition of few fundamental parameters, namely the dimensions of the blocks of pixels into which a picture is subdivided to meet processing requisites.

Such a pre-definition may represent be a heavy constraint that limits the possibility of optimizing the processing system, for example a MPEG2 coder, or its adaptability to different conditions of use in terms of different performance requisites.

It is also evident the enormous economic advantage in terms of reduction of costs of an integrated data processing system tat may be programmed to calculate in parallel the DCT on several blocks of pixels of size selectable among a certain number of available sizes.

OBJECT AND SUMMARY OF THE INVENTION

It is evident the need and/or usefulness of a method and of a hardware architecture for calculating in parallel the discrete cosine transform (DCT) on a plurality of blocks of pixels, whose architecture provides for the scalability of the size of the blocks of pixels, for example the calculation of the discrete cosine transform (DCT) either for one block of 8x8 pixels, or four blocks of 4x4 pixels in parallel, or for sixteen blocks of 2x2 pixels in parallel, operating a selection of the block's size.

Scalability of the size of the block of pixels and the possibility of performing the calculation of the discrete cosine transform in parallel on blocks of congruently reduced size compared to a certain maximum block's size, by a hardware structure is also instrumental of the implementation of highly efficient "hybrid" picture compression schemes and algorithms.

For example, by virtue of the scalability of the block size and of the ability to calculate in parallel the DCT on more blocks, it is possible, according to the present invention, to implement a fractal coding applied in the DCT domain rather than in the space domain of picture data, as customary.

Therefore, another important aspect of the invention is a new picture data compressing and coding method that practically is made possible by a hardware structure calculating the DCT on blocks of scaleable size and which essentially consists in

subdividing a picture by defining two distinct types of subdivision blocks: a first type, of N/i*N/i dimension called range blocks that essentially are not overimposable one on another, and a second type, of N*N dimension, called domain blocks, that are transferable by intervals of N/i pixels and overimposable one on another (by transferring on the original picture a window that identifies a domain block by an interval equivalent to the horizontal and/or vertical dimension of a range block);
calculating the discrete cosine transform (DCT) of the 2ⁱ range blocks and of a relative domain block in parallel;
classifying the transform range blocks according to their relative complexity calculated by summing the three AC coefficients;
applying the fractal transform in the DCT domain to the data of range blocks whose complexity exceeds a pre-defined threshold and storing only the DC coefficient of the range blocks with a complexity lower than said threshold, identifying a relative domain block belonging to the range block being transformed that produces the best fractal approximation of the same range block and calculating its discrete cosine transform;
calculating a difference picture between each range block and its fractal approximation;
quantizing said difference picture in the DCT domain by using a quantization table predisposed in function of human sight characteristics;
coding said quantized difference picture by a method based on the probability of the quantization coefficients;
storing or transmitting the coding code for each range block compressed in the DCT domain and the DC coefficient of each uncompressed range block.

By indicating with F_R(u,v), the DCT of a generic range block, in the domain of the DCT, the AC coefficients indicate the block's complexity. For the case of N=8, the four coefficients at the top left of the block are:

the DC coefficient that occupies the position 00;
the three AC coefficients that occupy the positions: 01, 10 and 11, respectively.

The AC coefficients are used to decide to which a certain range block belongs: if the sum of their absolute values is less that a determined threshold T, the block range in question is classified as a "low activity" block, on the contrary, if the sum is equal or greater than T, the range block is classified as a "high activity" block.

For a low activity range block, the AC coefficients are small and therefore they may be omitted without significantly affecting fidelity: in this case the block may be approximated by storing only its DC coefficient.

For a high activity range block, the progression of fractal coding of the invention consists of searching two appropriate linear transform, for example, rotations, , overturns, τ or the like and a domain block DCT, of which being defined by F_D(u,v), which at least approximately satisfy the following equation:

Having so identified the domain block most similar or homologous to the range block that is being processed, its parameters F_D (u,v),τ, are stored.

The difference picture between the range block and its fractal position is ten calculated:

By quantizing the difference picture D(u,v),

is obtained, where:

DQ(u,v) is the quantized difference picture in the domain of DCT;
Q(u,v) is a quantization table designed by considering human sight characteristics;
INTEG is a function that approximates its argument to the nearest integer;

After quantization, the majority of the D_Q (u,v) coefficients are null. Therefore, it is easy to design a coding, for example an Huffman coding, based on the probabilities of the coefficients. Finally, the code to be recorded or transmitted is stored. The compression procedure terminates when each range block has been coded.

The object of the present invention is more precisely defined in the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

The different aspects and implementations of the scaleable architecture for calculating the discrete cosine transform of the invention as well as of the novel efficient method of compression and fractal coding, will be more easily understood through the following detailed description of an embodiment of the architecture of the invention and of the different functioning modes according to a selection of the size selection of the blocks of pixels into which the picture is divided by referring to the annexed drawings, wherein:

Figure 1 is a block diagram of a coder effecting hybrid compression based on fractal coding and DCT, according to the present invention;

Figure 2 is a flow chart of the parallel computation of the DCT of sixteen blocks of 2x2-pixel size;

Figure 3 illustrates the architecture for parallel computation of sixteen 2x2 DCT _s ;

Figure 4 shows the arrangement of the input data for calculating the sixteen 2x2 DCT _s ;

Figure 5 shows the PROCESS phase of the calculating procedure of sixteen 2x2 DCT _s ;

Figure 6 illustrates the architecture for parallel computation of four 4x4 DCT _s ;

Figure 7 shows the arrangement of the input data for calculating the four 4x4 DCT _s ;

Figure 8 shows the PROCESS phase of the calculating procedure of four 4x4 DCT _s ;

Figure 9 illustrates the architecture for parallel computation of an 8x8 DCT;

Figure 10 shows the arrangement of the input data for calculating an 8x8 DCT;

Figure 11 shows the PROCESS phase for the calculating procedure of an 8x8 DCT;

Figure 12 shows the scaleable hardware architecture of the invention for calculating an 8x8 DCT or four 4x4 DCT _s in parallel or sixteen 2x2 DCT _s in parallel;

Figure 13 shows the INPUT structure of the scaleable architecture of the invention;

Figure 14 shows the PROCESS structure for the scaleable architecture of the invention;

Figure 15 shows the functional schemes of the blocks that implement the PROCESS phase in the scaleable architecture of the invention;

Figure 16 is a detailed scheme of the QA block;

Figure 17 is a detailed scheme of the QB block;

Figure 18 is a detailed scheme of the QC block;

Figure 19 is a detailed scheme of the QD block;

Figure 20 is a detailed scheme of the QE block;

Figure 21 is a detailed scheme of the QF block;

Figure 22 is a detailed scheme of the QG block;

Figure 23 illustrates an implementation of the ORDER phase in the scaleable architecture of the invention;

Figure 24 illustrates an implementation of the OUTPUT phase in the scaleable architecture of the invention.

Though referring in some of the schemes illustrated in the figures to a particularly significative and effective implementation of the architecture of parallel computation of the discrete cosine transform (DCT) on blocks of pixels of scaleable size, which comprises a compression phase for the fractal coding of the picture data, it is understood that the method and architecture of parallel calculation of the discrete cosine transformed (DCT) of a bidimensional matrix of input data by blocks of a scaleable size, provide for an exceptional freedom in implementing particularly effective compression algorithms by exploiting the scalability and the possibility of a parallel calculation of DCT.

DESCRIPTION OF SEVERAL EMBODIMENTS OF THE INVENTION

The partitioning steps and the calculation of the discrete cosine transform of a bidimensional matrix of input data will be described separately for each size of range block, according to an embodiment of the invention, starting from the smallest block dimension of 2x2 for which the DCT calculation is performed in parallel, up to the maximum block dimension of 8x8.

This description of an architecture scaleable according to needs by changing the value of the global variable size, will follow.

The procedure for a parallel DCT computation of the invention may be divided in distinct phases:

INPUT phase
PROCESS phase
ORDER phase
OUTPUT phase.

Each phase is hereinbelow described for each case considered.

The DCT operation may be defined as follows.

For an input data matrix XN*N =[xi,j ],0≤i,j ≤N -1, the output matrix yN*N =[ym,n ],0≤m,n≤N -1, is defined by:

where:

For convenience, assume that N=2ⁱ , where i is an integer and i≥1. Let's remove ε(m), ε(n), and the normalization value 2/N from equation (4), in view of the fact that they may be reintroduced in a successive step. Therefore, from now on, the following simplified version of equation (4) will be used:

Parallel computation of sixteen 2x2 DCT_s

For N=2 equation (5) becomes:

The flow graph for a 2x2 DCT is shown in Fig. 2, in which A=B=C=1 and the input and output data are the pixels in the positions (0,0),(0,1),(1,0),(1,1).

Let us now consider how to calculate in parallel sixteen 2x2 DCT _s in which an 8x8 block is subdivided.

The procedure is divided in many steps, a global view of which is depicted in Fig. 3.

This figure highlights the transformations performed on the 2x2 block constituted by the pixels (0,6),(0,7),(1,6),(1,7).

The pixel that constitute the input block are ordered in the INPUT phase and are processed in the PROCESS phase to obtain the coefficients of the sixteen bidimensional DCT _s , or briefly 2-D DCT _s , on four samples, for example, the 2-D DCT of the block (0,1) constituted by:

{l[0],m[0],n[0],o[0]} is {a[0],b[0],c[0],d[0]}

The coefficients of the 2-D DCT are re-arranged in the ORDER phase into eight vectors of eight components. For example the coefficients {a[0],b[0],c[0],d[0]} constitute the vector l '.

The vectors thus obtained proceed to the OUTPUT phase to give the coefficients of the 2x2 DCT, constituting the output block.

INPUT phase

The pixels of each block (i,j), with 0≤ i ≤ 1 and 0≤j ≤3, are ordered to the eight-component vectors l, m, n, o in the following manner:

the pixels that occupy the position (0,0) in the block constitute the vector l ;
the pixels that occupy the position (0,1) in the block constitute the vector m ;
the pixels that occupy the position (1,0) in the block constitute the vector n ;
the pixels that occupy the position (1,1) in the block constitute the vector o .

Similarly, the pixels of each block (i,j), with 2 ≤ i ≤ 3 and 0 ≤ i ≤ 3, are ordered to constitute the eight-component vectors p, q, r, s in the following manner:

the pixels that occupy the position (0,0) in the block constitute the vector p ;
the pixels that occupy the position (0,1) in the block constitute the vector q ;
the pixels that occupy the position (1,0) in the block constitute the vector r ;
the pixels that occupy the position (1,0) in the block constitute the vector s .

This arrangement is detailed in Fig. 4.

It should be noted, for example, that the pixels of the block (0,3) will constitute the third component of the l, m, n, o vectors.

PROCESS phase

The PROCESS phase consists in calculating in parallel the sixteen 2-D DCT _s by processing the eight-component vectors l, m, ..., s as shown in Fig. 5. It should be noticed, for example, that the coefficients of the 2-D DCT of the block (0,3) will constitute the third component of the vectors a, b, c, d of Fig. 3.

ORDER phase

The ORDER phase consist in arranging the output sequences of the eight 2-D DCT _s in eight vectors l', m', ..., s' thus defined:

It should be noticed, for example, that the coefficients of the 2-D DCT of the block (0,3) will constitute the

components

4, 5, 6, 7 of the vector m '.

OUTPUT phase

This phase consists in rearranging the output data: starting from the eight-component vectors a, b, ..., h , a 64 component vector defined as follows, is constructed:

Parallel computation of four 4x4 DTCs

For N = 4, equation (5) becomes

If: Y 16*1= y 0 y 1 y 2 y 3 , F 64*1= f 0 f 1 f 2 f 3 where: yi=[yi,0,yi,1,yi,2,yi,3]' {f 0,r }3 r =0 = DCT({A 1,i }3 i =0), {f 2,r }3 r=0 = DCT({B 3,i }3 i=0 {f 1,r }3 r=0 = DCT({A 3,i }3 i=0), {f 3,r}3 r=0 = DCT({B 1,i }3 i=0) {A 1,i }3 i=0 = {x 0,0,x 1,1,x 2,2,x 3,3}, {A 3,i }3 i=0 = {x 1,0,x 3,1,x 0,2,x 2,3}, {B 3,i }3 i=0 = {x 2,0,x 0,1,x 3,2,x 1,3 , {B 1,i }3 i=0 ={x 3,0,x 2,1,x 1,2,x 0,3 it may be demonstrated that:

where:

The matrices (H_i ) ₄ , i=0, 1, 2, 3 are as follows:

The monodimensional DCT, or briefly the 1-D DCT, is expressed by the matrix (1-D DCT)₄ given by:

From these equations it may be said that the computation of one 4x4 DCT may be divided into two steps:

computation of four 1-D DCT, each performed on an appropriate sequence of four pixels.
computation of the 2-D DCT starting from said four 1-D DCT.

These two steps we carried out in a similar manner, and are implemented with the same hardware that is used twice.

Let us consider now how to calculate in parallel four 4x4 DCT _s . The total 64 samples are obtained from the 4x4 blocks into which an 8x8 block is subdivided.

The procedure is subdivided in distinct phases to each of which corresponds an architectural block. A whole view is shown in Fig. 6. This figure highlights the transformations carried out on each 4x4 block.

INPUT phase

The pixel of each quadrant (i,j), 0 ≤ i,j ≤ 1 are ordered to constitute the vectors:

After arranging the data in 16 four-component vectors, we define the eight-component vectors l, m, n, o , constituted by the first, second, third and fourth components, respectively, of the initial vectors constituted by the pixels of the 00 and 01 quadrants, and the p, q, r, s, vectors constituted by the first, second, third and fourth components, respectively, of the initial vectors constituted by the pixels of the 10 and 11 quadrants. Precisely:

By taking into account the way in which the vectors A i,j / 1, A i,j / 3 B i,j / 3, B i,j / 1 are defined, the arrangement detailed in Fig. 7 is obtained. It should be noted that in this figure the original 8x8 block is subdivided in the four 4x4 quadrants, within each quadrant (i,j), the pixels belonging to the respective vectors A i,j / 1, A i,j / 3, B i,j / 3, B i,j / 1 have different shadings in the figure.

According to what has been described above, the computation of a 4x4 DCT may be subdivided in two stages: consequently, the PROCESS phase that is the only phase in which arithmetical operations are performed, is done twice:

a first time, to compute in parallel the sixteen 1-D DCT _s ;
a second time, to compute in parallel four 4x4 DCT starting from the coefficients of the 1-D DCT _s .

The variable stage indicates whether the first or second calculation stage is being performed.

During the INPUT phase the variable stage is updated to the value 0.

At the input in the PROCESS phase, there are 64 input MUX _es that are controlled by the variable stage. Each MUX receives two inputs:

a pixel of the original picture, coming from the INPUT phase (this input is selected when stage = 0);
a coefficient of a 1-D DCT, coming from the ORDER phase (this input is selected when stage = 1).

PROCESS phase

This phase consists in processing the l, m, ..., s vectors as shown in Fig. 8. In this figure the following symbols are used:

At the output of the PROCESS structure there are 64 DEMUX _es controlled by the variable stage. The DEMUX address the data according to two conditions:

if stage = 0, the input datum to each DEMUX is a coefficient of a 1-D DCT; therefore the datum must be further processed and, for this purpose, is conveyed to the ORDER phase;
if stage = 1, the input datum to each DEMUX is a coefficient of a 2-D DCT; therefore the datum must not be processed farther and therefore is conveyed to the OUTPUT phase.

ORDER phase

The ORDER phase consists in ranging the output sequence of the eight 1-D DCT _s in eight l', m', ...,s' vectors, thus defined:

After the ORDER phase the variable stage is updated to the value 1. The output data from the ORDER phase are sent to the PROCESS phase.

OUTPUT phase

This phase consists in rearranging the data originating from the second (stage = 1) execution of the PROCESS step: starting from these data, which constitute the

eight-component vectors: a, b, ..., h, the output block Y_N*N is thus defined:

The main differences between the hardware for calculating the four 4x4 DCT _s and the hardware needed for the sixteen 2x2 DCT _s are the following:

the ordering sequences of the pixels of the block of the original picture depend on the chosen DCT size;
to execute the sixteen 2x2 DCT _s the PROCESS step must be carried out only once; instead, to execute the four 4x4 DCT _s the PROCESS step must be repeated two times;
the operations executed during the PROCESS phase are not always the same for the two cases.

Computation of an 8X8 DCT

For N = 8 equation (5) becomes:

Putting:

where: yi =[yi, 0 yi, 1 ··· yi ,7]' {f 0,r }7 r =0 = DCT({A 1,i }7 i =0), {f 4,r }7 r =0 = DCT({B 7,i } 7 i =0), {f 1,r }7 r =0 = DCT({A 3,i }7 i =0), {f 5,r }7 r =0 = DCT({B 5,i }7 i =0), {f 2,r }7 r =0 = DCT({A 5,i }7 i =0 , {f 6,r }7 r =0 = DCT({B 3,i }7 i =0), {f 3,r }7 r =0 = DCT({A 7,i }7 i =0), {f 7,r }7 r =0 = DCT({B 1,i }7 i =0 , {A 1,i }7 i =0 = {x 0,0 x 1,1 x 2,2 x 3,3 x 4,4 x 5,5 x 6,6 x 7,7 , {A 3,i }7 i =0 = {x 1,0 x 4,1 x 7,2 x 5,3 x 2,4 x 0,5 x 3,6 x 6,7 , {A 5,i }7 i =0 = {x 2,0 x 7,1 x 3,2 x 1,3 x 6,4 x 4,5 x 0,6 x 5,7 , {A 7,i }7 i =0 = {x 3,0 x 5,1 x 1,2 x 7,3 x 0,4 x 6,5 x 2,6 x 4,7 , {B 7,i }7 i =0 = {x 4,0 x 2,1 x 6,2 x 0,3 x 7,4 x 1,5 x 5,6 x 3,7 , {B 5,i }7 i =0 = {x 5,0 x 0,1 x 4,2 x 6,3 x 1,4 x 3,5 x 7,6 x 2,7}, {B 3,i }7 i =0 = {x 6,0 x 3,1 x 0,2 x 2,3 x 5,4 x 7,5 x 4,6 x 1,7}, {B 1,i }7 i =0 = {x 7,0 x 6,1 x 5,2 x 4,3 x 3,4 x 2,5 x 1,6 x 0,7} it may be demonstrated that:

where:

the matrices (Hi)s i = 0, 1, ..., 7 have the following expressions:

The 1-D DCT is expressed by the matrix:

Where we put: Cm n = cos( m n π)

From the above equations it is evident that the computation of an 8x8 DCT may be subdivided in two stages:

calculating eight 1-D DCTs, each for a certain sequence of eight pixels;
calculating the 2-D DCT, starting from the eight 1-D DCT _s .

These two stages may be executed through the same hardware using it twice.

The processing is subdivided in different steps, to each of which corresponds an architectural block. A whole view of the hardware is shown in Fig. 9.

INPUT phase

The pixels of the 8x8 input block are ordered to constitute the eight-component vectors l, m, n, o, p, q, r, s:

By taking into account the way in which the vectors A ₁, A ₃, A ₅, A ₇, B ₇, B ₅ , B ₃, B ₁ are defined, we obtain the detailed arrangement of Fig. 10. It should be noticed that in this figure the pixels belonging to the vectors A ₁, A ₃, A ₅, A ₇, B ₇, B ₅, B ₃, B ₁ are countersigned by different shadings.

As shown above, the computation of an 8x8 DCT may be subdivided into two stage. The PROCESS step, which is the only phase in which mathematical operations are performed, is performed twice:

the first time, to compute in parallel sixteen 1-D DCT _s ;
the second time, to compute the 8x8 DCT starting from the coefficients of the sixteen 1-D DCT _s .

The variable stage indicates whether the first or second calculation step is being performed.

During the INPUT phase, the variable stage is updated to the value 0.

At the input of the PROCESS structure, there are 64 MUX _es controlled by the variable stage. Each MUX receives two inputs:

a pixel of the original picture, originating from the INPUT phase (this input is selected when stage = 0);
a coefficient of a 1-D DCT, originating from the ORDER phase (this input is selected when stage = 1).

PROCESS phase

This phase consists in processing the l, m, ..., s vectors as shown in Fig. 11. In this figure, the following symbols are used:

At the output of the PROCESS structure there are 64 DEMUX _es controlled by the variable stage. The DEMUX _es address the data according to two possibilities:

if stage = 0, the input datum to each DEMUX is a coefficient of a 1-D DCT; therefore, the datum must be further processed and, for this purpose, is sent to the ORDER phase;
if stage = 1, the input datum to each DEMUX is a coefficient of a 2-D DCT; therefore, the datum does not need any further processing and therefore is sent to the OUTPUT phase.

ORDER phase

This phase consists in arranging the output sequence of the eight 1-D DCT _s in eight l', m',...,s' vectors, thus defined:

Following the ORDER phase the variable stage is updated to the value 1. The output data from the ORDER phase are sent to the PROCESS phase.

OUTPUT phase

This phase consists in rearranging the data originating from the second execution of the PROCESS step (that is, with stage = 1): starting from these data, which constitute the eight-component vectors a, b, ..., h , the output block Y _N*N defined as follows is constituted:

The main differences between the hardware that calculates an 8x8 DCT and the hardware that calculates the four 4x4 DCT _s are:

the sequences into which must be arranged the pixels of a block of the original picture depend on the chosen size of the DCT;
the operations executed during the PROCESS step are not always the same for the two cases.

Procedure for calculating the DCT for blocks of scaleable size (8x8 DCTs, 4x4 DCT _s and 2x2 DCT _s )

From the above described procedures, an algorithm for calculating at choice one 8x8 DCT or four 4x4 DCT _s (in parallel) or sixteen 2x2 DCT _s (in parallel) may be derived.

The selection is made by the user by assigning a certain value to the global variable size:

The procedure is subdivided in various phases (regardless of the value of the variable size), to each of which corresponds an architectural block. A whole view is shown in Fig. 12.

Each phase has been organized in order to provide for partial results corresponding to the chosen value, minimizing redundancies. Some times the operations performed are different depending on the value of size. In these cases, the architecture considers a MUX whose control input is size. Let us examine now the various phases and highlight the differences in respect to the architectures that have already been described above:

INPUT phase

The object of this phase, depicted in Fig. 13, is to arrange the data to allow the computation starting from the arranged data of the 1-D DCTs. This is done by inputting the luminance values of the pixels (8x8 matrix) and arranging them in eight-component vectors l, m, ..., s.

For example:

PROCESS phase with stage = 0

This phase consists in calculating in parallel the eight 1-D DCT _s by processing the vectors l, m, ..., s as shown in Fig. 14.

In this figure may be observed the use of 16 MUX _es controlled by the variable size.

The eight MUX _es on the left serve to bypass the operations required for the computation of the 8x8 DCT. Thus, the bypass occurs when size = 1 or 2, while it does not occur for size = 0.

The eight MUX _es on the right serve to output only the result that corresponds to the pre-selected value of size.

The scheme in Fig. 14 may be subdivided into the architectural blocks shown in Fig. 15.

For example, two vectors each of eight components (each component being a pixel, that may have been processed already) are input to the QA block, which outputs two vectors of eight components: the first vector is the sum of the two input vectors while the second vector is the difference between the two input vectors that is successively processed with the linear operator A.

It should be noticed tat the operators A, B, C, D, B, F, G are 8x8 matrices.

By considering a lower level of generalization, the QA, QB, QC blocks are shown in detail in Figures 16, 17 and 18, respectively. In these figures the MUX _es are controlled by three bits, which correspond to the variable stage (which may take the

value

0 or 1, and thus is represented by a bit) and the variable size (which may take the

value

0, 1 or 2, and thus is represented by two bits).

The blocks QD, QE, QF, QG are shown in detail in Figures 19, 20, 21 and 22, respectively. In these figures the MUX _es are controlled by a bit that corresponds to the variable stage.

ORDER phase

The ORDER phase, depicted in Fig. 23, consists in arranging the output sequences of the eight 1-D DCT _s in eight vectors l', m', ..., s' . For example:

OUTPUT phase

This phase, depicted in Fig. 24, consists in rearranging the data coming from the second (that is with stage = 1) execution of the PROCESS step. Starting from these data, constituting the eight-component vectors a, b, ..., h, the output block yN*N is constituted.

For example:

DESCRIPTION OF THE DRAWINGS

A functional block diagram of a picture compressor-coder according to the present invention may be represented as shown in Figure 1 .

Essentially, the compressor-coder performs a hybrid compression based on a fractal coding in the DCT domain. This is made possible by the peculiar architecture of parallel calculation of the DCT on blocks of scaleable size of pixels, as described above.

Hereinbelow, the remaining figures described one by one:

Figure 2 is a flow graph of the 2x2 DCT generating block. This block is the "base" block that is repeatedly used in the PROCESS phase of all the NxN DCT _s , where N is a power of 2.In particular:

the flow graph for a 2x2 DCT is shown in Fig. 2, wherein A = B = C = 1 and the input and output data are pixels in the positions (0,0), (0,1), (1,0), (1,1);

for sixteen 2x2 DCTs, the inputs and the outputs are eight-component vectors and the following symbols are used, considering A = B = C I _8x8;

for four 4x4 DCTs the inputs and outputs are eight-component vectors and the following symbols are used:

for an 8x8 DCT, the inputs and outputs are eight-component vectors and the flowing symbols are used:

In the scaleable architecture for calculating an 8x8 DCT or four 4x4 DCT _s (in parallel) or sixteen 2x2 DCT _s (in parallel), the inputs and the outputs are vectors of eight components and the following symbols are used:

Figure 3 illustrates the architecture for calculating sixteen 2x2 DCT _s in parallel. The pixels that constitute the input block are ordered during the INPUT phase and processed during the PROCESS phase to obtain the coefficients of the sixteen 2-D DCT _s on four samples. For example, the 2-D DCT of the block (0,1) constituted by

{l[0],m[0],n[0],o[0]} is {a[0],b[0],c[0],d[0]}.

The coefficients of the 2-D DCT _s are rearranged during the ORDER phase in eight vectors of eight components. For example the coefficients {a[0],b[0],c[0],d[0]} will constitute the vector l'.The sixteen two-component vectors so obtained are sent to the PROCESS phase to obtain the coefficients of the 2x2 DCT. These coefficients, reordered during the OUTPUT phase, constitute the output block.

Figure 4 shows the ordering of the input data for calculating sixteen 2x2 DCT _s . This figure shows the way the pixels of the 8x8 input block are ordered to constitute the vectors of 8 components l, m, ..., s . In each quadrant (i,j), with 0 ≤ i,j ≤ 3, the pixels belonging to the vectors are symbolized by different shadings. For example: {A 0,0 i,k }1 k=0 ={x 0,0,x 1,1}From each of these vectors, the components with the same index (that is the pixels with the same column index) will form a vector of four components. For example the vector l is constituted by the elements {A1[0], B1[0]}.Therefore, each pixel of the 8x8 input block will constitute a component of one of the vectors l, m, n, o, p, q, r, s .

Figure 5 shows the process phase for calculating sixteen 2x2 DCT _s . This phase consists in processing the eight-component vectors l, m, ..., s . The PROCESS phase, which is the only phase in which arithmetical operations are performed, is executed only once to calculate in parallel the sixteen 2-D DCT _s .

Figure 6 illustrates the architecture for calculating four 4x4 DCT _s . The pixels that constitute the input block are ordered in the INPUT phase and processed in the PROCESS phases to obtain the coefficients of the sixteen 1-D DCT _s on 4 samples. For example, the 1-D DCT of the sequence {l[0],m[0],n[0], or [0]} is {a[0],b[0],c[0],d[0]}.The coefficients of the 1-D DCT _s are reordered in the ORDER phase in 8 vectors of eight components. For example the coefficients {a[0],b[0],c[0],d[0]} will constitute the vector l '.The 4 four-component vectors so obtained are sent to the PROCESS phase to obtain the coefficients of the 4x4 DCT. These coefficients, reordered in the OUTPUT phase, constitute the output block.

Figure 7 shows the arrangement of the input data for calculating four 4x4 DCT _s . This figure shows how the pixels of the 8x8 input block are ordered to constitute the eight-component vectors l, m, ..., s. In each quadrant (i,j) with 0 ≤ i,j ≤ 3, the pixels belonging to the different vectors have different shadings. For example: {A 0,0 i,k }3 k=0 ={x 0,0,x 1,1,x 2,2,x 3,3}From each of these vectors, the components with the same index (that is, the pixels with the same column index) will form a vector of four components. For example the vector l is constituted by the elements {A1[0], A3[0], B3[0], B1[0]}. The outcome is that each pixel of the input 8x8 block will constitute one component of one of the vectors l, m, n, o, p, q, r, s.

Figure 8 depicts the PROCESS phase for calculating the four 4x4 DCT _s . This phase consists in processing the eight-component vectors: l, m, ..., s. The PROCESS phase, which is the only phase wherein arithmetical operations are performed, is carried out twice:

the first time (stage = 0), to calculate in parallel the sixteen 1-D DCT _s ;

the second time (stage = 1), to calculate the 8x8 DCT starting from the coefficients of the 1-D DCT _s .

Figure 9 illustrates the architecture for calculating an 8x8 DCT. The pixels that constitute the input block are ordered during the INPUT phase and are processed in the PROCESS phase to obtain the coefficients of the eight 1-D DCT _s on 8 samples. For example, the 1-D DCT of the sequence {l[0],m[0], ... , s[0]} is {a[0],b[0], .... ,h[0]}.The coefficients of the 1-D DCT _s are rearranged during the ORDER phase in 8 vectors of eight components. For example the coefficients {a[0],b[0], .... ,h[7]} will constitute the l ' vector.The 8 eight-component vectors so obtained are sent to the PROCESS phase to obtain the 8x8 DCT coefficients. These coefficients, rearranged during the OUTPUT phase, constitute the output block.

Figure 10 shows the arrangement of the input data for calculating an 8x8 DCT. This figure shows how the pixels of the input 8x8 block are arranged to constitute the 8 eight-component vectors: l, m, ..., s. The pixels belonging to the vectors A1, A3, A5, A7, B7, B5, B3, B1 are symbolized with different shadings, for example: {A 1,i }7 i=0 ={x 0,0,x 1,1,x 2,2,x 3,3,x 4,4,x 5,5,x 6,6,x 7,7}From each of these vectors, the components with the same index (that is, the pixels with the same column index) will form a vector of eight components. For example, the vector l is constituted by the elements {A1[0], A3[0], ..., B1[0]}.The result is that each pixel of the input 8x8 block will constitute a component of one of the vectors l, m, n, o, p, q, r, s.

Figure 11 depicts the PROCESS phase for calculating an 8x8 DCT. This phase consists in processing the eight-component vectors l, m, ..., s. The PROCESS phase in which arithmetical operations are performed is executed twice:

the first time (stage=0), to calculate in parallel the sixteen 1-D DCT _s ;

the second time (stage=1), to calculate the 8x8 DCT starting from the coefficients of the 1-D DCT _s .

In Fig. 11 the following symbols have been used:

Figure 12 illustrates a scaleable architecture for calculating an 8x8 DCT or four 4x4 DCT _s or sixteen 2x2 DCT _s . The pixels that constitute the input block are ordered during the INPUT phase and processed during the PROCESS phase, which calculates:

the 1-D DCT _s (for stage = 0, that is for the 8x8 DCT, and for stage = 1, that is for the 4x4 DCT _s ;

the 2-D DCT _s for stage = 2 directly, that is for the 2x2 DCT _s ;

When stage = 0 and stage = 1 the coefficients are then rearranged in the ORDER phase in 8 eight-component vectors, which are sent to the PROCESS phase to obtain the coefficients of the 2-D DCT. These coefficients, rearranged in the OUTPUT phase, constitute the output block.If stage = 2 the coefficients are transmitted directly to the OUTPUT phase, where they are rearranged to constitute the output block.

Figure 13 depicts the INPUT phase for a scaleable architecture. The inputs are the 64 pixels that constitute the input block.The arrangement of the inputs is operated through the MUX _es controlled by the size variable.The 64 outputs are the 8 vectors of eight components l, m, ..., s.

Figure 14 depicts the PROCESS phase for a scaleable architecture. This phase consists in calculating in parallel the eight 1-D DCT _s by processing the vectors l, m, ...,s as shown in Fig. 11.In this figure we may notice that the use of 16 MUX _es controlled by size.The eight MUX _es on the left serve to bypass the necessary operations only for calculating the 8x8 DCT; therefore, the bypass takes place for stage = 1 or 2, while it does not occur when stage = 0.The eight MUX _es on the right serve to output only the result corresponding to the pre-selected size.In Fig. 14 the following symbols are used:

Figure 15 is a block diagram of the structure that implements the PROCESS phase. For example, the QA block receives as an input two vectors of eight components (each component is a pixel, that may have already been processed) and outputs two vectors of eight components. The first vector is the sum of the two input vectors, while the second vector is the difference between the two input vectors, successively processed with the linear operator A. It should be noticed that the A, B, C, D, E, F, G operators are 8x8 matrices.

Figure 16 is a detailed scheme of the QA block. This scheme shows the details of the single components of the two input vectors and the arithmetical operators (adders etc.) which act on each component. The results are sent to the MUX _es depicted on the right side of the figure, each of which, depending on the control variables stage and size, select only one result, which constitutes one component of the output vector.

Figure 17 is a detailed scheme of the QB block. This scheme shows the details of the single components of the two input vectors and the arithmetical operators (adders etc.) which act on each component. The results are sent to the MUX _es depicted on the right side of the figure, each of which, depending on the control variables stage and size, select only one result, which constitute a component of the output vector.

Figure 18 is a detailed scheme of the QC block. This scheme shows the details of the single components of the two input vectors and the arithmetical operators (adders etc.) acting on each component. The results are sent to the MUX _es depicted on the right side of the figure, each of which, depending on the control variable stage and size, select only one result, which constitute one component of the output vector.

Figure 19 is a detailed scheme of the QD block. This scheme shows the details of the single components of the two input vectors and the arithmetical operators (adders etc.) which act on each component. The results are sent to the MUX _es depicted on the right side of the figure, each of which, depending on the control variable stage and size, select only one result, which constitute a component of the output vector.

Figure 20 is a detailed scheme of the QE block. This scheme shows the details of the single components of the two input vectors and the arithmetical operators (adders etc.) which act on each component. The results are sent to the MUX _es depicted on the right side of the figure, each of which, depending on the control variable stage, select only one result, which constitute one component of the output vector.

Figure 21 is a detailed scheme of the QF block. This scheme shows the details of the single components of the two input vectors and the arithmetical operators (adders etc.) which act on each component. The results are sent to the MUX _es depicted on the right side of the figure, each of which, depending on the control variable {\em stage} select only one result, which constitute a component of the output vector.

Figure 22 is a detailed scheme of the QG block. This scheme shows the details of the single components of the two input vectors and the arithmetical operators (adders etc.) which act on each component. The results are sent to the MUX _es depicted on the right side of the figure, each of which, depending on the control variable stage, select only one result, which constitute a component of the output vector.

Figure 23 depicts the ORDER phase for the scaleable architecture. The inputs are constituted by the 64 pixels after they have been processed through the PROCESS phase.The inputs arrangement is effected by the MUX _es controlled by the variable size.The 64 outputs are the components of the eight-component vectors l, m, ..., s.

Figure 24 depicts the OUTPUT phase for the scaleable architecture. The inputs are constituted by the 64 2-D DCT coefficients. The input arrangement is effected by the MUX _es controlled by the variable size.The 64 outputs are the pixels that constitute the output block.

Claims

A method of calculating the discrete cosine transform (DCT) of blocks of pixels of a picture, characterized in that it comprises the steps of defining first subdivision blocks called range blocks, having a fractional and scaleable size N/2 ⁱ*N/2 ⁱ , where i is an integer number, in respect to a maximum pre-defined size of N*N pixels of blocks of division of said picture, referred to as domain blocks, shiftable by intervals of N/2 ⁱ pixels, and of calculating the DCT on 2 ⁱ range blocks of subdivision of a domain block of N*N pixels of said picture, in parallel.
The method according to claim 1, characterized in that the calculation of the DCT in parallel on all range blocks of subdivision of a certain domain block is carried out in a hardware structure and comprises the steps of:

a) ordering the pixels in function of a subdivision in range blocks of a certain dimension by rearranging the input pixels in a number 2 ⁱ of sequences or vectors of 2 ⁱ components;

b) calculating in parallel 2 ⁱ monodimensional DCT _s by processing said vectors defined in the preceding step a);

c) arranging the output sequences of the monodimensional DCT _s relative to said 2 ⁱ vectors;

d) completing the calculation in parallel of 2 ⁱ bidimensional DCT _s by processing said output sequences of monodimensional DCT _s produced in step c);

e) arranging the output sequences of bidimensional DCT _s generated in step d) in a number 2 ⁱ of vectors of bidimensional DCT coefficients.
The method according to claim 2, characterized in that the calculation in parallel of said 2 ⁱ monodimensional DCT _s in step b) and the completion of the parallel calculation of 2 ⁱ bidimensional DCT _s of step d) are performed by subdividing the sequences resulting from step a) and from step c), respectively, in groups of scalar elements, calculating the sums and differences thereof by way of adders and subtractors and by reiterately multiplying the sum and difference results by respective coefficients until completing the calculation of the relative DCT coefficients, respectively monodimensional and bidimensional.
A method of compressing data of a picture to be stored or transmitted through a fractal coding, characterized in that the fractal transform is carried out in the domain of the discrete cosine transform (DCT) through the following steps:

subdividing a picture in blocks of pixels of said two distinct type of blocks as defined in claim 1;

parallely calculating the discrete cosine transform (DCT) of all the 2 ⁱ range blocks and of a relative domain block;

classifying the transformed range blocks according to their relative complexity represented by the sum of the values of the three AC coefficients;

applying the fractal transform in the DCT domain to the data of the range blocks whose complexity classification exceeds a pre-defined threshold and storing only the DC coefficient of the range blocks with a complexity lower than said threshold, identifying a relative domain block to which the range block in a transformation belongs that produces the beset fractal approximation of the range block;

calculating a difference picture between each range block and its fractal approximation;

quantizing said difference picture in the DCT domain by using a quantization table preestablished in function of the characteristics of human sight;

coding said difference picture quantized by a process based on the probabilities of the quantization coefficients;

storing or transmitting the coding code of each range block compressed in the DCT domain and the DC coefficient of each uncompressed range block.