EP0985303A1

EP0985303A1 - Device and method for clock recovery and regeneration of data

Info

Publication number: EP0985303A1
Application number: EP98933436A
Authority: EP
Inventors: Günter Weiss
Original assignee: Robert Bosch GmbH
Current assignee: Robert Bosch GmbH
Priority date: 1997-05-28
Filing date: 1998-05-05
Publication date: 2000-03-15
Also published as: DE19722302A1; WO1998054874A1

Abstract

The invention relates to a device for clock recovery and regeneration of data of HDB3 coded data signals, comprising a device (3) for dividing the data signal (DS) into two channels (DS1,DS2), a theshold value decision circuit device (7) to which the data signals are supplied on both channels and which generates data signals with two logical states (low/high), a scanning device (11) for scanning signals from the threshold value decision circuit device (7) with a system clock (ST) and a decoder device (15) to decode the coded data signal. The invention is characterized in that a timing device (13) is provided to generate an enable-signal (ES) when the signal edge rises and generates an enable-signal (ES) when no signal edge is present after three predeterminable clock counts, in addition to linking both data signals to an output signal, which is supplied to the decoder device (15). The invention also relates to a method enabling clock recovery and data retiming of HDB3 coded data signals.

Description

Device and method for clock recovery and data regeneration

State of the art

The invention relates to a device for clock recovery and data regeneration of HDB3-coded data signals, with a device for dividing the data signal into two channels, a threshold value decision device, to which the data signals of the two channels are fed and which generates data signals with two logical states, and a sampling device Sampling of the data signals of the threshold value decision device with a system clock, and with a decoding device for converting the data signal into a coded binary signal. The invention also relates to a method for clock recovery and data regeneration of HDB3-encoded data signals.

In the field of communication technology in particular, data signals are used for data transmission which are coded according to the HDB3 method. It this HDB3 code is a ternary code that allows the values +1.0 -1 and returns a value +1 or -1 after a maximum of three consecutive zero bits. The HDB3 data signal itself has an RZ (Return to Zero) signal form, which means that the logical one is coded shorter in time than the logical zero. A precise definition of the HDB3 code can be found in ITU G.703, Annex A.

In the device for clock recovery and data regeneration known from the prior art, two binary data signals with the values 0 and 1 are generated from the ternary data signal. In addition, the two binary data signals are sampled with a system clock in order to achieve synchronization with the system clock.

For clock recovery, the two binary data signals are linked and checked for rising signal edges. If a signal edge is detected, a so-called enable signal is generated which serves as a recovered clock signal. Following this signal edge, that is to say the logic 1, one, two or three logic zeros, no signal edge that could trigger the generation of an enable signal can be detected during this period. Instead, one, two or three enable signals are generated in a fixed time frame based on the last detected signal edge.

In the known device, these enable signals are fed to a scanning device which the samples both binary data signals and feeds the resulting data signals to a downstream decoder for generating the decoded binary data signal.

This device has the disadvantage that it has a very low jitter tolerance. This is due to the fact that the time window within which error-free scanning by the scanning device is possible, especially with three consecutive logic zeros, is very narrow even with low jitter.

Advantages of the invention

The advantage of the device for clock recovery and data regeneration with the features of claim 1 and the method with the features of claim 7 is that a significantly higher jitter tolerance, which is higher by a factor of 2.4, can be achieved.

A clock derivation device according to the invention generates an enable signal at a logic zero when a predetermined number of clock cycles has been detected since the last detected signal edge. Because the enable signal is no longer used to sample the binary data signals fed directly to a decoder, the time windows, that is to say the minimum and maximum number of clock cycles within which an enable signal is generated, can be appreciably increased and thus the Improve jitter tolerance. Further advantageous embodiments result from the subclaims.

In an advantageous embodiment, the clock derivation device has a memory unit which is designed to hold three clock number values.

A selection unit is preferably assigned to this storage unit, which outputs one of the three clock number values in sequence.

In a further advantageous embodiment, the clock derivation device comprises an edge detection unit to which the two binary data signals are fed and which generates an edge detection signal when a rising edge is detected.

In a further advantageous embodiment, the clock derivation device has a counting device which increments a counter as a function of a system clock and which has a reset input which is connected to the output of the logic element.

In a further advantageous embodiment, the clock derivation device comprises a comparator, to which the output signal of the counter device and the output signal of the memory unit are fed and which, if they match, generates an enable signal. drawing

The invention will now be explained in more detail using an exemplary embodiment with reference to the drawings. Show:

FIG. 1 shows a block circuit diagram of a device for clock recovery and data regeneration,

Figure 2 is a block circuit diagram of a scanner which is part of the device shown in Figure 1, and

3 shows various temporal signal curves which serve to explain the device according to FIG. 1, a partial diagram relating to the generation of an enable signal according to the prior art.

Embodiment

FIG. 1 shows a device 1 for clock recovery and data regeneration of HDB3-coded data signals. Such a device is used, for example, in communication systems that work, for example, with data streams of two megabits per second. On the one hand, it supplies the data signal decoded into a binary signal and, on the other hand, a so-called enable signal, which is the system clock of the transmitter extracted from the data stream. The data signal stream loses its synchronicity to that due to transmission losses or interference system clock on the transmission side, which is also referred to as jitter. These synchronization problems make data regeneration more difficult, since the temporal position of an expected data signal cannot be specified exactly, but only as a time range.

The device 1 shown in FIG. 1 comprises a separating device 3, for example in the form of a transformer, which separates a ternary data signal DS present at an input 5 of the device 1 into two binary data signals DS1, DS2. The data signal DS1 with the values 0 and 1 and the data signal DS2 with the values 0 and -1 are thus generated from the ternary data signal DS with the logical values -1.0 +1. These two signals DS1, DS2 are fed to an analog threshold value decider 7. This converts the two signals DS1, DS2 into two signals DS1 ¹ and DS2 ', which only have the values 1 and 0.

For synchronization with a system clock ST, which is present at an input 9 of the device 1, the two signals DS1 ¹ and DS2 'are sampled with the system clock ST by means of a scanning device 11 to form signals DS1, DS2. In order to achieve the highest possible jitter tolerance, the system clock is chosen to be as large as possible, so that signal sampling in a fine grid can be achieved. At a signal frequency of 2 MHz of the data signal DS, a system clock ST of 20 MHz is used, for example. However, the system clock should have at least twice the frequency of the data signal DS.

The two sampled data signals DS1, DS2 are an enable signal generator 13 (in the following the ES generator for short), which on the one hand detects rising signal edges in the two input signals DS1 *, DS2 and generates an edge detection signal FL, and on the other hand generates an enable signal ES from the two input data signals, with the system clock ST also providing the ES for synchronization -Generator 13 is supplied.

Finally, for decoding the data signal DS1, DS2 *, the device 1 has an HDB3-BIN decoder 15, to which the enable signal ES, the edge detection signal FL and the system clock ST are supplied in addition to the two signals DS1, DS2 to be decoded. The decoder 15 then provides the decoded binary data signal at an output 17 of the device 1, while the enable signal ES, which is also necessary for further processing, can be tapped off at an output 19.

As shown in FIG. 2, the ES generator 13 comprises an edge detection unit 21, to which the two signals DS1 and DS2 are fed together with the system clock ST and which, upon detection of a rising edge in one of the two Si Signgnnaallee DDSSII and DS2, the edge detection signal FL generated.

Furthermore, the ES generator 13 comprises a memory device 23 which has at least three memory cells 25.1 to 25.3 and a selection element 27 which, in the manner of a multiplexer, connects one of the memory cells 25 to an output 29 of the memory device 23. The memory cells 25.1 to 25.3 each serve to store one Value that represents a number of bars and thus a time period. These values can be specified from the outside via an indicated line 31.

The signal of one of the memory cells 25 present at the output 29 of the memory device 23 is fed to a comparator 33 as an input signal, a further input of the comparator being acted upon by a signal which is generated by a counter device 35 which increments a counter in the system clock ST becomes. The counting device 35 is reset to a value 0 by a rising signal edge in the signal FL of the edge detection unit 21.

When the two input signals match, that is to say the counter value and the value stored in one of the memory cells 25 match, the comparator 33 generates a signal which is synchronized by a circuit 37, for example a flip-flop, with the system clock ST to the enable Signal ES is processed.

As already mentioned, the selection element 27 serves to select one of the memory cells 25, the signal for changing from one memory cell to the next being provided by the circuit 37 in the form of the signal ES. Furthermore, the selection element 27 is reset to a known state by the signal FL, so that, for example, the memory cell 25.1 is connected to the output 29.

The function of the device 1 will now be explained using the diagrams according to FIG. 3. The diagram according to FIG. 3a shows the original data signal OS in the form of data windows without jitter, a bit sequence "10001" being used in the present exemplary embodiment.

FIG. 3b shows the course over time of the combined signals DS1, DS2, with 1-bit signals with minimum, maximum and without jitter being drawn in a time section identified by U instead of the O-bit signals.

FIG. 3c shows the system clock ST, which can be seen to have a multiple of the clock of the data signal.

The enable signal ES generated by the ES generator 13 is then shown in FIG. 3e, while an explanation of the difference from the prior art in FIG. 3d shows an enable signal as it has been generated so far.

In the present exemplary embodiment, the rising edge is used to recover the clock from the two binary data signals DS1, DS2. It ensures that an enable signal ES is generated. This is shown in FIG. 3e in time segment I as signal ESI. By using the rising signal edge, a time-defined enable signal can be generated.

The situation is different when the incoming data signals have a logic zero value. Then there is no signal edge to be detected. In this case, the enable signal must rather be estimated. Advantageous with the The HDB3 code used is that a maximum of three consecutive logical zeros can occur in the data signal.

The ES generator 13 now generates an ES signal within the time ranges indicated by II to IV in FIG. 3 as follows: With the detection of an ascending signal edge, at least the counter 35 and the selection element 27 are reset. This is due to the comparator 33 in the memory cell

25.1 stored value and the value of the counter 35, which is initially 0. As soon as the two values applied to the comparator 33 match, that is to say after detection of the rising signal edge, a number of clock cycles corresponding to the value of the memory cell 25.1 has expired without detection of an rising signal edge, the circuit 37 generates an enable signal ES. It can be seen from FIG. 3 that there are thirteen clock cycles between the signal ESI and the first estimated signal ES2.

If no rising signal edge is detected, the counter 35 continues to count. The selection element is activated by the enable signal ES2 so that it switches to the next memory cell 25.2.

Counter 35 reaches that in the memory cell

25.2 stored higher value, the next enable signal ES3 is generated. In the present exemplary embodiment, the value stored in the memory cell 25.2 is 23.

The selection element 27 is switched on by the signal ES3, so that now the memory cell 25.3 is connected to the comparator 33. If the counter 35 reaches the value stored in the memory cell 25.3, in the present case 33, a further enable signal ES4 is generated.

The next value of the data signal OS must be a logical 1, since three logical O values have already preceded it, so that there is again a defined point in time for generating an enable signal ES5. The counter 35 and the selection element 27 are thus reset and the previously described process begins again.

In the present exemplary embodiment, the values 13, 23, 33 are stored in the memory cells 25.1 to 25.3. These values can be calculated as follows:

In the diagram according to FIG. 3b, signals S1, S2 and S3 with the respective logical value 1 are shown in time segments II to IV. These are ideal signals that are present without jitter at a logical 1 in the data signal OS. For each of these signals S1 to S3, two signals, shown in dashed lines, are shown, with one signal leading in time and the other signal lagging. These signals are therefore no longer synchronized with the data signals OS and therefore have jitter. Using these jitter signals, time _ranges t _Eln -t _E3n can be calculated within which an enable signal could be generated without errors. Each of the time _ranges t _Eln to t _E3n extends from the end of the rising signal _{edge of} the lagging signal to at the beginning of the signal edge of the leading signal of the subsequent time range. In the present exemplary embodiment, the middle of the time ranges was selected as the point in time for generating an enable signal ES.

Because the enable signal ES is not used to sample the data signals DS1, DS2, the time ranges can be extended into sections in which - even with maximum jitter - no data signal can be present, for example between the lagging signal S1 and the leading signal S2 in time periods II and III.

In contrast, the enable signal in conventional systems - as shown in FIG. 3d - is usually generated in such a way that it lies in the middle of the data signal DS1, DS2. The enable signals estimated in time periods II to IV are also strictly based on the middle of the signals S1 to S3 which are not jittery. Since the enable signal according to the prior art is used to sample the data signals DS1, DS2, the time range within which the enable signal could be generated is predetermined by the overlap area of the two jitter signals associated with a signal S1 to S3. The corresponding areas are marked with t _Ela to t _E3a . It can be clearly seen that in time segment IV the time range t _{E3a is} significantly smaller than the possible time range t _{E3n of} the invention, which has a negative influence on the jitter tolerance of the device. As already mentioned, the time _ranges t _Eln to t _E3n according to FIG. 3b can be calculated from the maximum edge movement of the data signal given a given jitter, for example ITU G. 823.

Another advantage of the present invention is that it is insensitive to the pulse width of the HDB3-encoded data to be regenerated with maximum jitter tolerance.

Claims

Expectations

1. Device for clock recovery and data regeneration of HDB3-coded data signals, with a device (3) for dividing the data signal (DS) into two channels (DS1, DS2), a threshold value decision device (7), which the data signals on the two channels are supplied and data signals with two logic states (low / high) are generated, a sampling device (11) for sampling the signals of the threshold value decision device (7) with a system clock (ST) and a decoding device (15) for decoding the coded data signal, thereby characterized in that a clock derivation device (13) is provided which generates an enable signal (ES) on a rising signal edge of the data signal and which, in the absence of a signal edge, generates an enable signal (ES) after one of three predeterminable clock numbers that the output signals ( DS1, DS2) of the scanning device (11) are supplied, and that the decoding device (15) is supplied with an edge detection signal (FL) leads is.

2. Device according to claim 1, characterized in that the clock derivation device (13) comprises a memory device (23) which is designed to receive three clock number values.

3. Apparatus according to claim 2, characterized in that the memory unit (23) comprises a selection unit (27) which outputs three clock number values in sequence.

4. Device according to one of the preceding claims, characterized in that the clock derivation device (13) comprises an edge detection unit (21) which detects the two input signals (DS1, DS) and generates the edge detection signal (FL) on a rising edge.

5. The device according to claim 4, characterized in that the clock derivation device (13) comprises a counting device (35) which has a reset input which is connected to the output of the edge detection unit (21).

6. The device according to claim 5, characterized in that the clock derivation device (13) comprises a comparator device (33) to which the output signal of the counting device (35) and the output signal of the memory unit (23) are supplied.

7. Method for clock recovery and data regeneration of HDB3-coded data signals, which are initially divided into two binary data signal channels and sampled with a system clock, characterized in that the two data signal channels are passed to a decoder for decoding, that when a signal edge is detected in the data signals (DS1, DS2) an enable signal (ES) is generated for clock recovery and a counter (35) is initialized and activated in that when one of three predeterminable counter readings is reached, an enable signal is generated for clock recovery, that the enable signal (ES) is fed to the decoder for data regeneration, and that an edge detection signal (FL) is fed to the decoder (15) that upon detection a rising edge is generated in the data signals.