EP0958602A1 - Method for producing a transistor with self-aligned contacts and field insulation - Google Patents

Method for producing a transistor with self-aligned contacts and field insulation

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Publication number
EP0958602A1
EP0958602A1 EP97930599A EP97930599A EP0958602A1 EP 0958602 A1 EP0958602 A1 EP 0958602A1 EP 97930599 A EP97930599 A EP 97930599A EP 97930599 A EP97930599 A EP 97930599A EP 0958602 A1 EP0958602 A1 EP 0958602A1
Authority
EP
European Patent Office
Prior art keywords
layer
grid
formation
transistor
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP97930599A
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German (de)
French (fr)
Inventor
Simon Deleonibus
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
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Filing date
Publication date
Application filed by Commissariat a lEnergie Atomique CEA filed Critical Commissariat a lEnergie Atomique CEA
Publication of EP0958602A1 publication Critical patent/EP0958602A1/en
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate

Definitions

  • the present invention relates to a field effect transistor provided with field isolation and contact points self-aligned with respect to its active region, and to a method for producing such a transistor.
  • the invention relates more precisely to the manufacture of this transistor on a silicon-on-insulator type substrate, designated in the following text by SOI (Silicon on Insulator).
  • SOI Silicon on Insulator
  • the invention finds applications in microelectronics for the manufacture of devices of the MOS (Metal Oxide Semiconductor) type and in particular for integrated circuits able to be used in an environment subjected to radiation.
  • MOS Metal Oxide Semiconductor
  • FIG. 1 The state of the art closest to the invention is illustrated in Figure 1 attached.
  • This figure shows schematically and in section the structure of a MOS-type transistor 10 produced on an SOI substrate.
  • the active region 12 of the transistor 10 is formed in a thin film of silicon 14 covering a buried layer of silicon oxide S: 0-16 the active region 1? is delimited by thick paves of silicon oxide 17 of the LOCOS type (LOcalized Oxidation of Silicon) formed in the thin film 1 ⁇ ⁇ e silicon.
  • Paves 17 isolate each other differently transistors produced on the same SOI substrate.
  • a grid structure 18 comprises a stack with, in order, a layer of grid insulation 20, a grid 22, a shunt layer 24 forming a contact on the grid 20 and lateral spacers 26 formed on the flanks of the stack.
  • the gate structure 18 is arranged above the channel 28 of the transistor and source 30 and drain 32 regions are formed by doping the thin film 14 on either side of the gate structure.
  • a thick layer 34 of ⁇ e type BPSG glass covers the active region 12 and coats the grid structure 18.
  • Contact holes 36, 38 made in the glass layer 34, directly above the source 30 and of the drain 32, and a metal 40 formed in the holes 36, 38 form conductive paths connecting the source and the drain respectively to metallic interconnection lines 42, 44 formed on the layer 34.
  • a transistor in accordance with FIG. 1 requires a high number of photolithography steps to define its constituent elements.
  • a first step is necessary for the formation of the field oxide pavers 17.
  • a second photolithography step allows the realization of the grid structure 18.
  • Finally, a photolithography step is necessary to practice the holes in the glass layer 34 of contact.
  • the formation of the grid structure 18 includes the deposition of the grid insulator layer 20, the grid layer 22 and the shunt ⁇ e layer 24, then the etching of these layers according to a mask defining the shape and the dimensions of the grid structure.
  • the positioning of the mask defining the grid relative to the mask used to define the oxide pavers is difficult for highly integrated devices.
  • the process does not allow very precise alignment of the grid on the active area and there are problems of inversion of the type of carriers on the sides of the active area. These problems are due in particular to the coupling of the grid with the sides of the active area when the field area is partially hollowed out from the field insulator.
  • Another difficulty in producing the transistor of FIG. 1 is due to the alignment of the contact holes on the source and drain regions. This difficulty also constitutes a limitation to the miniaturization of the devices.
  • an object of the invention is to provide a transistor and its production process on an SOI substrate which does not present the difficulties mentioned above.
  • An object is in particular to propose a method in which the alignment of the grid with respect to the active region comprising the channel, on the one hand, and the alignment of the contact points with respect to the grid, on the other hand , are automatic.
  • Another aim of the invention is to propose a process with a minimum of photolithography steps.
  • An object of the invention is also to propose a transistor allowing total control in weak inversion.
  • the low inversion regime is the conduction regime of the transistor below the conduction threshold under the strong inversion regime. We consider that the total control in low inversion is obtained when there is no current leakage in this operating regime.
  • the invention finally aims to provide a transistor capable of operating in a so-called hostile environment, subjected to ionizing radiation.
  • the invention more specifically relates to a method for producing a transistor on a SOI type support comprising an insulating silicon oxide layer, called buried oxide layer and a film thin silicon covering the buried oxide layer, the process comprising the following successive steps: a) formation on the thin silicon film of a stack comprising, in order, a layer of gate insulator, and a layer of gate material, b) formation on the stack of a first etching mask in a pattern corresponding to an active region of the transistor, c) etching of the layer of gate material, of the layer of gate insulator, and thin film, to form a column with first flanks defined according to the pattern of the first etching mask, d) formation of a layer of electrical insulating material around the column and flattening of this layer with stop on the column, e ) gra vure of the layer of grid material of the column according to a second mask to form a grid structure with two> flanks, f) electrical insulation of the sides of the grid
  • the method of the invention is particularly well suited to SOI type substrates for which the thin film has a thickness less than
  • the electrical insulation of the sides of the grid and the formation of self-aligned contact points on the grid makes it possible to avoid the constraint of precise control of the position of contact holes in the layer of electrical insulating material. .
  • the method of the invention requires only two photolithography steps to form the transistor.
  • the method can also comprise, during step a), the formation of a protective layer above the layer of grid material, the protective layer also being etched during from step c), and forming a stop layer during the planarization of the layer of insulating material in step d).
  • the protective layer is removed after step d).
  • a function of the protective layer is also to protect the upper part of the grid from any oxidation. So, after removing the protective layer, making contact on the grid with a connecting line or with a layer of conductive material called shunt is facilitated.
  • the method may further comprise, after step d) and the exposure of the gate material, the formation of a layer known as a shunt covering the layer of electrical insulating material. and coming into contact with the grid material, the shunt layer also being etched during step e) according to the second etching mask, and second flanks of the snunt layer, formed during step e), also being electrically isolated during step f).
  • a layer known as a shunt covering the layer of electrical insulating material. and coming into contact with the grid material, the shunt layer also being etched during step e) according to the second etching mask, and second flanks of the snunt layer, formed during step e), also being electrically isolated during step f).
  • the shunt layer preferably made of a metal polysilicon, forms a connection line for addressing the grid.
  • step d) oxidation of the sides of the column formed in step c), to cover them with a layer known as oxide of flanks.
  • This oxidation makes it possible to round the edges of the active region of the future transistor and promotes the control of its characteristic in low inversion.
  • the flank oxide layer also serves as an etching stop layer during step e.
  • the formation of contact points on the source and drain regions does not require an additional photolithography step.
  • the contacts are formed, for example, by the conformal deposit of a metal layer, self-aligned with respect to the grid structure, and by the polishing of this metal layer.
  • the absence of a photolithography step for taking the shots contact avoids delicate alignment problems and allows miniaturization of devices.
  • the method can also include the elimination of the grid oxide layer exposed on either side of the grid during step e) and a self-aligned siliciding. of the metal layer with the thin film exposed by the removal of the gate oxide layer. Thanks to this measure, good contact between the source and drain regions and the metal layer is guaranteed.
  • the subject of the invention is also a field effect transistor comprising a source, a channel and a drain formed in a portion of silicon film of a structure of silicon on insulator (SOI) type, a field insulation layer. laterally surrounding the portion of silicon film, a grid structure with isolated sides formed above the channel, and source and drain contacts formed on the portion of silicon film between the field insulation layer and the structure grid.
  • the source and drain contacts are self-aligned on the grid structure and on the field insulation layer and are directly disposed against the sides of the grid structure.
  • the contacts are delimited by a layer, called flank oxide, substantially perpendicular to the portion of silicon film and self-aligned on the field insulation layer.
  • FIG. 1 is a schematic longitudinal section of an MOS field effect transistor of a known type
  • FIG. 2 is a diagrammatic section of a stack of layers on a SOI type substrate, from which a transistor is produced in accordance with the method of the invention
  • FIG. 3 is a schematic section showing the formation of a column by etching the stack of Figure 2
  • FIG. 4 and 5 are schematic sections of the stack illustrating a coating of the column with a layer of insulating material and flattening the layer of insulating material,
  • FIG. 6 is a schematic section of the stack illustrating the formation of a shunt layer on the structure of FIG. 5,
  • FIGS 7 and 8 are sections along a plane VI-VI, indicated in Figure 6, making an angle of 90 ° with the cutting plane of Figures 1 to 6, and illustrate the manufacture of a grid structure
  • - Figures 9, 10 and 11 are sections of the stack according to the section plane of Figures 7 and 8 and illustrate the formation of contact points on source and drain regions of the transistor
  • - Figure 12 is a sectional view of a particular embodiment of a transistor according to one invention. Detailed description of an embodiment of the invention
  • Figure 2 shows the starting structure for manufacturing a transistor.
  • the transistor is produced on an SOI substrate
  • the buried layer 104 comprising a thin surface film of silicon 102 integral with an insulating silicon oxide layer, known as the buried layer 104.
  • the thin film 102 preferably has a thickness less than or equal to 50 nm.
  • a first oxide layer 106 is formed by oxidation of silicon on the free surface of the thin layer 102.
  • Layer 106 constitutes the gate insulator layer of the transistor that is produced.
  • a layer 108 called polyc ⁇ stallm or amorphous silicon grid material, for example, is deposited on the grid insulator layer 106.
  • a protective layer 110 for example, of silicon nitride, or of oxide is deposited on the layer 108 of grid material in order to cover the free face thereof.
  • This protective layer subsequently serves as a polishing stop layer.
  • the stack formed by layers 106, 108 and 110 is designated by the general reference 112.
  • a first etching mask 114 is formed on the stack 112 according to photolithography methods known per se.
  • the mask 114 defines the dimensions of the active area of the transistor that is produced.
  • the following description relates specifically to the production of a single transistor a field effect. However, it is possible to produce simultaneously on the same substrate a plurality of such transistors forming, for example, an integrated circuit.
  • a mask is formed on the stack 112 with a plurality of patterns similar to the pattern 114 and defining the active regions of the plurality of transistors.
  • the layers 110, 108, 106 of the stack and the film 102 of the substrate 100 are etched.
  • the buried oxide layer 104 serves, during this etching, as a stop layer.
  • a column 116 visible in FIG. 3 is obtained.
  • the column comprises, respectively, portions of the thin film 102, of the layer of gate oxide 106, of the layer of gate 108 and of the protective layer 110.
  • the thin film portion 102 of the column 116 corresponds substantially to the active part of the transistor.
  • the sides of column 116 are indicated with the reference 118.
  • the flanks 118 are oxidized. This oxidation relates in particular to the thin silicon film] 02 and the grid material 108 of the column 116.
  • the protective layer 110 limits, in the case of the oxide, and even prevents, in the case silicon nitride, the oxidation of the upper surface of the grid material layer, which it covers.
  • Figure 4 shows in section the structure obtained.
  • a first characteristic shape is a bird's beak shape at the height of the grid oxide layer 106.
  • Another characteristic shape is a rounding of the lower edges of the remaining thin film portion of the column 116.
  • Oxidation at high temperature and / or at high pressure is understood to mean oxidation taking place at a temperature above 1000 ° C. and at a pressure above 10 5 Pa.
  • oxidation at high pressure reference may be made to the document. "High Pressure Oxidation of Silicon in Dry Oxygen" by Liang N. Lie et al. in Solid-State Science and Technology, December 1982, pages 2828-2833.
  • the rounded shape of the thin film portion that is to say of the future active region of the transistor, it is possible to limit the leakage currents of the transistor in a low inversion regime.
  • the control of leakage currents in a low inversion regime that is to say below the conduction threshold, makes it possible to reduce the consumption at rest of the transistor.
  • the flank oxide layer which covers the flanks 118 of the column 116 is designated by the reference 120. Its thickness is comprised, for example between 5 and 20 nm.
  • a next step in the process consists in forming a layer 122 of electrical insulating material around the column 116 to coat it. Layer 120 is shown in Figure ⁇ .
  • the electrical insulating material is for example an oxide layer (glass) doped with phosphorus of the PSG or BPSG type. After the deposition of the layer 122 of insulating material, a heat treatment allows its stabilization and its creep.
  • the function of the insulating material layer is to mutually isolate different transistors or components produced on the same substrate. Another function is to harden the transistors to ionizing radiation.
  • the layer of grid material 108 is exposed and is exposed substantially in the plane of the leveling surface 124 of Ja layer 122.
  • doping can be carried out by implantation of the silicon of the gate layer. Impurities are implanted leading to an n or p type conductivity.
  • the process continues, as shown in FIG. 6, by the formation above the layer of grid material of a layer 126 called shunt.
  • the shunt layer deposited in full plate also covers the planarizing surface of the insulating layer 122.
  • the shunt layer 126 is preferably made of a polysilicon of refractory metal. It is covered with a layer of deposited oxide 128, not doped.
  • the shunt layer makes it possible to improve the contact on the gate and thus increase the operating speed of the transistor.
  • This layer when it is shaped, can also constitute an access line for the polarization of the grid, such as, for example, a line of words.
  • a second etching mask 130 formed on the deposited oxide layer 128 defines the location and dimensions of a gate structure 132 above the active region of the transistor.
  • the successive etching of the oxide layer 128, the shunt layer 126 and the material layer 108, with stopping on the gate oxide layer 102 and on the side oxide layer 120 makes it possible to obtain the structure of figure 7.
  • FIG. 7 and the following figures correspond to a section plane VI-VI, indicated in FIG. 6, and which makes an angle of 90 ° with the section planes of the preceding figures.
  • the lateral extension of the etchings according to the second mask 130 is limited in the zone situated above the portion of thin film 102 by the oxidation of flanks 120.
  • the etchings according to the mask 130 thus make it possible to release the grid structure 132 which is therefore necessarily aligned with the remaining portion of thin film 102, that is to say aligned with the future active region of the transistor.
  • the grid structure includes the grid material layer 108, the shunt layer 126 and the shaped oxide layer 128, shaped.
  • the process is continued by an oxidation of the sides 134 of the grid structure, that is to say, in particular, the layers of grid material 103, and the layer of shunt 126. It is also possible directly deposit a fine oxide on the sides.
  • a first implantation of ions is carried out in the thin film 102 using the grid structure 132 as implantation mask.
  • the doped regions formed during the first implantation are shown in FIG. 7. And indicated by the reference 135.
  • a second implantation is carried out at a higher dose. The implantation is carried out with impurities leading to a conductivity n + or p + depending on the type of transistor channel produced.
  • FIG. 8 After implantation, annealing is carried out and the structure shown in FIG. 8 is obtained.
  • the source and drain regions bear the references 140 and 142 respectively.
  • the lateral spacers 136 are obtained by depositing a layer which makes it possible to isolate the grid from the contact zones 150 and 152, then by attacking this layer by an anisotropic etching, selective with respect to the oxide on the flanks.
  • this layer is made of silicon nitride. It can be made of oxide but its selectivity during the etching of the spacers is less good.
  • the lateral spacers 136 have the function not only of forming gradual source and drain regions but also of protecting 1 - these regions in the vicinity of the grid and on the edge of contact points made subsequently. In particular, the spacers 136 make it possible to avoid or limit a lateral attack on the layer 122 of insulating material (PSG) during cleaning operations which precede the formation of contact points on the drain and source regions.
  • PSG insulating material
  • the formation of contact points on the source and drain regions is preceded by the elimination of the residual gate oxide layer around the gate structure, to expose a part of the thin film 102 corresponding to the source. and to the drain.
  • the oxide sides of the grid structure and the oxide sides 120 covering laterally the layer 122 of insulating material, are protected by the lateral spacers 136.
  • a layer of metal 148 for example of tungsten, is then formed by chemical vapor deposition on the entire structure. As shown in FIG. 9, the metal layer 148 comes into contact with the exposed source and drain regions 140, 142 and coats the grid structure 132
  • the technique of metal deposition in the vapor phase (CVDj) allows obtain a compliant deposit.
  • the free surface 124 of the layer 122 of insulating material can be covered with a layer 125 of titanium / tungsten and advantageously a two-layer system whose composition makes it possible to perform the functions diffusion barrier and ⁇ e contact barrier It is for example a layer of Ti-W in a composition close to stoichiometry.
  • This layer represented in FIG. 9, constitutes a layer metal attachment and also serves as a diffusion barrier of the metal in the insulation.
  • the source and drain 140, 142 are silicided before the deposition of the layer 125 using selective siliciding on the bare silicon. Siliconization makes it possible to reduce the resistance at the metal-semiconductor interface and thus improve the contacts made on the source and drain.
  • the silicided parts are indicated with the reference 149.
  • the metal layer is polished in order to flatten it up to the silicon oxide layer 128 of the grid structure 132.
  • the layer 125 is also polished to the following.
  • the metal layer and the bonding layer can, as shown in FIG. 11, be etched for the shaping of contacts 150, 152.
  • Other conventional operations ae depositing metals or insulators make it possible to carry out interconnections of the transistor with an integrated circuit. These operations, known per se, are not detailed here.
  • FIG. 11 also shows the characteristics of the transistor which is the subject of the invention.
  • the main characteristics of this transistor are: an active region, formed in layer 102, the edges of which are rounded, a gate 108, 132 self-aligned on the channel in the active region, an active region protected by an insulation layer 122, and contacts 150, 152 self-aligned on both the grid and the insulation layer.
  • the flank oxide layer 120 which extends substantially perpendicular to the active region makes it possible to avoid any risk of covering the metal of the contacts on the edges of the active zone, that is to say on the sides of the thin film portion forming the active area.
  • the insulating materials forming the flank oxide layer 120 and the insulation layer 122 are different.
  • the sidewall oxide layer is formed by oxidation while the insulation layer 122 is formed by deposition.
  • FIG. 11 illustrates the production of a transistor with a symmetrical structure
  • FIG. 12 shows a transistor, according to the invention, in which the gate structure 132 is not centered relative to the sides of the insulating layer 122.
  • the gate is however always perfectly aligned with respect to the channel ⁇ e the active region Sur Figures 11 and 12, the channel is indicated with the reference 103.
  • the contact sockets 150, 152 formed on the sources and drain 140, 142, are self-aligned on the grid and the active area and are arranged directly against the grid structure, in contact with the lateral spacers
  • the contact points 150, 152 constitute in a way raised and metallized source and drain.
  • the method and the transistor of the invention make it possible to increase the density of integration and, as indicated here or now, to make the economy of an expensive and critical masking step for making the contacts on the source and drain.

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  • Power Engineering (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Thin Film Transistor (AREA)

Abstract

The invention concerns a MOS transistor and its method of production. The transistor comprises a source (140), a channel (103) and a drain (142) formed on a silicon film (102) portion of a silicon on sapphire structure, a field insulating layer (122) surrounding the film (102), a grid structure (132) with insulated flanks formed above the channel, and source and drain contacts (150, 152) provided on the silicon film (102) portion between the field insulating layer (122) and the grid structure (132). The source and drain contacts are self-aligned on the grid structure (132) and the field insulating layer (122) and directly arranged against the grid structure. The invention is useful in the manufacture of integrated circuits.

Description

TRANSISTOR ET PROCEDE DE REALISATION D'UN TRANSISTOR A CONTACTS ET A ISOLATION DE CHAMP AUTO-ALIGNES TRANSISTOR AND METHOD FOR PRODUCING A CONTACTS AND SELF-ALIGNED FIELD ISOLATION TRANSISTOR
DESCRIPTIONDESCRIPTION
Domaine techniqueTechnical area
La présente invention se rapporte a un transistor a effet de champ pourvu d'une isolation de champ et de prises de contact auto-alignees par rapport a sa région active, et a un procède de réalisation d'un tel transistorThe present invention relates to a field effect transistor provided with field isolation and contact points self-aligned with respect to its active region, and to a method for producing such a transistor.
L'invention concerne plus précisément la fabrication de ce transistor sur un substrat de type silicium sur isolant, désigne dans la suite du texte par SOI (Silicon on Insulator) .The invention relates more precisely to the manufacture of this transistor on a silicon-on-insulator type substrate, designated in the following text by SOI (Silicon on Insulator).
L'invention trouve des applications en raicroelectronique pour la fabrication de dispositifs du type MOS (Métal Oxyde Semiconductor) et en particulier pour des circuits intègres aptes a être utilises dans un environnement soumis a des rayonnementsThe invention finds applications in microelectronics for the manufacture of devices of the MOS (Metal Oxide Semiconductor) type and in particular for integrated circuits able to be used in an environment subjected to radiation.
Etat de la technique antérieureState of the art
L'état de la technique le plus proche de l'invention est illustre par la figure 1 annexée. Cette figure montre de façon schématique et en coupe la structure d'un transistor 10 de type MOS réalisée sur un substrat SOI. La région active 12 du transistor 10 est rormee dans un film mince de silicium 14 recou/rant une couche enterrée d'oxyde de silicium S:0- 16 la région active 1? est délimitée par des paves épais d'oxyde de silicium 17 du type LOCOS (LOcalized Oxidation of Silicon) formes dans le film mince 1^ αe silicium. Les paves 17 isolent mutuellement différents transistors réalisés sur le même substrat SOI. Une structure de grille 18 comprend un empilement avec, dans l'ordre, une couche d'isolant de grille 20, une grille 22, une couche de shunt 24 formant une prise de contact sur la grille 20 et des espaceurs latéraux 26 formés sur les flancs de l'empilement.The state of the art closest to the invention is illustrated in Figure 1 attached. This figure shows schematically and in section the structure of a MOS-type transistor 10 produced on an SOI substrate. The active region 12 of the transistor 10 is formed in a thin film of silicon 14 covering a buried layer of silicon oxide S: 0-16 the active region 1? is delimited by thick paves of silicon oxide 17 of the LOCOS type (LOcalized Oxidation of Silicon) formed in the thin film 1 ^ αe silicon. Paves 17 isolate each other differently transistors produced on the same SOI substrate. A grid structure 18 comprises a stack with, in order, a layer of grid insulation 20, a grid 22, a shunt layer 24 forming a contact on the grid 20 and lateral spacers 26 formed on the flanks of the stack.
La structure de grille 18 est disposée au- dessus du canal 28 du transistor et des régions de source 30 et de drain 32 sont formées par dopage du film mince 14 de part et d'autre de la structure de grille.The gate structure 18 is arranged above the channel 28 of the transistor and source 30 and drain 32 regions are formed by doping the thin film 14 on either side of the gate structure.
Une épaisse couche 34 de verre αe type BPSG (borophosphosilicate glass) recouvre la région active 12 et enrobe la structure de grille 18. Des trous de contact 36, 38 pratiqués dans la couche de verre 34, à l'aplomb de la source 30 et du drain 32, et un métal 40 formé dans les trous 36, 38 forment des voies conductrices reliant la source et le drain respectivement à des lignes d'interconnexion métalliques 42, 44 formées sur la couche 34.A thick layer 34 of αe type BPSG glass (borophosphosilicate glass) covers the active region 12 and coats the grid structure 18. Contact holes 36, 38 made in the glass layer 34, directly above the source 30 and of the drain 32, and a metal 40 formed in the holes 36, 38 form conductive paths connecting the source and the drain respectively to metallic interconnection lines 42, 44 formed on the layer 34.
La réalisation d'un transistor conforme a la figure 1 nécessite un nombre élevé d'étapes de photolithographie pour définir ses éléments constitutifs . Une première étape est nécessaire pour la formation des pavés d'oxyde de champ 17. Une deuxième étape de photolithographie permet la réalisation de la structure de grille 18. Enfin, une étape de photolithographie est nécessaire pour pratiquer dans la couche de verre 34 les trous de contact.The production of a transistor in accordance with FIG. 1 requires a high number of photolithography steps to define its constituent elements. A first step is necessary for the formation of the field oxide pavers 17. A second photolithography step allows the realization of the grid structure 18. Finally, a photolithography step is necessary to practice the holes in the glass layer 34 of contact.
La formation de la structure de grille 18 comprend le dépôt de la couche d'isolant de grille 20, de la couche de grille 22 et de la couche αe shunt 24, puis la gravure de ces couches selon un masque définissant la forme et les dimensions de la structure de grille. Le positionnement du masque définissant la grille par rapport au masque utilisé pour définir les pavés d'oxyde est délicat pour des dispositifs à forte intégration. Ainsi, le procède ne permet pas un alignement très précis de la grille sur la zone active et on note des problèmes d'inversion du type de porteurs sur les flancs de la zone active. Ces problèmes sont dus notamment au couplage de la grille avec les flancs de la zone active lorsque la zone de champ est partiellement évidee de l'isolant de champ.The formation of the grid structure 18 includes the deposition of the grid insulator layer 20, the grid layer 22 and the shunt αe layer 24, then the etching of these layers according to a mask defining the shape and the dimensions of the grid structure. The positioning of the mask defining the grid relative to the mask used to define the oxide pavers is difficult for highly integrated devices. Thus, the process does not allow very precise alignment of the grid on the active area and there are problems of inversion of the type of carriers on the sides of the active area. These problems are due in particular to the coupling of the grid with the sides of the active area when the field area is partially hollowed out from the field insulator.
Une autre difficulté de la réalisation du transistor de la figure 1 tient a l'alignement des trous de contact sur les régions de source et de drain. Cette difficulté constitue également une limitation a la miniaturisation des dispositifs.Another difficulty in producing the transistor of FIG. 1 is due to the alignment of the contact holes on the source and drain regions. This difficulty also constitutes a limitation to the miniaturization of the devices.
Ainsi, un but de l'invention est ce proposer un transistor et son procède de réalisation sur un substrat SOI qui ne présente pas les difficultés évoquées ci-dessus.Thus, an object of the invention is to provide a transistor and its production process on an SOI substrate which does not present the difficulties mentioned above.
Un but est en particulier de proposer un procédé dans lequel l'alignement de la grille par rapport à la région active comprenant le canal, d'une part, et l'alignement des prises de contact par rapport a la grille, d'autre part, sont automatiques. Un but αe l'invention est encore de proposer un procédé avec un minimum d'étapes de photolithographie.An object is in particular to propose a method in which the alignment of the grid with respect to the active region comprising the channel, on the one hand, and the alignment of the contact points with respect to the grid, on the other hand , are automatic. Another aim of the invention is to propose a process with a minimum of photolithography steps.
Un but de l'invention est aussi de proposer un transistor autorisant le contrôle total en faiole inversion. Le régime de faible inversion est le régime de conduction du transistor sous le seuil de conduction en régime de forte inversion. On considère que le contrôle total en faible inversion est obtenu lorsqu'il n'y a pas de fuite de courant dans ce régime de fonctionnement .An object of the invention is also to propose a transistor allowing total control in weak inversion. The low inversion regime is the conduction regime of the transistor below the conduction threshold under the strong inversion regime. We consider that the total control in low inversion is obtained when there is no current leakage in this operating regime.
L'invention a enfin pour but de proposer un transistor capable de fonctionner dans un environnement dit hostile, soumis à un rayonnement ionisant.The invention finally aims to provide a transistor capable of operating in a so-called hostile environment, subjected to ionizing radiation.
Exposé de l'inventionStatement of the invention
Pour atteindre les buts mentionnes ci-dessus, l'invention a plus précisément pour objet un procédé de réalisation d'un transistor sur un support de type SOI comprenant une couche d'oxyde de silicium isolant, dite couche d'oxyde enterrée et un film mince de silicium recouvrant la couche d'oxyde enterrée, le procède comprenant les étapes successives suivantes : a) formation sur le film mince de silicium d'un empilement comprenant, dans l'ordre, une couche d'isolant de grille, et une coucne de matériau de grille, b) formation sur l'empilement d'un premier masσue de gravure selon un motif correspondant a une zone active du transistor, c) gravure de la couche de matériau de grille, de la couche d'isolant de grille, et du film mince, pour former une colonne avec des premiers flancs définis selon le motif du premier masque de gravure, d) formation d'une couche de matériau isolant électrique autour de la colonne et aplanissement de cette couche avec arrêt sur la colonne, e) gravure de la couche de matériau de grille de la colonne selon un deuxième masque pour former une structure de grille avec des deu> îemes flancs, f) isolation électrique des flancs de la structure de grille, g) formation de régions de source et de drain dans le film mince par implantation d'impuretés, h) formation auto-alignée sur la structure de grille de prises de contact sur les régions de source et de drain.To achieve the goals mentioned above, the invention more specifically relates to a method for producing a transistor on a SOI type support comprising an insulating silicon oxide layer, called buried oxide layer and a film thin silicon covering the buried oxide layer, the process comprising the following successive steps: a) formation on the thin silicon film of a stack comprising, in order, a layer of gate insulator, and a layer of gate material, b) formation on the stack of a first etching mask in a pattern corresponding to an active region of the transistor, c) etching of the layer of gate material, of the layer of gate insulator, and thin film, to form a column with first flanks defined according to the pattern of the first etching mask, d) formation of a layer of electrical insulating material around the column and flattening of this layer with stop on the column, e ) gra vure of the layer of grid material of the column according to a second mask to form a grid structure with two> flanks, f) electrical insulation of the sides of the grid structure, g) formation of source and drain regions in the thin film by implantation of impurities, h) self-aligned formation on the grid structure of contact points on the regions source and drain.
Le procédé de l'invention est particulièrement bien adapté à des substrats de type SOI pour lesquels le film mince présente une épaisseur inférieure àThe method of the invention is particularly well suited to SOI type substrates for which the thin film has a thickness less than
20 nm. Sa mise en oeuvre ne se limite cependant pas à ces épaisseurs.20 nm. However, its implementation is not limited to these thicknesses.
Par ailleurs, l'isolation électrique des flancs de la grille et la formation de prises de contact auto- alignées sur la grille permet d'éviter la contrainte d'un contrôle précis de la position de trous de contact dans la couche de matériau isolant électrique.Furthermore, the electrical insulation of the sides of the grid and the formation of self-aligned contact points on the grid makes it possible to avoid the constraint of precise control of the position of contact holes in the layer of electrical insulating material. .
On peut noter également que le procédé de l'invention ne nécessite que deux étapes de photolithographie pour former le transistor.It can also be noted that the method of the invention requires only two photolithography steps to form the transistor.
Selon un aspect de l'invention, le procédé peut en outre comporter, lors de l'étape a) , la formation d'une couche de protection au-dessus de la couche de matériau de grille, la couche de protection étant également gravée lors de l'étape c) , et formant une couche d'arrêt lors de aplanissement de la couche de matériau isolant à l'étape d) . La couche de protection est éliminée après l'étape d) .According to one aspect of the invention, the method can also comprise, during step a), the formation of a protective layer above the layer of grid material, the protective layer also being etched during from step c), and forming a stop layer during the planarization of the layer of insulating material in step d). The protective layer is removed after step d).
Une fonction de la couche de protection est également de protéger la partie supérieure de la grille de toute oxydation. Ainsi, après l'élimination de la couche de protection, la prise de contact sur la grille avec une ligne de connexion ou avec une couche de matériau conducteur dit de shunt est facilitée.A function of the protective layer is also to protect the upper part of the grid from any oxidation. So, after removing the protective layer, making contact on the grid with a connecting line or with a layer of conductive material called shunt is facilitated.
En effet, selon un autre aspect de l'invention, le procédé peut comporter en outre après l'étape d) et la mise à nu du matériau de grille, la formation d'une couche dite de shunt recouvrant la couche de matériau isolant électrique et venant en contact avec le matériau de grille, la couche de shunt étant également gravée lors de l'étape e) selon le deuxième masque de gravure, et des deuxièmes flancs de la couche de snunt, formés lors de l'étape e), étant également isolés électriquement lors de l'étape f) .In fact, according to another aspect of the invention, the method may further comprise, after step d) and the exposure of the gate material, the formation of a layer known as a shunt covering the layer of electrical insulating material. and coming into contact with the grid material, the shunt layer also being etched during step e) according to the second etching mask, and second flanks of the snunt layer, formed during step e), also being electrically isolated during step f).
La couche de shunt, de préférence en un polysiliciure de métal, forme une ligne de connexion pour l'adressage de la grille.The shunt layer, preferably made of a metal polysilicon, forms a connection line for addressing the grid.
Selon une mise en oeuvre particulière du procédé, celui-ci peut comporter en outre, avant l'étape d) une oxydation des flancs de la colonne formée à l'étape c), pour les recouvrir d'une coucne dite d'oxyde de flancs. Cette oxydation permet d'arrondir les bords de la région active du futur transistor et favorise le contrôle de sa caractéristique en faible inversion.According to a particular implementation of the method, it can also comprise, before step d) oxidation of the sides of the column formed in step c), to cover them with a layer known as oxide of flanks. This oxidation makes it possible to round the edges of the active region of the future transistor and promotes the control of its characteristic in low inversion.
La couche d'oxyde de flancs sert également de couche d'arrêt de gravure lors de l'étape e.The flank oxide layer also serves as an etching stop layer during step e.
La formation de prises de contact sur les régions de source et de drain ne nécessite pas d'étape supplémentaire de photolithographie. Les prises de contact sont formées, par exemple, par le αepôt conforme d'une couche de métal, auto-alignee par rapport à la structure de grille, et par le polissage de cette couche de métal. L'absence d'une étape de photolithographie pour la réalisation des prises de contact permet d'éviter les problèmes d'alignement délicats et autorise une miniaturisation des dispositifs .The formation of contact points on the source and drain regions does not require an additional photolithography step. The contacts are formed, for example, by the conformal deposit of a metal layer, self-aligned with respect to the grid structure, and by the polishing of this metal layer. The absence of a photolithography step for taking the shots contact avoids delicate alignment problems and allows miniaturization of devices.
Selon un autre aspect de l'invention, le procédé peut aussi comporter l'élimination de la couche d'oxyde de grille mise à nu de part et d'autre de la grille lors de l'étape e) et une siliciuration auto- alignée de la couche de métal avec le film mince mis à nu par l'élimination de la couche d'oxyde de grille. Grâce à cette mesure, un bon contact entre les régions de source et de drain et la couche de métal est garanti .According to another aspect of the invention, the method can also include the elimination of the grid oxide layer exposed on either side of the grid during step e) and a self-aligned siliciding. of the metal layer with the thin film exposed by the removal of the gate oxide layer. Thanks to this measure, good contact between the source and drain regions and the metal layer is guaranteed.
L'invention a également pour objet un transistor à effet de champ comprenant une source, un canal et un drain formés dans une portion de film de silicium d'une structure de type silicium sur isolant (SOI), une couche d'isolation de champ entourant latéralement la portion de film de silicium, une structure de grille à flancs isolés formés au-dessus du canal, et des contacts de source et de drain ménagés sur la portion de film de silicium entre la couche d'isolation de champ et la structure de grille. Conformément à l'invention, les contacts de source et de drain sont auto-alignés sur la structure de grille et sur la couche d'isolation de champ et sont directement disposés contre les flancs de la structure de grille. De plus, les contacts sont délimités par une couche, dite d'oxyde de flancs, sensiblement perpendiculaire à la portion de film de silicium et auto-alignée sur la couche d'isolation de champ.The subject of the invention is also a field effect transistor comprising a source, a channel and a drain formed in a portion of silicon film of a structure of silicon on insulator (SOI) type, a field insulation layer. laterally surrounding the portion of silicon film, a grid structure with isolated sides formed above the channel, and source and drain contacts formed on the portion of silicon film between the field insulation layer and the structure grid. According to the invention, the source and drain contacts are self-aligned on the grid structure and on the field insulation layer and are directly disposed against the sides of the grid structure. In addition, the contacts are delimited by a layer, called flank oxide, substantially perpendicular to the portion of silicon film and self-aligned on the field insulation layer.
D'autres caractéristiques et avantages de l'invention ressortiront mieux de la description qui va suivre, donnée à titre purement illustratif et nullement limitatif, en référence aux figures des dessins annexés.Other characteristics and advantages of the invention will emerge more clearly from the description which follows, given purely by way of illustration and in no way limiting, with reference to the figures of the appended drawings.
Brève description des figures - la figure 1, déjà décrite, est une coupe schématique longitudinale d'un transistor à effet de champ MOS d'un type connu,Brief description of the figures - FIG. 1, already described, is a schematic longitudinal section of an MOS field effect transistor of a known type,
- la figure 2 est une coupe schématique d'un empilement de couches sur un substrat de type SOI, a partir duquel on réalise un transistor conformément au procède de l'invention,FIG. 2 is a diagrammatic section of a stack of layers on a SOI type substrate, from which a transistor is produced in accordance with the method of the invention,
- la figure 3 est une coupe schématique montrant la formation d'une colonne par gravure de l'empilement de la figure 2, - les figures 4 et 5 sont des coupes schématiques de l'empilement illustrant un enrobage de la colonne avec une couche de matériau isolant et 1 ' aplanissement de la couche de matériau isolant,- Figure 3 is a schematic section showing the formation of a column by etching the stack of Figure 2, - Figures 4 and 5 are schematic sections of the stack illustrating a coating of the column with a layer of insulating material and flattening the layer of insulating material,
- la figure 6 est une coupe schématique de l'empilement illustrant la formation d'une couche shunt sur la structure de la figure 5,FIG. 6 is a schematic section of the stack illustrating the formation of a shunt layer on the structure of FIG. 5,
- Les figures 7 et 8 sont des coupes selon un plan VI-VI, indique sur la figure 6, faisant un angle de 90° avec le plan de coupe des figures 1 a 6, et illustrent la fabrication d'une structure de grille,- Figures 7 and 8 are sections along a plane VI-VI, indicated in Figure 6, making an angle of 90 ° with the cutting plane of Figures 1 to 6, and illustrate the manufacture of a grid structure,
- les figures 9, 10 et 11 sont des coupes de l'empilement selon le plan de coupe des figures 7 et 8 et illustrent la formation de prises de contact sur des régions de source et de drain du transistor, - la figure 12 est une vue en coupe d'une réalisation particulière d'un transistor conforme a 1 ' invention . Description détaillée d'un mode de mise en oeuyre de 1 ' invention- Figures 9, 10 and 11 are sections of the stack according to the section plane of Figures 7 and 8 and illustrate the formation of contact points on source and drain regions of the transistor, - Figure 12 is a sectional view of a particular embodiment of a transistor according to one invention. Detailed description of an embodiment of the invention
La figure 2 montre la structure de départ pour la fabrication d'un transistor. Le transistor est réalisé sur un substrat SOIFigure 2 shows the starting structure for manufacturing a transistor. The transistor is produced on an SOI substrate
100 comprenant un film superficiel mince de silicium 102 solidaire d'une couche d'oxyde de silicium isolant, dite couche enterrée 104.100 comprising a thin surface film of silicon 102 integral with an insulating silicon oxide layer, known as the buried layer 104.
Le film mince 102 présente de préférence une épaisseur inférieure ou égale a 50 nm.The thin film 102 preferably has a thickness less than or equal to 50 nm.
Une première couche d'oxyde 106 est formée par oxydation du silicium a la surface libre de la couche mince 102.A first oxide layer 106 is formed by oxidation of silicon on the free surface of the thin layer 102.
La couche 106 constitue la couche d'isolant de grille du transistor que l'on réalise.Layer 106 constitutes the gate insulator layer of the transistor that is produced.
Une couche 108 dite de matériau de grille en silicium polycπstallm ou amorphe, par exemple, est déposée sur la couche d'isolant αe grille 106.A layer 108, called polycπstallm or amorphous silicon grid material, for example, is deposited on the grid insulator layer 106.
Enfin, une couche de protection 110, par exemple, en nitrure de silicium, ou en oxyde est déposée sur la couche 108 de matériau de grille afin d'en recouvrir la face libre. Cette couche de protection sert ultérieurement de couche d'arrêt de polissage. L'empilement formé par les couches 106, 108 et 110 est désigné par la référence générale 112.Finally, a protective layer 110, for example, of silicon nitride, or of oxide is deposited on the layer 108 of grid material in order to cover the free face thereof. This protective layer subsequently serves as a polishing stop layer. The stack formed by layers 106, 108 and 110 is designated by the general reference 112.
Un premier masque de gravure 114, représente en trait discontinu sur la figure 2 est formé sur l'empilement 112 selon des procèdes de photolithographie connus en soi. Le masque 114 définit les dimensions de la zone active du transistor que l'on réalise.A first etching mask 114, shown in broken lines in FIG. 2, is formed on the stack 112 according to photolithography methods known per se. The mask 114 defines the dimensions of the active area of the transistor that is produced.
La suite de la description se rapporte spécifiquement à la réalisation d'un seul transistor a effet de champ. Toutefois, il est possible de réaliser de façon simultanée sur le même substrat une pluralité de tels transistors formant, par exemple, un circuit intégré. Dans ce cas, on forme sur l'empilement 112 un masque avec une pluralité de motifs semblables au motif 114 et définissant les régions actives de la pluralité de transistors.The following description relates specifically to the production of a single transistor a field effect. However, it is possible to produce simultaneously on the same substrate a plurality of such transistors forming, for example, an integrated circuit. In this case, a mask is formed on the stack 112 with a plurality of patterns similar to the pattern 114 and defining the active regions of the plurality of transistors.
Après la formation du masque on grave les couches 110, 108, 106 de l'empilement et le film 102 du substrat 100. La couche d'oxyde enterrée 104 sert, lors de cette gravure, de couche d'arrêt.After the mask has been formed, the layers 110, 108, 106 of the stack and the film 102 of the substrate 100 are etched. The buried oxide layer 104 serves, during this etching, as a stop layer.
Après la gravure et l'élimination du masque 114, on obtient une colonne 116 visible sur la figure 3. La colonne comporte respectivement des portions du film mince 102, de la couche de l'oxyde de grille 106, de la couche de grille 108 et de la couche de protection 110. La portion de film mince 102 de la colonne 116 correspond sensiblement à la partie active du transistor. Les flancs de la colonne 116 sont indiqués avec la référence 118.After the etching and removal of the mask 114, a column 116 visible in FIG. 3 is obtained. The column comprises, respectively, portions of the thin film 102, of the layer of gate oxide 106, of the layer of gate 108 and of the protective layer 110. The thin film portion 102 of the column 116 corresponds substantially to the active part of the transistor. The sides of column 116 are indicated with the reference 118.
Après l'élimination du masque 114, les flancs 118 sont oxydés. Cette oxydation concerne en particulier le film mince de silicium ]02 et le matériau de grille 108 de la colonne 116. Lors de cette étape, la couche de protection 110 limite, dans le cas de l'oxyde, et même prévient, dans le cas du nitrure de silicium, l'oxydation de la surface supérieure de couche de matériau de grille, qu'elle recouvre. La figure 4 montre en coupe la structure obtenue. Sur cette figure, on peut noter des formes caractéristiques de la colonne 116 avec les flancs oxydés . Une première forme caractéristique est une forme en bec d'oiseau à la hauteur de la couche 106 d'oxyde de grille. Une autre forme caractéristique est un arrondi des bords inférieurs de la portion de film mince de silicium restante de la colonne 116.After removal of the mask 114, the flanks 118 are oxidized. This oxidation relates in particular to the thin silicon film] 02 and the grid material 108 of the column 116. During this step, the protective layer 110 limits, in the case of the oxide, and even prevents, in the case silicon nitride, the oxidation of the upper surface of the grid material layer, which it covers. Figure 4 shows in section the structure obtained. In this figure, we can note characteristic shapes of column 116 with oxidized flanks. A first characteristic shape is a bird's beak shape at the height of the grid oxide layer 106. Another characteristic shape is a rounding of the lower edges of the remaining thin film portion of the column 116.
Ces formes caractéristiques sont obtenues de préférence avec une oxydation à haute température et/ou à haute pression. On entend par oxydation a haute température et/ou à haute pression une oxydation ayant lieu à une température supérieure à 1000°C et une pression supérieure a 105 Pa. Au sujet de l'oxydation a haute pression, on peut se reporter au document "High Pressure Oxidation of Silicon in Dry Oxygen" de Liang N. Lie et al. dans Solid-State Science and Technology, Décembre 1982, pages 2828-2833.These characteristic forms are preferably obtained with high temperature and / or high pressure oxidation. Oxidation at high temperature and / or at high pressure is understood to mean oxidation taking place at a temperature above 1000 ° C. and at a pressure above 10 5 Pa. With regard to oxidation at high pressure, reference may be made to the document. "High Pressure Oxidation of Silicon in Dry Oxygen" by Liang N. Lie et al. in Solid-State Science and Technology, December 1982, pages 2828-2833.
Grâce à la forme arrondie de la portion de film mince, c'est-à-dire de la future région active du transistor, il est possible de limiter des courants de fuite du transistor en régime de faible inversion. Le contrôle des courants de fuite en régime de faible inversion, c'est-a-dire en-dessous du seuil de conduction, permet de réduire la consommation au repos du transistor.Thanks to the rounded shape of the thin film portion, that is to say of the future active region of the transistor, it is possible to limit the leakage currents of the transistor in a low inversion regime. The control of leakage currents in a low inversion regime, that is to say below the conduction threshold, makes it possible to reduce the consumption at rest of the transistor.
La couche d'oxyde de flancs qui recouvre les flancs 118 de la colonne 116 est désignée par la référence 120. Son épaisseur est comprise, par exemple entre 5 et 20 nm. Une étape suivante du procédé consiste a former une couche 122 de matériau isolant électrique autour de la colonne 116 pour l'enrober. La couche 120 est représentée sur la figure Λ . Le matériau isolant électrique est par exemple une couche d'oxyde (verre) dopée au phosphore du type PSG ou BPSG. Après le dépôt de la coucne 122 de matériau isolant, un traitement thermique permet sa stabilisation et son fluage.The flank oxide layer which covers the flanks 118 of the column 116 is designated by the reference 120. Its thickness is comprised, for example between 5 and 20 nm. A next step in the process consists in forming a layer 122 of electrical insulating material around the column 116 to coat it. Layer 120 is shown in Figure Λ. The electrical insulating material is for example an oxide layer (glass) doped with phosphorus of the PSG or BPSG type. After the deposition of the layer 122 of insulating material, a heat treatment allows its stabilization and its creep.
La couche de matériau isolant (verre PSG ou BPSG) a pour fonction d'isoler mutuellement différents transistors ou composants réalisés sur le même substrat. Une autre fonction est de durcir les transistors aux rayonnements ionisants.The function of the insulating material layer (PSG or BPSG glass) is to mutually isolate different transistors or components produced on the same substrate. Another function is to harden the transistors to ionizing radiation.
Un polissage mécanochimique sélectif par rapport au nitrure de silicium, permet d'aplanir la couche 122 de matériau isolant jusque sur la couche de protection 110 en nitrure de silicium qui recouvre la couche de matériau de grille 108.Selective mechanochemical polishing with respect to the silicon nitride makes it possible to flatten the layer 122 of insulating material as far as the protective layer 110 of silicon nitride which covers the layer of grid material 108.
Puis, après l'élimination de la couche de protection 110 on obtient la structure vue en coupe sur la figure 5. La couche de matériau de grille 108 est mise à nu et affleure sensiblement dans le plan de la surface d' aplanissement 124 de Ja couche 122.Then, after the elimination of the protective layer 110, the structure seen in section in FIG. 5 is obtained. The layer of grid material 108 is exposed and is exposed substantially in the plane of the leveling surface 124 of Ja layer 122.
A ce stade du procédé, on peut effectuer un dopage par implantation du silicium de la couche de grille. On implante des impuretés conduisant à une conductivité de type n ou p.At this stage of the process, doping can be carried out by implantation of the silicon of the gate layer. Impurities are implanted leading to an n or p type conductivity.
Le procédé se poursuit, comme le montre la figure 6, par la formation au-dessus de la couche de matériau de grille d'une couche 126 dite de shunt. La couche de shunt déposée en pleine plaque recouvre également la surface d ' aplanissement de la couche isolante 122. La couche de shunt 126 est réalisée de préférence en un polysiliciure de métal réfractaire. Elle est recouverte d'une couche d'oxyde déposé 128, non dope. La couche de shunt permet d'améliorer la prise de contact sur la grille et d'augmenter ainsi la vitesse de fonctionnement du transistor. Cette couche, lorsqu'elle est mise en forme, peut aussi constituer une ligne d'accès pour la polarisation de la grille, telle que, par exemple, une ligne de mots.The process continues, as shown in FIG. 6, by the formation above the layer of grid material of a layer 126 called shunt. The shunt layer deposited in full plate also covers the planarizing surface of the insulating layer 122. The shunt layer 126 is preferably made of a polysilicon of refractory metal. It is covered with a layer of deposited oxide 128, not doped. The shunt layer makes it possible to improve the contact on the gate and thus increase the operating speed of the transistor. This layer, when it is shaped, can also constitute an access line for the polarization of the grid, such as, for example, a line of words.
Un deuxième masque de gravure 130 formé sur la couche d'oxyde déposé 128 définit l'emplacement et les dimensions d'une structure de grille 132 au-dessus de la région active du transistor. La gravure successive de la couche d'oxyde 128, de la couche de shunt 126 et de la couche de matériau 108, avec arrêt sur la couche d'oxyde de grille 102 et sur la couche d'oxyde de flancs 120 permet d'obtenir la structure de la figure 7.A second etching mask 130 formed on the deposited oxide layer 128 defines the location and dimensions of a gate structure 132 above the active region of the transistor. The successive etching of the oxide layer 128, the shunt layer 126 and the material layer 108, with stopping on the gate oxide layer 102 and on the side oxide layer 120 makes it possible to obtain the structure of figure 7.
Il convient de noter que la figure 7 et les figures suivantes correspondent à un plan de coupe VI-VI, indiqué sur la figure 6, et qui fait un angle de 90° avec les plans de coupe des figures précédentes.It should be noted that FIG. 7 and the following figures correspond to a section plane VI-VI, indicated in FIG. 6, and which makes an angle of 90 ° with the section planes of the preceding figures.
L'extension latérale des gravures selon le deuxième masque 130 est limitée dans la zone située au- dessus de la portion de film mince 102 par l'oxyαe de flancs 120. Les gravures selon le masque 130 permettent ainsi de dégager la structure de grille 132 qui est donc nécessairement alignée sur la portion restante de film mince 102, c'est-à-dire alignée sur la future région active du transistor. La structure de grille comprend la couche de matériau de grille 108, la couche de shunt 126 et la couche d'oxyde dépose 128, mise en forme.The lateral extension of the etchings according to the second mask 130 is limited in the zone situated above the portion of thin film 102 by the oxidation of flanks 120. The etchings according to the mask 130 thus make it possible to release the grid structure 132 which is therefore necessarily aligned with the remaining portion of thin film 102, that is to say aligned with the future active region of the transistor. The grid structure includes the grid material layer 108, the shunt layer 126 and the shaped oxide layer 128, shaped.
Avantageusement, après l'élimination du masque 130, le procédé est poursuivi par une oxydation des flancs 134 de la structure de grille, c ' est-a-dire, en particulier, les couches de matériau de grille 103, et la couche de shunt 126. Il est possible également d'effectuer directement un dépôt d'oxyde fin sur les flancs .Advantageously, after the elimination of the mask 130, the process is continued by an oxidation of the sides 134 of the grid structure, that is to say, in particular, the layers of grid material 103, and the layer of shunt 126. It is also possible directly deposit a fine oxide on the sides.
Pour former les régions de source et de drain du transistor, une première implantation d'ions est effectuée dans le film mince 102 en utilisant la structure de grille 132 comme masque d'implantation. Les régions dopées formées lors de la première implantation sont représentées sur la figure 7. Et indiquées par la référence 135. Après la formation d'espaceurs latéraux 136 sur les flancs de la structure de grille et sur la couche d'oxyde de flancs 120 recouvrant la couche isolante 122, on effectue une deuxième implantation à une dose plus élevée. L'implantation est effectuée avec des impuretés conduisant à une conductivité n+ ou p+ selon le type canal de transistor réalisé.To form the source and drain regions of the transistor, a first implantation of ions is carried out in the thin film 102 using the grid structure 132 as implantation mask. The doped regions formed during the first implantation are shown in FIG. 7. And indicated by the reference 135. After the formation of lateral spacers 136 on the flanks of the grid structure and on the flank oxide layer 120 covering the insulating layer 122, a second implantation is carried out at a higher dose. The implantation is carried out with impurities leading to a conductivity n + or p + depending on the type of transistor channel produced.
Après l'implantation on effectue un recuit et on obtient la structure représentée à la figure 8. Sur cette figure les régions de source et de drain portent respectivement les références 140 et 142.After implantation, annealing is carried out and the structure shown in FIG. 8 is obtained. In this figure, the source and drain regions bear the references 140 and 142 respectively.
Les espaceurs latéraux 136 sont obtenus par le dépôt d'une couche qui permet d'isoler la grille des zones de contact 150 et 152, puis en attaquant cette couche par une gravure anisotrope, sélective par rapport à l'oxyde sur les flancs. Avantageusement, cette couche est en nitrure de silicium. Elle peut être en oxyde mais sa sélectivité lors de la gravure des espaceurs est moins bonne. Les espaceurs latéraux 136 ont non seulement pour fonction de former des régions de source et de drain graduelles mais aussi de protège1- ces régions au voisinage de l a grille et sur le bord de prises de contact réalisées ultérieurement. En particulier, les espaceurs 136 permettent d'éviter ou de limiter une attaque latérale de la couche 122 de matériau isolant (PSG) lors d'opérations de nettoyage qui précèdent la formation de prises de contact sur les régions de drain et de source.The lateral spacers 136 are obtained by depositing a layer which makes it possible to isolate the grid from the contact zones 150 and 152, then by attacking this layer by an anisotropic etching, selective with respect to the oxide on the flanks. Advantageously, this layer is made of silicon nitride. It can be made of oxide but its selectivity during the etching of the spacers is less good. The lateral spacers 136 have the function not only of forming gradual source and drain regions but also of protecting 1 - these regions in the vicinity of the grid and on the edge of contact points made subsequently. In particular, the spacers 136 make it possible to avoid or limit a lateral attack on the layer 122 of insulating material (PSG) during cleaning operations which precede the formation of contact points on the drain and source regions.
La formation des prises de contact sur les régions de source et de drain est précédée par l'élimination de la couche d'oxyde de grille résiduelle autour de la structure de grille, pour mettre a nu une partie du film mince 102 correspondant a la source et au drain.The formation of contact points on the source and drain regions is preceded by the elimination of the residual gate oxide layer around the gate structure, to expose a part of the thin film 102 corresponding to the source. and to the drain.
Lors de cette opération, les flancs oxydes de la structure de grille et l'oxyde αe flancs 120 recouvrant latéralement la couche 122 de matériau isolant, sont protèges par les espaceurs latéraux 136.During this operation, the oxide sides of the grid structure and the oxide sides 120 covering laterally the layer 122 of insulating material, are protected by the lateral spacers 136.
Une couche de métal 148, par exemple de tungstène, est ensuite formée par dépôt chimique en phase vapeur sur l'ensemble de la structure. Comme le montre la figure 9, la couche de métal 148 vient en contact avec les régions 140, 142 de source et de drain mises a nu et enrobe la structure de grille 132 La technique de dépôt du métal en phase vapeur (CVDj permet d'obtenir un dépôt conforme.A layer of metal 148, for example of tungsten, is then formed by chemical vapor deposition on the entire structure. As shown in FIG. 9, the metal layer 148 comes into contact with the exposed source and drain regions 140, 142 and coats the grid structure 132 The technique of metal deposition in the vapor phase (CVDj allows obtain a compliant deposit.
Par ailleurs, avant le dépôt de la couche de métal 148, la surface libre 124 de la couche 122 de matériau isolant peut être recouverte d'une couche 125 de titane/tungstene et avantageusement un système bicouche dont la composition permet d'assurer les fonctions de barrière de diffusion et αe barrière de contact II s'agit par exemple d'une couche de Ti-W dans une composition proche de la stoechiometrie. Cette couche, représentée a la figure 9, constitue une couche d'accrochage du métal et sert aussi de barrière de diffusion du métal dans l'isolant.Furthermore, before the deposition of the metal layer 148, the free surface 124 of the layer 122 of insulating material can be covered with a layer 125 of titanium / tungsten and advantageously a two-layer system whose composition makes it possible to perform the functions diffusion barrier and αe contact barrier It is for example a layer of Ti-W in a composition close to stoichiometry. This layer, represented in FIG. 9, constitutes a layer metal attachment and also serves as a diffusion barrier of the metal in the insulation.
De façon avantageuse les source et drain 140, 142 sont siliciurés avant le dépôt de la couche 125 en utilisant une siliciuration sélective sur le silicium à nu. La siliciuration permet de réduire la résistance a l'interface métal-semi-conducteur et améliorer ainsi les prises de contact sur les source et drain. Sur la figure 9 les parties siliciurées sont indiquées avec la référence 149.Advantageously, the source and drain 140, 142 are silicided before the deposition of the layer 125 using selective siliciding on the bare silicon. Siliconization makes it possible to reduce the resistance at the metal-semiconductor interface and thus improve the contacts made on the source and drain. In FIG. 9, the silicided parts are indicated with the reference 149.
Par la suite, comme le montre la figure 10, on procède a un polissage de la couche de métal pour l'aplanir jusqu'à la couche d'oxyde de silicium 128 de la structure de grille 132. La couche 125 est également polie à la suite.Thereafter, as shown in FIG. 10, the metal layer is polished in order to flatten it up to the silicon oxide layer 128 of the grid structure 132. The layer 125 is also polished to the following.
Enfin, la couche de métal et la couche d'accrochage peuvent, comme le montre la figure 11, être gravées pour la mise en forme de contacts 150, 152. D'autres opérations classiques αe dépôt de métaux ou d'isolants permettent de réaliser des interconnexions du transistor avec un circuit intégré. Ces opérations, connues en soi, ne sont pas détaillées ici .Finally, the metal layer and the bonding layer can, as shown in FIG. 11, be etched for the shaping of contacts 150, 152. Other conventional operations ae depositing metals or insulators make it possible to carry out interconnections of the transistor with an integrated circuit. These operations, known per se, are not detailed here.
La figure 11 montre aussi les caractéristiques du transistor objet de l'invention.FIG. 11 also shows the characteristics of the transistor which is the subject of the invention.
Les principales caractéristiques de ce transistor sont : une région active, formée dans la couche 102, dont les bords sont arrondis, une grille 108, 132 auto-alignee sur le canal dans la région active, une région active protégée par une couche d'isolation 122, et des contacts 150, 152 auto-alignés a la fois sur la grille et la couche d'isolation. On peut noter que la couche d'oxyde de flancs 120 qui s'étend sensiblement perpendiculairement a la région active permet d'éviter tout risque de recouvrement du métal des contacts sur les bords de la zone active, c'est-a-dire sur les flancs de la portion de film mince formant la zone active.The main characteristics of this transistor are: an active region, formed in layer 102, the edges of which are rounded, a gate 108, 132 self-aligned on the channel in the active region, an active region protected by an insulation layer 122, and contacts 150, 152 self-aligned on both the grid and the insulation layer. It can be noted that the flank oxide layer 120 which extends substantially perpendicular to the active region makes it possible to avoid any risk of covering the metal of the contacts on the edges of the active zone, that is to say on the sides of the thin film portion forming the active area.
Les matériaux isolants formant la couche d'oxyde de flanc 120 et la couche d'isolation 122 sont différents. La couche d'oxyde de flancs est formée par oxydation tandis que la couche 122 d'isolation est formée par dépôt.The insulating materials forming the flank oxide layer 120 and the insulation layer 122 are different. The sidewall oxide layer is formed by oxidation while the insulation layer 122 is formed by deposition.
Par ailleurs, la présence de la couche 120 d'oxyαe de flanc permet de ménager un décalage entre la zone active et la couche d'isolation 122. Tandis que la figure 11 illustre la réalisation d'un transistor a structure symétrique, la figure 12 montre un transistor, conforme a l'invention, oour lequel la structure de grille 132 n'est pas centrée par rapport aux flancs de la couche d'isolation 122. Le grille est cependant toujours parfaitement alignée par rapport au canal αe la région active Sur les figures 11 et 12, le canal est indique avec la référence 103.Furthermore, the presence of the sidewall oxyαe layer 120 makes it possible to provide a shift between the active zone and the insulation layer 122. While FIG. 11 illustrates the production of a transistor with a symmetrical structure, FIG. 12 shows a transistor, according to the invention, in which the gate structure 132 is not centered relative to the sides of the insulating layer 122. The gate is however always perfectly aligned with respect to the channel αe the active region Sur Figures 11 and 12, the channel is indicated with the reference 103.
Sur cette figure, il apparaît que les prises de contact 150, 152, formées sur les sources et drain 140, 142, sont auto-alignes sur la grille et la zone active et so-t disposées directement contre la structure de grille, en contact avec les espaceurs latéraux Les prises de contact 150, 152 constituent en quelque sorte des source et drain surélevés et métallisés.In this figure, it appears that the contact sockets 150, 152, formed on the sources and drain 140, 142, are self-aligned on the grid and the active area and are arranged directly against the grid structure, in contact with the lateral spacers The contact points 150, 152 constitute in a way raised and metallized source and drain.
Finalement, le procède et le transistor de l'invention permettent d'accroître la densité d'intégration et, comme indique oreceαemment , de faire l'économie d'une étape de masquage coûteuse et critique pour la réalisation des contacts sur les source et drain. Finally, the method and the transistor of the invention make it possible to increase the density of integration and, as indicated here or now, to make the economy of an expensive and critical masking step for making the contacts on the source and drain.

Claims

REVENDICATIONS
1. Procédé de réalisation d'un transistor sur un support de type SOI comprenant une couche d'oxyde de silicium (104) , dite couche d'oxyde enterrée, et un 5 film mince (102) de silicium recouvrant la couche d'oxyde enterrée (104) , le procédé comprenant les étapes successives suivantes : a) formation sur le film mince de silicium (102) d'un empilement (112) comprenant, dans l'ordre, une1. Method for producing a transistor on an SOI type support comprising a layer of silicon oxide (104), called buried oxide layer, and a thin film (102) of silicon covering the oxide layer buried (104), the method comprising the following successive steps: a) forming on the thin silicon film (102) a stack (112) comprising, in order, a
10 couche d'isolant de grille (106) , et une couche de matériau de grille (108) , b) formation sur l'empilement d'un premier masque de gravure (114) selon un motif correspondant à une région active du transistor,10 layer of gate insulator (106), and a layer of gate material (108), b) formation on the stack of a first etching mask (114) according to a pattern corresponding to an active region of the transistor,
!5 c) gravure de la couche de matériau de grille (108) , de la couche d'isolant de grille (106) et du film mince! 5 c) etching of the grid material layer (108), the grid insulation layer (106) and the thin film
(102) , pour former une colonne (116) avec des premiers flancs (118) définis selon le motif du premier masque de gravure, 0 d) formation d'une couche (122) de matériau isolant électrique autour de la colonne (118) et aplanissement de cette couche avec arrêt sur la colonne, e) gravure de la couche de matériau de grille (108) de 5 la colonne (118) selon un deuxième masque (130) pour former une structure de grille (132) avec des deuxièmes flancs (134) , f) isolation électrique des deuxièmes flancs (134) de la structure de grille (132) , 0 g) formation de régions de source (140) et de drain (142) dans le film mince (102) par implantation d ' impuretés, h) formation auto-alignée sur la structure de grille de prises de contact (150, 152), sur les régions de source et de drain.(102), to form a column (116) with first flanks (118) defined according to the pattern of the first etching mask, 0 d) formation of a layer (122) of electrical insulating material around the column (118) and flattening this layer with stop on the column, e) etching the grid material layer (108) of the column (118) according to a second mask (130) to form a grid structure (132) with second flanks (134), f) electrical insulation of the second flanks (134) of the grid structure (132), 0 g) formation of source (140) and drain (142) regions in the thin film (102) by implantation impurities, h) self-aligned formation on the contact grid structure (150, 152), on the source and drain regions.
2. Procédé selon la revendication 1, caractérisé en ce qu'il comporte en outre lors de l'étape a) la formation d'une couche de protection (110) au-dessus de la couche de matériau de grille (108), la couche de protection étant également gravée lors de l'étape c) , et formant une couche d'arrêt lors de aplanissement de la couche de matériau isolant (122) à l'étape d) et la couche de protection étant éliminée après 1 ' étape d) .2. Method according to claim 1, characterized in that it further comprises during step a) the formation of a protective layer (110) above the layer of grid material (108), the protective layer also being etched during step c), and forming a stop layer when planarizing the layer of insulating material (122) in step d) and the protective layer being removed after step 1 d).
3. Procédé selon la revendication 1, caractérisé en ce que le premier masque de gravure (114) est éliminé avant l'étape d) .3. Method according to claim 1, characterized in that the first etching mask (114) is eliminated before step d).
4. Procédé selon la revendication 1, caractérisé en ce qu'il comporte en outre, avant l'étape d) une oxydation des flancs (118) αe la colonne formée a l'étape c) , pour les recouvrir d'une couche (120) dite d'oxyde de flancs.4. Method according to claim 1, characterized in that it further comprises, before step d) oxidation of the sides (118) αe the column formed in step c), to cover them with a layer ( 120) called flank oxide.
5. Procédé selon la revendication 4, caractérisé en ce que la gravure de l'étape e) est effectuée avec arrêt sur les couches d'oxyde de grille (106) et d'oxyde de flancs (120) . 5. Method according to claim 4, characterized in that the etching of step e) is carried out with stop on the gate oxide layers (106) and flank oxide (120).
6. Procédé selon la revendication 4, caractérisé en ce que l'oxydation des flancs est effectuée à haute température et/ou à haute pression.6. Method according to claim 4, characterized in that the oxidation of the flanks is carried out at high temperature and / or at high pressure.
7. Procédé selon la revendication 1, caractérisé en ce qu'il comporte en outre après l'étape d) et la mise à nu du matériau de grille (108) , la formation d'une couche (126) dite de shunt recouvrant la couche de matériau isolant électrique (122) et venant en contact avec le matériau de grille (108) , la couche de shunt étant également gravée lors de l'étape e) selon le deuxième masque de gravure (130) et des deuxièmes flancs de la couche de shunt, formes lors de l'étape e) étant également isolés électriquement lors de 1 ' étape f) .7. Method according to claim 1, characterized in that it further comprises after step d) and the exposure of the grid material (108), the formation of a layer (126) called shunt covering the layer of electrical insulating material (122) and coming into contact with the grid material (108), the shunt layer also being etched during step e) according to the second etching mask (130) and second flanks of the shunt layer, shapes during step e) also being electrically insulated during step f ).
8. Procédé selon l'une quelconque des revendications précédentes, caractérisé en ce que la formation de prises de contact, lors de l'étape h) , comporte le dépôt auto-aligné d'une couche de métal (148) et le polissage de cette couche de métal (148) .8. Method according to any one of the preceding claims, characterized in that the formation of contact points, during step h), comprises the self-aligned deposition of a layer of metal (148) and the polishing of this metal layer (148).
9. Procédé selon la revendication 8, caractérisé en ce qu'il comporte l'élimination de la couche d'oxyde de grille (106) mise a nue de part et d'autre de la structure de grille (132) lors de l'étape e) et une siliciuration auto-alignee de la couche de métal (148) avec le film mince (102) mis à nu par 1 ' élimination de la couche d'oxyde de grille (106) .9. Method according to claim 8, characterized in that it comprises the elimination of the gate oxide layer (106) exposed on either side of the gate structure (132) during the step e) and a self-aligned siliciding of the metal layer (148) with the thin film (102) exposed by the elimination of the gate oxide layer (106).
10. Procédé selon la revendication 8, caractérisé en ce que la couche de métal (148) est déposée selon une technique de dépôt chimique en phase vapeur (CVD) .10. Method according to claim 8, characterized in that the metal layer (148) is deposited according to a chemical vapor deposition (CVD) technique.
11. Procède selon la revendication 8, caractérisé en ce qu'il comporte la formation d'une coucne (125) d'accrochage et/ou de barrière de diffusion sur la couche de matériau isolant (122) avant le dépôt de la couche de métal (148) .11. Method according to claim 8, characterized in that it comprises the formation of a coucne (125) for attachment and / or diffusion barrier on the layer of insulating material (122) before the deposition of the layer of metal (148).
12. Procédé selon la revendication 1, caractérise en ce que la formation des régions de source et de drain comporte : - une première implantation d'impuretés dopantes a faible dose, - la formation d'espaceurs latéraux (136) sur les deuxièmes flancs de la grille et, le cas échéant, sur la couche de shunt, ainsi que sur les flancs de la couche de matériau isolant (122) , - une deuxième implantation d'impuretés dopantes à une dose supérieure à la dose de la première implantation.12. Method according to claim 1, characterized in that the formation of the source and drain regions comprises: - a first implantation of doping impurities at low dose, - the formation of lateral spacers (136) on the second flanks of the grid and, if applicable, on the shunt layer, as well as on the sides of the layer of insulating material (122), - a second implantation of doping impurities at a dose greater than the dose of the first implantation.
13. Procédé selon la revendication 12, caractérisé en ce que la formation des espaceurs latéraux comporte le dépôt d'une couche de nitrure de silicium puis la gravure anisotrope de cette couche. 13. Method according to claim 12, characterized in that the formation of the lateral spacers comprises the deposition of a layer of silicon nitride then the anisotropic etching of this layer.
14. Procédé selon la revendication 1, caractérisé en ce que la couche de matériau (122) isolant électrique formée lors de l 'étape d) est réalisée en un matériau choisi parmi le PSG et le BPSG.14. Method according to claim 1, characterized in that the layer of electrically insulating material (122) formed during step d) is made of a material chosen from PSG and BPSG.
15. Procédé selon la revendication 1, caractérisé en ce qu'il comprend en outre la formation de lignes d'interconnexion reliées aux source et drain du transistor par l'intermédiaire des prises de contact .15. The method of claim 1, characterized in that it further comprises the formation of interconnection lines connected to the source and drain of the transistor via the contact sockets.
16. Procédé selon la revendication 2, caractérisé en ce que la couche de protection (110) est réalisée en nitrure de silicium.16. The method of claim 2, characterized in that the protective layer (110) is made of silicon nitride.
17. Procédé selon la revendication 2, caractérisé en ce qu'on effectue un dopage de la couche de grille (108) après l'élimination de la couche de protection.17. The method of claim 2, characterized in that doping of the gate layer (108) after removal of the protective layer.
18. Procédé selon la revendication 1, caractérisé en ce que la couche de grille (108) est réalisée en un matériau choisi parmi le silicium polycπstallm et le silicium amorphe. 18. The method of claim 1, characterized in that the gate layer (108) is made of a material chosen from polycπstallm silicon and amorphous silicon.
19. Transistor a effet de champ comprenant une source (140) , un canal (103) et un drain (142) formes dans une portion de film (102) de silicium d'une structure de type silicium sur isolant (SOI) , une couche (122) d'isolation de champ entourant latéralement la portion de film (102) de silicium, une structure de grille (132) a flancs isoles formes au- dessus du canal, et des contacts (150, 152) de source 5 et de drain ménagés sur la portion de film (102) de silicium entre la couche d'isolation de champ (122) et la structure de grille (132), caractérise en ce que les contacts (150, 152) de source et de drain sont auto- alignes sur la structure de grille (132) et sur la 10 couche d'isolation de champ (122) et sont directement disposes contre les flancs de la structure de grille, les contacts étant en outre délimites par une couche (120) dite d'oxyde de flancs, sensiblement perpendiculaire a la portion de film (102) de silicium, b et auto-alignee sur la couche d'isolation de champ (122)19. Field effect transistor comprising a source (140), a channel (103) and a drain (142) formed in a portion of silicon film (102) of a silicon-on-insulator (SOI) structure, a layer (122) of field insulation laterally surrounding the portion of silicon film (102), a grid structure (132) with isolated flanks formed above the channel, and contacts (150, 152) of source 5 and drain formed on the silicon film portion (102) between the field insulation layer (122) and the gate structure (132), characterized in that the source and drain contacts (150, 152) are self-aligned on the grid structure (132) and on the field insulation layer (122) and are directly arranged against the sides of the grid structure, the contacts being further delimited by a layer (120) called of flank oxide, substantially perpendicular to the portion of silicon film (102), b and self-aligned on the field insulation layer (122)
20. Transistor selon la revendication 19, caractérise en ce que la structure de grille comporte un empilement comprenant une coucne d'isolant de grille 0 (106) et une coucne de matériau do grille (108) , et des espaceurs laterau< (136) entourant la grille et formant les flancs de la structure de grille20. Transistor according to claim 19, characterized in that the grid structure comprises a stack comprising a layer of grid 0 insulation (106) and a layer of grid material (108), and side spacers <(136) surrounding the grid and forming the sides of the grid structure
21 Transistor selon la revendication 20, caractérise en ce que l'empilement comporte en outre 5 une couche dite de shunt (126) , formant une prise de contact sur la grille (108) , la couche de shunt étant également entoure: par les espaceurs laterau\ (136) 21 Transistor according to claim 20, characterized in that the stack further comprises a layer called shunt (126), forming a contact on the grid (108), the layer of shunt also being surrounded by: the spacers laterau \ (136)
EP97930599A 1996-06-27 1997-06-26 Method for producing a transistor with self-aligned contacts and field insulation Withdrawn EP0958602A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR9608007 1996-06-27
FR9608007A FR2750534B1 (en) 1996-06-27 1996-06-27 TRANSISTOR AND METHOD FOR PRODUCING A CONTACTS AND SELF-ALIGNED FIELD ISOLATION TRANSISTOR
PCT/FR1997/001146 WO1997050118A1 (en) 1996-06-27 1997-06-26 Method for producing a transistor with self-aligned contacts and field insulation

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EP0958602A1 true EP0958602A1 (en) 1999-11-24

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EP97930599A Withdrawn EP0958602A1 (en) 1996-06-27 1997-06-26 Method for producing a transistor with self-aligned contacts and field insulation

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US (1) US6150241A (en)
EP (1) EP0958602A1 (en)
JP (1) JP2000514241A (en)
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WO (1) WO1997050118A1 (en)

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FR2839202A1 (en) * 2002-04-26 2003-10-31 St Microelectronics Sa MOS transistor assembly on a silicon substrate with each active zone delimited by an insulating layer
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WO1997050118A1 (en) 1997-12-31
JP2000514241A (en) 2000-10-24
FR2750534A1 (en) 1998-01-02
US6150241A (en) 2000-11-21
FR2750534B1 (en) 1998-08-28

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