EP0720389B1

EP0720389B1 - Prevention of jitter on the output image of a video camera

Info

Publication number: EP0720389B1
Application number: EP96101752A
Authority: EP
Inventors: Hiroyasu Ohtsubo; Kazuhiro Koshio
Original assignee: Hitachi Ltd
Current assignee: Hitachi Ltd
Priority date: 1990-10-31
Filing date: 1991-10-29
Publication date: 2001-04-04
Anticipated expiration: 2011-10-29
Also published as: US5483290A; EP0483745A2; EP0720389A1; DE69127950T2; DE69132577D1; EP0483745A3; KR940005173B1; DE69127950D1; EP0483745B1; DE69132577T2; US5287171A

Description

This is a divisional application out of European patent application EP-A-0 438 745 (EP 91 118 399.4) related to a video camera of the type as described in the preamble of claim 1 with digitized image processing. Digital color signal processing is performed on the basis of two timing clocks with a first clock which is in synchronism with the scanning cycle of the image signal and a second clock with a frequency n times the frequency of a color subcarrier depending on the color television system used. Video cameras of this type are known in the art as described, for example, in Japanese patent publication no. JP-A-63045153 or US-patent no. US-A-4 626 898.
An image is picked up by the solid-state CCD sensor of the video camera. The sensor adopts several values as the number of horizontal pixels. Since the horizontal scanning period is fixed, different frequencies of the horizontal pixel read clock (sensor clock) corresponding to the number of pixels must be provided for each different scanning system. For example, the sensor clock frequency (fs) for an NTSC color television system includes the values of 9.5 MHz, 12.7 MHz, 14.3 Mhz, etc. Generally, the signal processing in the digital camera is desired to be performed in synchronism with the sensor clock because of its easiness and merit of small-sized circuits. Now it should be noted that the signal processing in the encoder must be done with a clock n (n = 3 or 4) times larger than the frequency of the color subcarrier (fsc). Therefore, if in digitizing all the signal processings in a camera the relation fs = n·fsc (n = 3, 4, 6, 8, etc.) is not satisfied (the phase of a high clock is not fixed for), jitter of (n·fs)^-1 is generated in the transfer of data to the encoder. Now, if n = 4, the jitter is for NTSC (4 fsc)^-1 = 70 ns, and for PAL (4 fsc)^-1 = 56 ns. . For example, if the number of sensor clocks in the horizontal period is 550, then 1/fs = 1H/550 = 115 ns. Such a large timing difference will produce jitter in the output image visible to human eyes.
The range of jitter permitted for the color signal is 35 ns or less so that it is apparent that the above jitter is outside the permissible range. It was found that n must be 8 or greater in order to stay within the permitted range. However, actually, the signal processing based on the oscillation at 8 fsc (NTSC 28.6 MHz, PAL 35.44 Mhz) suffers from the following defects:
1. The oscillation is likely to be unstable so that strict specifications for an oscillator would be required. Furthermore, the power consumption of the oscillator is doubled.
2. The response time and switching speed for a gate used in an encoder circuit is required twice as high as before so that strict specifications are required for components also. The power consumption for the encoder circuit is increased. For this reason, actually, the signal processing is to be done only with clocks of 4 fsc or less.
The prior art devices suffer from further defects. In converting the signal processing in the video camera from an analog system to a digital system, no consideration on taking synchronization of a luminance signal with a sync signal, when the luminance signal is supplemented with the sync signals, is made although the luminance signal is synchronous with the sensor clock fs and the sync signals are synchronous with n·fsc.
Further, since the horizontal read clock frequency for the sensor is fixed at a certain value, the video camera cannot deal with the sensor being fixed at a different clock frequency; the video camera, therefore, does not have sufficient versatility.
It is, therefore, an object of the present invention to provide a video camera performing all the signal processings in digitized form including the encoder which can keep the jitter within a permitted range (35 ns or less) when 4 fsc is used as the data processing clock, this resulting in a video camera of low power consumption and small-size/light weight.
Another object of the present invention is to provide a video camera comprising a digital signal processor which prevents jitter from being generated on an output image, and a programmable synchronization signal clock generating means (TG, SSG) which is controlled by a microcomputer to make the timing of the sync signal variable, thereby dealing with sensors having several different specifications.
These and other objects are achieved in an advantageous manner basically by applying the features laid down in the characterizing part of claim 1. Further enhancements are provided by the dependent claims.

SUMMARY OF THE INVENTION

In order to keep the jitter within the permitted range, the video camera according to the present invention as defined in claim 1 comprises an A/D converter for converting the image signal from the CCD sensor into a digital signal synchronously with a sensor clock, a signal processor for processing the digitized image signal on the basis of a sensor clock to generate a luminance signal and a color difference signal, an encoder for balanced-modulating the color difference signal on the basis of a clock at the period of 4 times fsc (in the following referred to as 4fsc clock), and a D/A converter for converting the two digitized signals (luminance and color) after modulation into resulting analog signals for viewing by the human eyes.
Further, in order to prevent the jitter from being generated, there is provided a sync signal generating circuit (SSG) comprising two units, i.e. an nfsc unit for generating horizontal and vertical sync signals for a sensor using the signal at the frequency of nfsc as a clock and an fs unit for generating the sync signal for the TV.
Another embodiment comprises a programmable SSG which can change the timing of the sync signal for the TV unit generated by the fs timing unit in order to deal with several sensors having different specifications, and a microcomputer for controlling it.
Still another embodiment comprises a signal switching circuit for alternately supplying the sync signals for the luminance signal and the TV unit to the D/A converter, and a clock switching circuit for alternately supplying the clock at the frequency nfsc and the sensor clock fs as a clock for the D/A converter.
In the first embodiment mentioned above, when the clock at the frequency of nfsc is supplied, the nfsc unit processes timing pulse sequences, e.g. by a counter, to generate a horizontal sync signal (CHD) and a vertical sync signal (VD) for the video camera which are supplied to the sensor driving timing generator TG. TG generates a sensor clock fs using a signal synchronous with the CHD and supplies several kinds of control signals including the sensor clock fs to the digital signal processor and the fs unit in the SSG. The digital signal processor performs a signal processing using the sensor clock fs as a clock to generate the luminance signal and the color difference signal. On the other hand, using the sensor clock fs as a clock, the fs unit also generates the sync signals such as a composite sync signal (CSYNC) for a TV. Therefore, the luminance signal and the sync signals are synchronous with the sensor clock fs so that the luminance signal is synchronous with the sync signals. Thus, when the digital signal processor supplements the luminance signal with the sync signals, only a short timing difference occurs which prevents jitter.
In the second embodiment mentioned above, if timing data which are latched in a state holding circuit, control signals such as the sensor clock and the vertical sync signal are supplied from the microcomputer, TG and the nfsc unit, respectively, the fs unit processes the value of a counter having fs as clock with said timing data, thereby generating a horizontal sync signal and synthesizes the horizontal sync signal and the vertical sync signal supplied from the nfsc unit to produce the required sync control signals. Thus, if the timing data supplied from the microcomputer to the fs unit are set for the specification of a sensor used, the sync signals applicable to the sensor can be generated, thereby realizing versatility for plural sensors having different specifications.
In the third embodiment mentioned above, during a horizontal blanking period and at the time (point A) when the luminance signal is at a predetermined level before the horizontal blanking period and horizontal synchronizing period, the signal switching circuit is switched on the side of the sync signals and also the clock switching circuit is switched on the side of the nfsc so that the sync signals are supplied, using the nfsc clock, to the D/A converter. Likewise, during the horizontal blanking period and at the time (point B) when the luminance signal is at a predetermined level after the horizontal blanking period, the signal switching circuit and the clock switching circuit are switched opposite to the above so that an analog luminance signal is produced from the D/A converter. Therefore, even if the luminance and the sync signals are not synchronous with each other at the points A and B, because of the fixed level of the luminance signal, no jitter is generated.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, features and advantages of this invention will be apparent from consideration of the following description of preferred embodiments of a video camera taken in connection with the accompanying drawings listed as follows:

Fig. 1: is a block diagram of the video camera according to a preferred embodiment of the present invention;
Fig. 2: is a block diagram showing details of the sync signal generating unit SSG of Fig. 1;
Fig. 3: is a block diagram showing details of the digital signal processor;
Fig. 4: is a block diagram showing details of the programmable sync signal generating circuit SSG of Fig. 1;
Fig. 5: is a modification of the embodiment of Fig. 1;
Fig. 6: is a timing chart of the sync signals of Fig. 5;
Fig. 7: is a block diagram of a modification of the latch circuit and the horizontal sync circuit of Fig. 5;
Fig. 8: is a block diagram of the video camera according to another embodiment of the present invention;
Fig. 9: is a block diagram of the video camera according to yet another embodiment of the present invention;
Fig. 10A: is a block diagram of a circuit for supplying the luminance and sync signals to the D/A converter of the video camera;
Fig. 10B: is a timing chart for explaining the operation of the signal switching circuit of Fig. 10A;
Fig. 11: is a waveform of the luminance signal supplemented with the sync signals of Fig. 10;
Figs.12 to 14: are schematic block diagrams of video cameras according to further embodiments.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Now, referring to the accompanying drawings, an explanation will be given of several embodiments of the present invention.
The video camera system according to the embodiment of Fig. 1 is composed of a sensor 1, an analog/digital converter (A/D) 2, a digital signal processor 3, a digital/analog converter (D/A) 4, a sensor driving timing generating circuit (TG) 5, an oscillation circuit 51, a sync signal generating circuit (SSG) 6 and an oscillation circuit 61.
The operation of the video camera system will now be explained. The sensor 1, when having received an optical image signal 11, produces for each one horizontal scanning period an analog pixel signal 12 composed of repeated color signals which are synchronous with the sensor clock having the frequency fs and alternately different. The operation of the sensor 1 is controlled by the control signal 18 from the TG 5. The A/D 2, when it receives the analog pixel signal from the sensor 1, converts it into a digital pixel signal 13 which is in turn supplied to the digital signal processor 3. The digital signal processor 3, when it receives the digital pixel signal 13 from the A/D 2, the control signal 18 from the TG 5, and the sync signal 20 and control signal 23 from SSG 6, produces a luminance signal 14 and a color signal 15 supplemented with the sync signal, respectively which are supplied to the D/A 4. The D/A 4, when it receives the luminance signal 14 and the color signal 15 supplemented with the sync signal, converts these two signals 14 and 15 into analog signals to produce a luminance signal 16 and a color signal 17 supplemented with the analog sync signal, respectively. Additionally, the SSG 6 creates the sync signal 20 on the basis of the control signal 18. And, the TG 5 creates the control signal 18 on the basis of the control signal 19 sent from the SSG 6 and the reference signal 50 sent from the oscillation circuit 51.
Fig. 2 shows a concrete arrangement of the SSG 6. In Fig. 2, the SSG 6 is composed of a n·fsc unit 62 and a fs unit 63. Further, the n fsc unit 62 is composed of a horizontal sync signal generating circuit 621 and a vertical sync signal generating circuit 622, and the fs unit is composed of a horizontal sync signal generating circuit 633 and a sync signal creating circuit 635. The operation of the SSG 6 will be explained below.
First, when the n fsc unit 62 receives the signal 60 at the frequency of n fsc from the oscillation circuit 61, the horizontal sync signal generating circuit 621 generates a horizontal sync signal 623 which is sent to the vertical sync signal generating circuit 622. The vertical sync signal generating circuit 622, when it receives the horizontal sync signal 623, from the horizontal sync signal generating circuit 621, generates a vertical sync signal 625 which is supplied to the sync signal creating unit 635 in the fs unit 63. Further, the n·fsc unit 62 sends to the TG 5, as the control signals 19, the signal (CHD) 624 for creating the signal horizontally driving the sensor 1 in the horizontal sync signal 623 and the signal (VD) 626 for creating the signal vertically driving the sensor 1 in the vertical sync signal 625. The TG 5, which receives the control signals 19 from the SSG 6, takes the phase lock of the signal obtained by frequency-dividing the reference signal 50 supplied from the oscillation circuit 50 with the CHD 624 and creates the control signals such as the sensor clock at the frequency of fs from the above reference signal 50; the control signals 18 are sent to the fs unit 63 in the SSG 6. The horizontal sync signal generating circuit 633, when it receives the control signals 18, generates a horizontal sync signal 638 synchronous with the sensor clock fs which is supplied to the sync signal creating circuit 635. The sync signal creating circuit 635, when it receives the vertical sync signal 625 from the vertical sync signal generating circuit 622, the horizontal sync signal 638 from the horizontal sync signal generating circuit 633, creates sync signals (CSYNC, CBLK, BF) 20 which are supplied to the digital signal processing circuit 3. It should be noted that the horizontal sync signal 638 and the vertical sync signal 625 are synchronous with the sensor clock fs so that the sync signals are also synchronous with the sensor clock fs.
Fig. 3 shows a concrete arrangement of the digital signal processing circuit 3. The digital signal processing circuit 13 is composed of a Y/C separation circuit 31, a Y process circuit 32, a C process circuit and a CSYNC supplementing circuit 34, a BF supplementing circuit 35 and a modulation circuit 36. The operation of the digital signal processing circuit 3 will be explained below.
First, the Y/C separation circuit 31, when it receives the digital pixel signal 13 from the A/D 2, creates the first pixel signal 301 which is a luminance signal obtained by extracting the luminance component from the output signal from the A/D 2, and the second pixel signal 302 which is a color signal also extracted from the output signal from the A/D 2; these two signals are supplied to the Y process circuit 32 and the C process circuit 33, respectively. The Y process circuit 32, when it receives the first pixel signal 301 and the second pixel signal 302 from the Y/C separation circuit 31, creates a luminance signal 303 to be supplied to the CSYNC supplementing circuit 34. On the other hand, the C process circuit 33, when it receives the first pixel signal 301 and the second pixel signal 302 from the Y/C separation circuit 31, creates color difference signals 304 to be supplied to the BF supplementing circuit 35. Additionally, the Y/C separation circuit 31, the Y process circuit 32 and the C process circuit 33, which are controlled by the control signals 18 supplied from the TG 5, are phased-locked with the sensor clock fs. Therefore, the luminance signal 303 and the color difference signals 304 are also synchronous with the sensor clock fs, respectively. The sync signals supplied from the SSG 6 include three signals of CSYNC 305, CBLK 306 and BF 307. The CSYNC supplementing circuit 34, when it receives the luminance signal 303 from the Y process circuit 32, and CSYNC 305 and CBLK 306 from the SSG 6, creates the luminance signal 14 supplemented with the sync signals 20. On the other hand, the BF supplementing circuit 35, when it receives the color difference signals 304 from the C process circuit 33, and BF 305 and CBLK 306 from the SSG 6, creates the color difference signals 308 supplemented with the sync signals; the color difference signals are supplied to the modulation circuit 36. The modulation circuit 36, when it receives the color difference signal supplemented with the sync signals from the BF supplementing circuit 35 and the control signal 23 from the SSG 6, generates the color signal 15 supplemented with the sync signals. Thereafter, the D/A 4 converts the luminance signal 14 and the color signal 15 supplemented with the sync signals into the analog luminance signal 16 and the analog color signal 17, respectively.
In accordance with the embodiment shown in Figs. 1 to 3, the signal processing is controlled by the sensor clock and the sync signals are also created on the basis of the sensor clock so that the digital luminance signal is made synchronous with the sync signals; thus, it is possible to prevent the jitter from being generated in synthesizing the above two signals.
Now referring to Figs. 4 to 7, a modification of this embodiment will be explained below. The basic arrangement of video camera system according to this modification is substantially the same as that shown in Fig. 1 , but is different from the latter in that the SSG 6 is replaced by a programmable SSG 65 and a microcomputer 7 for controlling it is provided.
Fig. 4 shows a concrete arrangement of the programmable SSG 65 and the microcomputer 7. In Fig. 4, the SSG 65 is composed of an n fsc unit 62 and a fs unit 64; the fs unit is composed of a counter 631, a latch circuit 632, a horizontal sync signal generating circuit 634 and a sync signal creating circuit 635. The n fsc unit 62 and the sync signal creating circuit 635 are entirely the same as those in the SSG 6 in Fig. 2. Fig. 5 shows the details of each block in the fs unit 64. In Fig. 5, the latch circuit 632 is composed of latch circuits 632a and 632b, and the horizontal sync signal generating circuit 634 is composed of a comparator circuit 634a and a pulse generating circuit 634b. In Fig. 5 , a signal 22 denotes timing data including a data 22a and an address 22b; signals 639 and 640 denote output signals from the comparator 634a; and a signal 638 denotes a horizontal sync signal. Fig. 16 shows a timing chart for explaining the process of creating the horizontal sync signal 638. With reference to Figs. 4 to 6, the operation of the SSG 65 and the microcomputer 7 will be explained below.
In Fig. 4, the microcomputer 7 sends to the latch circuit 632 the timing data (set as a and b in the microcomputer 7) for creating the sync signals adapted to the specification of the sensor 1 whereby the data 22a is latched in the latch circuit 632. The latch circuit (632a or 632b) in which the data 22a should be latched is determined in accordance with the address 22b. Now it is assumed that a value a is held in the latch circuit 632a while a value (a + b) is held in the latch circuit 632b. The values a and (a + b) are two points apart from a time b. Thus, if the values of a and (a + b) are set in the respective latch circuits, the sync signal with a synchronization b can be generated. Namely, if the values a and b are set as input data for the microcomputer 7, a programmable SSG can be realized.
The counter 631, when it receives the control signal 18 from the TG 5, counts the sensor clock fs (number of clocks); the counted value 636 is supplied to the comparator circuit 634a in the horizontal sync signal generating circuit 634. The comparator circuit 634a, when it receives timing data 637a and 637b from the latch circuit 632 and the counted value 636 from the counter 631, examines if the counted value 636 coincides with the timing data 637a or 637b, and outputs '1' or '0' in accordance with the absence or presence of the coincidence. Namely, the comparator circuit 634a produces signals 639 and 640 in the timing chart of Fig. 6. The pulse generating circuits 634b, when it receives the signals 639 and 640, generates the sync signal 638 as shown in Fig. 6 which is in turn sent to the sync signal creating circuit 635. The sync signal creating circuit 635, when it receives the vertical sync signal 625 from the vertical sync signal generating circuit 622 and the horizontal sync signal 638 from the horizontal sync signal generating circuit 634, creates sync signals including CSYNC, CBLK and BF which are in turn sent to the digital signal processing circuit 3. The succeeding operation is the same as in the embodiment of Fig. 1 .
Although in the above modified embodiment, the fs unit 64 has been explained only in connection with the arrangement of Fig. 5, a plurality of latch circuits 632 connected in series with a plurality of pulse generating circuits 634 may be arranged in such a manner that signal input/output switches SW1 and SW2 are synchronously connected with any series connection of these latch circuits and pulse generating circuits, thereby providing a plurality of horizontal sync signals defined by series connections of the latch circuits 632 and the pulse generating circuit 634. Further, the latch circuit 632 may be replaced by any component as long as it has a state holding function.
In accordance with the above modified embodiment shown in Figs. 4 to 7, the programmable SSG and the microcomputer for controlling it are provided so that the timing of the horizontal sync signal can be made variable. Therefore, the sync signal adapted to the sensor to be used can be generated so that the video camera can deal with a plurality of kinds of sensors.
A further modified embodiment of the present invention will be explained below. The basic arrangement of the video camera system according to this embodiment is substantially the same as that in Fig. 1 except the arrangement of Fig. 8. The operation of each of the respective blocks is also the same as that of each of the corresponding blocks in Fig. 1 . As seen from Fig. 8, the video camera according to this embodiment is characterized by the provision of a programmable TG 9 and a microcomputer 7 for controlling it. The programmable TG 9, when it receives the timing data 22 from the microcomputer 7 and the sync signals from the SSG 6, a necessary timing control signal by the same latch circuit and pulse generating circuit as those included in the fs unit 64 in the programmable SSG 65 in Fig. 4.
In accordance with the embodiment of Fig. 8, the sensor driving pulse and the control signal for signal processing can be changed in accordance with the kind of the sensor and the system arrangement.
A still further modified embodiment of the present invention will be explained below. Fig. 9 shows the basic arrnagement of the video camera system according to this embodiment. This video camera is composed of a sensor 1, an A/D 2, a digital signal processing circuit 3, a D/A 4, a TG 52, a programmable SSG 6, a control circuit 10 and an oscillation circuit 51.
The operation of the video camera system thus arranged will be explained. Since the respective operations of the sensor 1, the A/D 2, the digital signal processing circuit 3 and the D/A 4 are the same as those of the corresponding components in the embodiment of Fig. 1 , only the operations of the other components will be explained below. First, the oscillation circuit 51 supplies a reference signal 50 to the TG 52. The TG 52, when it receives the reference signal 50 from the oscillation circuit 51, frequency-divides the reference signal 50 to create a control signal 191 such as the sensor clock fs and a sensor driving signal 181 for driving the sensor 1 which are in turn sent to the programmable SSG 66 and the sensor 1, respectively. The programmable SSG 66 comprises the same circuits as the fs unit 64. So, through the same process as in the fs unit 64, the programmable SSG 6, when it receives the timing data 22 for generating the sync signals adapted to several sensors from the exterior and the control signal 191 such as the sensor clock fs from the TG 52, creates the sync signals 20 synchronous with the sensor clock fs and the control signals 25 which are in turn sent to the digital signal processing circuit 3 and the control circuit 10, respectively. The control circuit 10, when it receives the control signals from the programmable SSG 66, supplies the control signals such as a clock to the A/D 2, and supplies the control signals such as the sensor clock fs to the digital signal processing circuit 3. Thereafter, the video camera system according to this embodiment produces the analog luminance signal and color signal supplemented with the sync signals through the same process as in video camera system according to the embodiment of Fig. 1 .
In accordance with this embodiment, provided is the programmable SSG 66 which can generate sync signals at different timings on the basis of data (information such as a and b required to create sync signals) externally supplied so that the video camera can deal with a plurality of kinds of sensors.
A further modified embodiment of the present invention will be explained. The basic arrangement of the video camera according to this embodiment is that of Fig. 9 further provided with a microcomputer 7 and an input terminal 71 for data rewrite. In Fig. 19, the microcomputer 7 temporarily holds data 72 inputted through the terminal 71 and further supplies the data 72 to the programmable SSG 66 as the timing data 22 to rewrite the timing data held in the SSG 66. It should be noted that the data 72 should be not limited to the timing data 22 and the microcomputer 7 can execute not only the above operation but also control the other circuits as required using the data 72.
As a further modified embodiment, as shown in Fig. 12, the arrangement of Fig. 9 may be provided with a ROM 73. In this case, with the data 72 stored in the ROM 73, the data can be supplied from the ROM 73 to the microcomputer 7. In accordance with this embodiment in which the microcomputer 7 and the ROM 73 for storing the data to be supplied to the microcomputer 7, the programmable SSG66 can generate the sync signals adapted to the used sensor using the timing data supplied from the microcomputer so that the video camera system according to this embodiment can deal with a plurality of sensors. The video camera can be automatically set up in its start.
As a further modified embodiment, the arangement of Fig. 12 may be modified into that as shown in Fig. 13. In this case, with the same data as the data 72 stored in a ROM 73, the data timing data 22 which is part of the data stored in the ROM 73 is directly supplied to the programmable SSG 66.
Referring to Fig. 14, a further modified embodiment will be explained. The basic arrangement of the video camera according to this embodiment is substantially the same as that of Fig. 9 except the provision of the arrangement of Fig. 14. In Fig. 14, a microcomputer 70 stores several kinds of timing data corresponding to individual systems, and a programmable ROM 74 stores the codes allotted to the respective systems and control data. A system selection data 78 is supplied to the microcomputer 70 through an input terminal 76. The microcomputer 70, when it receives the system selection data 78, reads, from the programmable ROM 74, system data 77 including the code designated by the selection data 78 and the control data, and supplies to the programmable SSG 66 the timing data 22 designated by the above code of several kinds of timing data stored in the microcomputer 70. The control data 25 are then supplied to the control circuit 10. The other operations are the same as those of the video camera system in the embodiment of Fig. 9.
In accordance with this embodiment, the system selection data has only to be supplied from the input terminal 76 to automatically place the video camera system in a normally operable state, thereby improving the working efficiency in the production process.
Referring to Figs. 10 A/B and 11, an explanation will be given of a further modified embodiment. The basic arrangement is substantially the same as the embodiment shown in Fig. 1. The digital signal processing circuit 3 is also substantially the same as that in Fig. 3 except the arrangement of the luminance signal processing unit 37 encircled by a dotted line. Fig. 10A shows a circuit for supplying the luminance signal and sync signals to the D/A converter unit 4. This luminance signal processing circuit is composed of a signal switch 371 and a clock switch 372. Fig. 11 shows the waveform of the luminance signal supplemented with sync signals. Since the basic operation of the video camera according to this embodiment is substantially the same as that shown in Fig. 1 except the D/A conversion operation, only the operation of the luminance signal processing unit 37 will be explained.
During the A - B interval in Fig. 11, the signal switch 371 connects a terminal 375 with a terminal 374 to supply the sync signals 20 to the D/A converter unit 4, and the clock switch 372 connects a terminal 377 with the n·fsc clock to the clock terminal 24 of the D/A converter unit 4. Then, in response to the n fsc clock, the D/A converter unit 4 converts the sync signals into an analog signal to be outputted as in Fig. 10A. At the time B in Fig. 11, the signal switch 371 is switched into a terminal 373 to supply the luminance signal 303 to the terminal 14 of D/A converter unit 4, and the clock switch 372 is switched into a terminal 376 to supply the sensor clock fs which is on line 18 and represents one of the control signals to the clock terminal 24 of the D/A converter unit 4. Then, in response to the sensor clock fs, the D/A converter unit 4 converts the luminance signal 303 into an analog luminance signal to be outputted. Such an operation is continued during the interval B - A' until a time A'. At the time A', the signal switch 371 and the clock switch 372 are switched into opposite terminals, respectively so that the same operation as during the above interval A - B is performed. Thereafter, the above operations will be repeated. It should be noted that in Fig. 11, the level of the luminance signal is fixed during all the intervals C, D, C' and D' where the switching timings A, B, A' and B' are located. In order to implement the switching operation in the above signal processing unit 37, the horizontal blanking signal HBLK as shown in Fig. 10B included in the sync signals 20 is supplied to the signal switch 371 and the clock switch 372 as a switching signal. Thus, as seen from Fig. 10B, at the falling edge of the HBLK, the terminals 375 and 378 are connected with the terminals 374 and 377, respectively whereas at the rising edge of HBLK, the terminals 375 and 378 are connected with the terminals 373 and 376, respectively.
In accordance with the embodiment of Figs. 10A and 10B, the luminance signal and the sync signals are D/A converted at the timing points at both ends of the horizontal blanking period where the level of the luminance signal is fixed. Therefore, even if the luminance signal is not in synchronism with the sync signals, jitter adversely affecting the resulting output is not generated.
In accordance with the embodiments explained in connection with Figs. 11 to 14, the sync signal generating circuit is composed of a unit for generating a horizontal sync signal and a vertical sync signal in response to the clock at a frequency n (dependent upon the color TV) times larger than the frequency fsc of the color subcarrier, and a unit for generating sync signals to be added to a luminance signal and color difference signals, and the luminance signal which is not yet supplemented with the sync signals is generated on the basis of the horizontal scanning clock of the sensor used. In such a construction, the luminance signal is made synchronous with the sync signals so that the jitter attendant on the digitization in the signal processing can be removed to achieve high image quality.
Furthermore, by providing a programmable sync signal generating circuit, a sensor driving timing generating circuit and a microcomputer or the like for controlling these circuits, the video camera can be equipped with a plurality of different kinds of sensors, thereby achieving versatility and low cost of the devices.
Further, there is provided a circuit for exchanging the D/A conversion of the luminance signal and the sync signals at the timings of both ends of the horizontal blanking period when the level of the luminance signal is fixed so that a jitterless image can be obtained.
All the embodiments hitherto explained can be effectively implemented in any general color TV system including PAL, SECAM, NTSC, etc.

Claims

A video camera comprising an image sensor (1) providing analog image signals (12) in accordance with a color television system standard, an A/D converter (2) for converting the analog image signals into corresponding digitized image signals represented by luminance and color difference signals (13), a signal processor (3) for digitally processing said digitized image signals, a D/A converter (4) for reconverting the processed digitized signals (14, 15) into analog output signals (16, 17), and synchronization signal clock generating means (5, 6) having:

a sensor driving timing generator TG (5) for generating a first clock (fs) pulse waveform (18) for synchronizing the scanning cycle of the image signal on the basis of a first predetermined clock (50) generated by a first clock generator (51), and

a synchronization signal generator SSG (6) generating a sync control signal (20) of a frequency being n times larger than the frequency of the color subcarrier (fsc) of said color television system standard to control said signal processor (3),

characterized in that said first clock (fs) pulse waveform (18) is supplied to the SSG (6) which includes:

a first SSG subunit (62) for generating horizontal (CHD) and vertical (VD) synchronization signals (19) on the basis of a second predetermined clock (60) at a frequency (n fsc) being n times larger than the frequency of said color subcarrier depending on the color television system used, and

a second SSG subunit (63 or 64) for generating the sync control signal (20: CSYNC, CBLK, BF) by synthesizing the vertical synchronization signal generated by said first SSG subunit (62) and a horizontal synchronization signal generated in response to said first clock (fs) pulse waveform (18) so that said sync control signal is in synchronism with said first clock (fs) pulse waveform (18), and that said timing generator TG (5) generates said first clock (fs) pulse waveform (18) in synchronism with said horizontal scanning cycle of the image sensor on the basis of said predetermined clock (fs) generated by said first clock generator (51) and in response to said horizontal (CHD) and vertical (VD) synchronization signals (19).
The video camera of claim 1, characterized in that said second SSG subunit (64) includes:

a counter (631) producing a counted value in response to said first clock (fs) pulse waveform (18),

data latching means (632) to store externally supplied data which determine a selected horizontal scanning frequency of the used TV system, and

a pulse generator (634) for generating a horizontal sync signal (638) by comparing the counted value from said counter (631) with the timing data stored in said latching means (632).
The video camera of claim 2, wherein the comparison of the counted value with the latched timing data is effected by generating rising and falling edge pulses and by combining said pulses, wherein the timing is such that the counted value and the timing data coincide.
The video camera of claim 2, characterized in that said second SSG subunit (64) further includes a sync signal synthesizer circuit (635) for synthesizing the vertical sync signal (VD) received from said first SSG subunit (62) and the horizontal sync signal (638) to produce said sync control signal (20: CSYNC, CBLK, BF).
The video camera of claim 2, wherein said data latching means (632) are composed of a plurality of rows of latches (632a,b) and said pulse generator (634) is composed of a plurality of logic elements (634a,b) connected in series which generate the corresponding horizontal sync signals having different clock rates, and a specified row of said latches (632) and pulse generator logic elements (634) is selected according to the image sensor specification to produce said horizontal sync signal (638).
The video camera of claim 1, wherein a programmable sensor driving timing generator PTG (9) is provided which makes the clock rate of said first clock (fs) variable in accordance with the image sensor specification, said PTG unit (9) adapted to receive program data (22) to control the timing of said first clock (fs).
The video camera of claim 1, characterized in that said SSG (66) is programmable for generating the said sync control signals (20: CSYNC, CBLK, BF) in synchronism with the horizontal scanning clock of said image sensor, said programmable SSG (66) being adapted for the rewriting of externally supplied data which determine a selected horizontal scanning frequency.
The video camera of claim 7, characterized by a ROM (73) for storing and providing timing data to a programmable SSG (66).
The video camera of claim 7, characterized by a ROM (73) for providing timing data to a microcomputer (7) which is connected to the programmable SSG (66) for temporarily holding timing data in said ROM which determine a selected horizontal scanning frequency.(Fig. 22).
The video camera of claim 7, further comprising a microcomputer (70) for storing preselected timing data for a plurality of different image sensors (1), said timing data adapted for supply to the programmable SSG (66), a programmable ROM (74) having stored codes and control data allotted to said different image sensors (1), and an input terminal (76) for inputting to said microcomputer (70) select data (78) for selecting said codes and control data (77) to be supplied from said programmable ROM (74) to said microcomputer (70).
The video camera of claim 1, wherein a luminance signal (303) and the sync control signals (20) are D/A converted in response to clock signals (24) at the timings at both ends of the horizontal blanking period (HBLK) where the level of the luminance signal is fixed, characterized by a first switching means (371) for selecting either said luminance signal (303) or said sync control signal (20) for supply to said D/A converter (4) when the luminance level is fixed at both ends of a horizontal blanking period, and a second switching means (372) for providing clock signals (24) to said D/A converter (4) by selecting synchronously with said first switch (371) either the first clock (fs) (18) or the clocking pulses (23) of a frequency being K times larger than the frequency of the color subcarrier (fsc) to supply the such selected signals as the clock signals (24) to the D/A converter (4).