EP0657811B1 - Integrated circuitry for checking the utilization rate of redundancy memory elements in a semiconductor memory device - Google Patents
Integrated circuitry for checking the utilization rate of redundancy memory elements in a semiconductor memory device Download PDFInfo
- Publication number
- EP0657811B1 EP0657811B1 EP93830493A EP93830493A EP0657811B1 EP 0657811 B1 EP0657811 B1 EP 0657811B1 EP 93830493 A EP93830493 A EP 93830493A EP 93830493 A EP93830493 A EP 93830493A EP 0657811 B1 EP0657811 B1 EP 0657811B1
- Authority
- EP
- European Patent Office
- Prior art keywords
- redundancy
- memory
- address
- signals
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000015654 memory Effects 0.000 title claims description 162
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 239000011159 matrix material Substances 0.000 claims description 36
- 230000002950 deficient Effects 0.000 claims description 22
- 230000005764 inhibitory process Effects 0.000 claims description 6
- 230000002401 inhibitory effect Effects 0.000 claims description 2
- 238000012360 testing method Methods 0.000 description 14
- 238000004519 manufacturing process Methods 0.000 description 7
- 230000004913 activation Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 230000007547 defect Effects 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000007619 statistical method Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
- G11C29/789—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes using non-volatile cells or latches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/835—Masking faults in memories by using spares or by reconfiguring using programmable devices with roll call arrangements for redundant substitutions
Landscapes
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Description
Claims (4)
- Integrated circuitry for checking the utilization rate of redundancy memory elements in a semiconductor memory device, comprising a matrix of memory elements and redundancy circuitry which comprises a plurality of programmable non-volatile memory registers (1), each of which is programmable to store an address of a defective memory element in the matrix which must be replaced by the redundancy memory element associated to the non-volatile register (1) and is supplied with address signals (A0-An) to generate a redundancy selection signal (RS) for the selection of the associated redundancy memory element when said address signals (A0-An) coincide with the address stored therein, combinatorial circuit means (3,9) supplied with said address signals (A0-An) and supplying the non-volatile memory registers (1) with an inhibition signal (DIS') for inhibiting the generation of the respective redundancy selection signals (RS) when said address signals (A0-An) coincide with the address stored in a non-programmed non-volatile memory register (1), characterized in that it comprises multiplexing circuit means (11), controlled by a control signal (CHKN) generated by a control circuitry (4) of the memory device, for transmitting said redundancy selection signals (RS) to output pads (17) of the memory device when said control signal (CHKN) is activated, said control signal (CHKN) being also supplied to said combinatorial circuit means (3,9) to prevent when activated the generation of said inhibition signal (DIS').
- Integrated circuitry according to claim 1, characterized in that when said control signal (CHKN) is disactivated said multiplexing circuit means (11) transmit to said output pads (17) signals (RDBUS) generated by a sensing circuitry (12) for reading the memory elements in the matrix.
- Integrated circuitry according to claim 1, said matrix of memory elements being divided in individually addressable matrix sectors, each sector being provided with respective redundancy memory elements associated to respective non-volatile memory registers (1) in the redundancy circuitry, characterized in that said integrated circuitry comprises sector selection circuit means (15) supplied with sector address signals ( An+1-Ak) and generating sector selection signals (SS) controlling switching means (16) supplied with all said redundancy selection signals (RS) and supplying said multiplexing circuit means (11) with a set of said selection signals (RS) which are generated by the non-volatile memory registers (1) associated to redundancy memory elements of the sector currently addressed.
- Integrated circuitry according to claim 1 or 2, characterized in that each programmable non-volatile memory register (1) comprises a number of programmable memory cells (MC0-MCn) equal to the number of said address signals (A0-An), each memory cell (MC0-MCn) being supplied with one address signal and generating an output signal (CMP0-CMPn) when the logical state of said address signal correspond to the logical state stored in the memory cell (MC0-MCn), each non-volatile memory register (1) further comprising selection circuit means (2) supplied with the output signals (CMP0-CMPn) of the memory cells (MC0-MCn) for generating said redundancy selection signal (RS), said selection circuit means (2) being also supplied with said inhibition signal (DIS') which prevent when activated the generation of said redundancy selection signal (RS).
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE69320824T DE69320824T2 (en) | 1993-12-09 | 1993-12-09 | Integrated circuit for monitoring the use of redundancy memory components in a semiconductor memory device |
EP93830493A EP0657811B1 (en) | 1993-12-09 | 1993-12-09 | Integrated circuitry for checking the utilization rate of redundancy memory elements in a semiconductor memory device |
US08/350,961 US5493531A (en) | 1993-12-09 | 1994-12-07 | Integrated circuitry for checking the utilization rate of redundancy memory elements in a semiconductor memory device |
JP6304900A JP2591922B2 (en) | 1993-12-09 | 1994-12-08 | Integrated circuit to check the usage of redundant memory elements |
US08/602,237 US5708601A (en) | 1993-12-09 | 1996-02-16 | Integrated circuitry for checking the utilization rate of redundancy memory elements in a semiconductor memory device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP93830493A EP0657811B1 (en) | 1993-12-09 | 1993-12-09 | Integrated circuitry for checking the utilization rate of redundancy memory elements in a semiconductor memory device |
Publications (2)
Publication Number | Publication Date |
---|---|
EP0657811A1 EP0657811A1 (en) | 1995-06-14 |
EP0657811B1 true EP0657811B1 (en) | 1998-09-02 |
Family
ID=8215273
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP93830493A Expired - Lifetime EP0657811B1 (en) | 1993-12-09 | 1993-12-09 | Integrated circuitry for checking the utilization rate of redundancy memory elements in a semiconductor memory device |
Country Status (4)
Country | Link |
---|---|
US (1) | US5493531A (en) |
EP (1) | EP0657811B1 (en) |
JP (1) | JP2591922B2 (en) |
DE (1) | DE69320824T2 (en) |
Families Citing this family (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5708601A (en) * | 1993-12-09 | 1998-01-13 | Sgs-Thomson Microelectronics S.R.L. | Integrated circuitry for checking the utilization rate of redundancy memory elements in a semiconductor memory device |
DE19507312C1 (en) * | 1995-03-02 | 1996-07-25 | Siemens Ag | Semiconductor memory, the memory cells of which are combined to form individually addressable units and method for operating such memories |
US5841712A (en) * | 1996-09-30 | 1998-11-24 | Advanced Micro Devices, Inc. | Dual comparator circuit and method for selecting between normal and redundant decode logic in a semiconductor memory device |
US20040023874A1 (en) * | 2002-03-15 | 2004-02-05 | Burgess Catherine E. | Therapeutic polypeptides, nucleic acids encoding same, and methods of use |
US6974684B2 (en) * | 2001-08-08 | 2005-12-13 | Curagen Corporation | Therapeutic polypeptides, nucleic acids encoding same, and methods of use |
US20040229779A1 (en) * | 1999-05-14 | 2004-11-18 | Ramesh Kekuda | Therapeutic polypeptides, nucleic acids encoding same, and methods of use |
US20040067490A1 (en) * | 2001-09-07 | 2004-04-08 | Mei Zhong | Therapeutic polypeptides, nucleic acids encoding same, and methods of use |
US6855806B1 (en) * | 1999-10-15 | 2005-02-15 | Curagen Corporation | Thymosin beta 10-like proteins and nucleic acids encoding same |
DE10012104C2 (en) * | 2000-03-13 | 2002-05-02 | Infineon Technologies Ag | Redundancy multiplexer for semiconductor memory device |
US20040005554A1 (en) * | 2000-05-08 | 2004-01-08 | Tayar Nabil El | Novel glycoproteins and methods of use thereof |
US20030219786A1 (en) * | 2000-08-11 | 2003-11-27 | Applied Research Systems Ars Holding N.V. | Novel glycoproteins and methods of use thereof |
US20040023259A1 (en) * | 2000-07-26 | 2004-02-05 | Luca Rastelli | Therapeutic polypeptides, nucleic acids encoding same, and methods of use |
UA83458C2 (en) | 2000-09-18 | 2008-07-25 | Байоджен Айдек Ма Інк. | The isolated polypeptide baff-r (the receptor of the factor of activation of b-cells of the family tnf) |
US20040043928A1 (en) * | 2001-08-02 | 2004-03-04 | Ramesh Kekuda | Therapeutic polypeptides, nucleic acids encoding same, and methods of use |
US20030017159A1 (en) * | 2001-05-02 | 2003-01-23 | Jerome Ritz | Immunogenic tumor antigens: nucleic acids and polypeptides encoding the same and methods of use thereof |
US20030087274A1 (en) * | 2001-07-05 | 2003-05-08 | Anderson David W. | Therapeutic polypeptides, nucleic acids encoding same, and methods of use |
US20040029790A1 (en) * | 2001-07-05 | 2004-02-12 | Meera Patturajan | Novel human proteins, polynucleotides encoding them and methods of using the same |
US20040030096A1 (en) * | 2001-08-02 | 2004-02-12 | Linda Gorman | Novel human proteins, polynucleotides encoding them and methods of using the same |
AU2002355562A1 (en) * | 2001-08-08 | 2003-02-24 | Curagen Corporation | System and method for identifying a genetic risk factor for a disease or pathology |
US20030199442A1 (en) * | 2001-10-09 | 2003-10-23 | Alsobrook John P. | Therapeutic polypeptides, nucleic acids encoding same, and methods of use |
US20040162236A1 (en) * | 2002-04-01 | 2004-08-19 | John Alsobrook | Therapeutic polypeptides, nucleic acids encoding same, and methods of use |
CN104480200B (en) | 2004-03-31 | 2017-12-29 | 综合医院公司 | Determine method of the cancer to EGF-R ELISA magnetic target therapy reactivity |
EP1874920A4 (en) | 2005-04-05 | 2009-11-04 | Cellpoint Diagnostics | Devices and methods for enrichment and alteration of circulating tumor cells and other particles |
JP5014125B2 (en) * | 2005-05-30 | 2012-08-29 | スパンション エルエルシー | Semiconductor device and program data redundancy method |
US7609562B2 (en) * | 2007-01-31 | 2009-10-27 | Intel Corporation | Configurable device ID in non-volatile memory |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0070823A1 (en) * | 1981-02-02 | 1983-02-09 | Mostek Corporation | Semiconductor memory redundant element identification circuit |
JPH03160695A (en) * | 1989-11-17 | 1991-07-10 | Nec Corp | Semiconductor memory |
US5343429A (en) * | 1991-12-06 | 1994-08-30 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device having redundant circuit and method of testing to see whether or not redundant circuit is used therein |
-
1993
- 1993-12-09 EP EP93830493A patent/EP0657811B1/en not_active Expired - Lifetime
- 1993-12-09 DE DE69320824T patent/DE69320824T2/en not_active Expired - Fee Related
-
1994
- 1994-12-07 US US08/350,961 patent/US5493531A/en not_active Expired - Lifetime
- 1994-12-08 JP JP6304900A patent/JP2591922B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPH07254296A (en) | 1995-10-03 |
US5493531A (en) | 1996-02-20 |
DE69320824D1 (en) | 1998-10-08 |
DE69320824T2 (en) | 1999-05-12 |
EP0657811A1 (en) | 1995-06-14 |
JP2591922B2 (en) | 1997-03-19 |
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