EP0509112A1 - Error amplifier - Google Patents

Error amplifier Download PDF

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Publication number
EP0509112A1
EP0509112A1 EP91106067A EP91106067A EP0509112A1 EP 0509112 A1 EP0509112 A1 EP 0509112A1 EP 91106067 A EP91106067 A EP 91106067A EP 91106067 A EP91106067 A EP 91106067A EP 0509112 A1 EP0509112 A1 EP 0509112A1
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EP
European Patent Office
Prior art keywords
mos transistor
output
stage
error amplifier
connection
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EP91106067A
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German (de)
French (fr)
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EP0509112B1 (en
Inventor
Rudolf Dr. Koch
Fritz Mistlberger
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Siemens AG
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Siemens AG
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Priority to EP91106067A priority Critical patent/EP0509112B1/en
Priority to DE59108506T priority patent/DE59108506D1/en
Priority to JP4119783A priority patent/JPH05136637A/en
Publication of EP0509112A1 publication Critical patent/EP0509112A1/en
Priority to US08/046,124 priority patent/US5337009A/en
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Publication of EP0509112B1 publication Critical patent/EP0509112B1/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier

Definitions

  • the invention relates to an error amplifier.
  • output buffer amplifiers are required for a large number of applications, for example for operating hearing capsules and loudspeakers in telephone terminals.
  • the requirements placed on an output buffer amplifier include: the ability to drive low-resistance loads with a partially high capacitive component, a large output signal swing up to the operating voltage, sufficient linearity without transfer distortion and a low quiescent current consumption.
  • Common output buffer amplifiers are designed as class AB power amplifiers in CMOS technology with two complementary MOS transistors coupled into them. The two MOS transistors are controlled by error amplifiers, each of which is coupled from the coupled drain connections of the two MOS transistors to an input of the error amplifier.
  • error amplifiers are, for example, from K.E. Brehmer and J.B.
  • the error amplifier presented by KE Brehmer and JB Wieser consists of a symmetrical input differential amplifier stage with two source-coupled MOS transistors that are connected to a supply potential via a current source.
  • the drain connections of the two MOS transistors are connected to the other supply potential via a current mirror circuit.
  • the output of the input differential amplifier stage is connected to the gate connection of a MOS output transistor located on the source side to the other supply potential, and to the source connection of a further MOS transistor located on the gate side to the one supply potential.
  • the drain connection of the MOS output transistor is direct and the drain connection of the further MOS transistor is connected to the gate connection of one of the two MOS transistors of the input differential stage with the interposition of a capacitor.
  • the potential at the drain connection of the MOS output transistor changes in the direction of the other supply potential
  • the potential at the coupled source connections of the two MOS transistors of the input differential stage shifts in the direction of the one supply potential, while the output of the input differential amplifier stage in the direction of the other supply potential wanders.
  • one of the two MOS transistors of the input differential amplifier stage is pressed into the start-up range even at medium modulation, and the modulation of the entire error amplifier is thus impeded.
  • the error amplifier therefore has only a low common-mode controllability.
  • the object of the invention is therefore to provide an error amplifier of the type mentioned above which does not have these disadvantages.
  • FIG. 1 shows an output buffer amplifier which has an output stage for small output powers and an output stage for large output powers, the outputs of which are connected to one another and form an output 20 of the output buffer amplifier, a control stage which is connected upstream of the output stage for small output powers, and one input of which is driven by a signal proportional to an output signal of the output stage for high output powers and the other input of which is driven by a signal proportional to an output signal of the output stage for small output lines.
  • the output stage for large output powers consists of a MOS transistor 9 of the p-channel type, the source connection of which is connected to a positive supply potential 18 and the drain connection of which is connected to the output 20, and a MOS transistor 10 of the n- Channel type, the source connection of which is connected to a negative supply potential 19 and the drain connection of which is connected to the output 20.
  • the gate connections of the two MOS transistors 9 and 10 are each connected to the output of an error amplifier 13 or 14, the non-inverting inputs of which are connected to one another and to the output 20.
  • the inverting inputs of the two error amplifiers 13 and 14 are connected to one another and to the inverting input of the control stage designed as a differential amplifier 12 with an offset voltage source 15 or 16 connected in series.
  • the output stage for small output powers consists of a MOS transistor 1 of the p-channel type, the source connection of which is supplied with the positive supply potential 18, and of a MOS transistor 4 of the n-channel type, the source connection of which the negative supply potential 19 is applied.
  • the drain-source path of the MOS transistor 4 is connected in parallel with the drain-source path of a MOS transistor 17 of the n-channel type, the gate connection of which is connected to the output of the differential amplifier 12.
  • the drain connections of the two MOS transistors 1 and 4 are connected to one another via a series connection of two diodes in the forward direction.
  • the two diodes are connected by a MOS transistor 2 of the n-channel type, in which the gate and drain connections are connected to one another and to the drain connection of the MOS transistor 1, and by a MOS transistor 3 of the p-channel type, in which the gate and drain connections are connected to one another and to the drain connection of the MOS transistor 4.
  • the source connections of the two MOS transistors 2 and 3 are coupled to one another and connected to the non-inverting input of the differential amplifier 12.
  • an MOS transistor 7 of the n-channel type the gate connection of which is connected to the drain connection of the MOS transistor 1 and the drain connection of which is connected to the positive supply potential 18
  • a MOS transistor 8 of the p- Channel type the gate connection of which is connected to the drain connection of the MOS transistor 4 and the drain connection of which is connected to the negative supply potential 19.
  • the source connections of the two MOS transistors 7 and 8 are coupled to one another and form the output of the output stage for low output powers. They are therefore also connected to output 20.
  • a MOS transistor 5 of the p-channel type is connected via its drain connection to the inverting input of the differential amplifier 12 and via its source connection to the positive supply potential 18.
  • a MOS transistor 6 of the n-channel type is connected to the negative supply potential 19 via its source connection and to the inverting input of the differential amplifier 12 via its drain connection.
  • the gate terminal of the MOS transistor 5 is connected to the gate terminal of the MOS transistor 1 and the gate terminal of the MOS transistor 6 is connected to the gate terminal of the MOS transistor 4, forming the inputs of the output buffer amplifier, coupled.
  • an input amplifier 11 is connected upstream of the output buffer amplifier, which has two differential inputs 21 and 22 and two differential outputs which are connected to the gate connections of the MOS transistors 1, 5 and 4, 6, respectively.
  • the error amplifier 14 according to FIG. 1 is shown in detail in FIG. 2 of the drawing.
  • This has a differential amplifier stage with two source-coupled MOS transistors 23 and 24 of the n-channel type and a current source.
  • the current source consists of a MOS transistor 25 of the n-channel type, the drain connection of which is connected to the coupled source connections of the MOS transistors 23 and 24 and the source connection of which is connected to the negative supply potential 19.
  • a bias potential 31 is applied to the gate connection of the MOS transistor 25.
  • the drain connection of the MOS transistor 24, which represents the output of the differential amplifier stage, is coupled to the gate connection of a MOS transistor 28 of the p-channel type, whose source connection is connected directly to the positive supply potential 18 and whose drain Connection connected with the interposition of a diode in the forward direction to the negative supply potential 19.
  • the diode is preferably formed by an MOS transistor 29 of the n-channel type, in which the drain and gate connections are connected to one another.
  • the MOS transistor 10 is connected to the mutually coupled gate and drain connections of the MOS transistor 29 and to the drain connection of the MOS transistor 28, which form the output of the error amplifier 14.
  • a level shifter stage is connected upstream of at least one input of the differential amplifier stage.
  • the gate connection of the MOS transistor 24 connected on the one hand via a current source 30 to the positive supply potential 18 and on the other hand via the source-drain path of a MOS transistor 27 of the p-channel type to the negative supply potential 19.
  • the gate connection of the MOS transistor 23 is preceded by a further, identically constructed level shift stage, consisting of a current source 34 and a MOS transistor 33 of the p-channel type.
  • the gate of MOS transistor 27 is the non-inverting input of error amplifier 14, while the gate of MOS transistor 33 is its inverting input. According to FIG. 1, the non-inverting input of the control amplifier 14 is connected to the output 20.
  • the error amplifier 13 also shown in FIG. 1, which will not be described in more detail below, is constructed complementarily to the control amplifier 14 shown.
  • the differential amplifier stage is also designed asymmetrically. This is achieved in that the drain connection of the MOS transistor 23 is connected directly and the drain connection of the MOS transistor 24 is connected to the positive supply potential 18 via the drain-source path of a MOS transistor 26 of the p-channel type is. A bias potential 32 is applied to the gate connection of the MOS transistor 32.
  • the potential at the output of the differential amplifier stage onto the gate connection of the MOS transistor 10 by reflecting the potential at the output of the differential amplifier stage onto the gate connection of the MOS transistor 10, the potential at the output 20 and the potential at the output of the differential amplifier stage, that is to say at the drain connection of the MOS transistor 10, is achieved.
  • Transistor 24, are in common mode. This is achieved by means of the two MOS transistors 28 and 29, the MOS transistor 29 connected as a diode and the MOS transistor 10 forming a current mirror which is controlled by the voltage at the output of the differential amplifier stage by means of the MOS transistor 28.
  • a level shifter is used for the negative feedback, so with negative Control of the differential amplifier stage of the current source transistor, namely the MOS transistor 25, remains in saturation.
  • the asymmetrical structure of the differential stage prevents the potential at the output of the differential amplifier stage from remaining approximately the same as the positive supply potential 18 and not toppling over in the direction of the negative supply potential 19 when there is positive modulation.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Abstract

An error amplifier having a differential amplifier stage (23, 24, 25) which exhibits two inputs and one output, having an MOS transistor (28), the gate terminal of which is connected to the output of the differential amplifier stage (23, 24, 25), and the source terminal of which is connected to a first supply potential (18), having a diode (29) which is connected in the forward direction between the drain terminal of the MOS transistor (28), intended as output of the error amplifier, and a second supply potential (19). <IMAGE>

Description

Die Erfindung betrifft einen Fehlerverstärker.The invention relates to an error amplifier.

Bei der analogen Signalverarbeitung werden für eine Vielzahl von Anwendungen Ausgangspufferverstärker benötigt, wie beispielsweise zum Betreiben von Hörkapseln und Lautsprechern bei Telefonendgeräten. Die Anforderungen, die dabei an einen Ausgangspufferverstärker gestellt werden, sind u.a. die Fähigkeit niederohmige Lasten mit teilweise hohem kapazitiven Anteil zu treiben, ein großer Ausgangssignalhub bis knapp an die Betriebsspannung, eine ausreichende Linearität ohne Übernahmeverzerrungen und eine geringe Ruhestromaufnahme. Gebräuchliche Ausgangspufferverstärker sind als Endstufen der Klasse AB in CMOS-Technik mit zwei draingekoppelten komplementären MOS-Transistoren ausgeübt. Die beiden MOS-Transistoren werden von Fehlerverstärkern angesteuert, die jeweils von den gekoppelten Drain- Anschlüssen der beiden MOS-Transistoren auf einen Eingang des Fehlerverstärkers gegengekoppelt sind. Derartige Fehlerverstärker sind beispielsweise aus K.E. Brehmer und J.B. Wieser, "Large swing CMOS power amplifier", IEEE J. Solid-State Circuits, Vol. SC-18, S. 624-629, Dezember 1983; B.K. Ahuja, P.R. Gray, W.M. Baxter und G.T. Uehara, "A programmable CMOS dual channel interface processor for telecommunications applications", IEEE J. Solid-State Circuits, Vol. SC-19, S. 892-899, Dezember 1984 sowie J.A. Fisher, "A high-performance CMOS power amplifier", IEEE J. Solid State Circuits, Vol. SC-20, S. 1200-1205, Dezember 1985 bekannt.In the case of analog signal processing, output buffer amplifiers are required for a large number of applications, for example for operating hearing capsules and loudspeakers in telephone terminals. The requirements placed on an output buffer amplifier include: the ability to drive low-resistance loads with a partially high capacitive component, a large output signal swing up to the operating voltage, sufficient linearity without transfer distortion and a low quiescent current consumption. Common output buffer amplifiers are designed as class AB power amplifiers in CMOS technology with two complementary MOS transistors coupled into them. The two MOS transistors are controlled by error amplifiers, each of which is coupled from the coupled drain connections of the two MOS transistors to an input of the error amplifier. Such error amplifiers are, for example, from K.E. Brehmer and J.B. Wieser, "Large swing CMOS power amplifier", IEEE J. Solid-State Circuits, Vol. SC-18, pp. 624-629, December 1983; B.K. Ahuja, P.R. Gray, W.M. Baxter and G.T. Uehara, "A programmable CMOS dual channel interface processor for telecommunications applications", IEEE J. Solid-State Circuits, Vol. SC-19, pp. 892-899, December 1984 and J.A. Fisher, "A high-performance CMOS power amplifier", IEEE J. Solid State Circuits, Vol. SC-20, pp. 1200-1205, December 1985.

Der von K.E. Brehmer und J.B. Wieser vorgestellte Fehlerverstärker besteht aus einer symmetrisch aufgebauten Eingangsdifferenzverstärkerstufe mit zwei sourcegekoppelten MOS-Transistoren, die über eine Stromquelle mit einem Versorgungspotential verbunden sind. Die Drainanschlüsse der beiden MOS-Transistoren sind über eine Stromspiegelschaltung an dem anderen Versorgungspotential angeschlossen. Der Ausgang der Eingangsdifferenzverstärkerstufe ist auf den Gateanschluß eines sourceseitig an den anderen Versorgungspotential liegenden MOS-Ausgangstransistor, sowie auf den Source-Anschluß eines gateseitig an dem einen Versorgungspotential liegenden weiteren MOS-Transistors geführt. Der Drainanschluß des MOS-Ausgangstransistors ist direkt und der Drainanschluß des weiteren MOS-Transistors ist unter Zwischenschaltung eines Kondensators mit dem Gateanschluß eines der beiden MOS-Transistoren der Eingangsdifferenzstufe verbunden. Ändert sich das Potential am Drainanschluß des MOS-Ausgangstransistors in Richtung des anderen Versorgungspotentials, so verschiebt sich das Potential an den gekoppelten Source-Anschlüssen der beiden MOS-Transistoren der Eingangsdifferenzstufe in Richtung des einen Versorgungspotentials, während der Ausgang der Eingangsdifferenzverstärkerstufe in Richtung des anderen Versorgungspotentials wandert. Dadurch wird einer der beiden MOS-Transistoren der Eingangsdifferenzverstärkerstufe schon bei mittlerer Aussteuerung in den Anlaufbereich gedrückt und es wird damit die Aussteuerung des gesamten Fehlerverstärkers behindert. Der Fehlerverstärker besitzt daher nur eine geringe Gleichtaktaussteuerbarkeit.The error amplifier presented by KE Brehmer and JB Wieser consists of a symmetrical input differential amplifier stage with two source-coupled MOS transistors that are connected to a supply potential via a current source. The drain connections of the two MOS transistors are connected to the other supply potential via a current mirror circuit. The output of the input differential amplifier stage is connected to the gate connection of a MOS output transistor located on the source side to the other supply potential, and to the source connection of a further MOS transistor located on the gate side to the one supply potential. The drain connection of the MOS output transistor is direct and the drain connection of the further MOS transistor is connected to the gate connection of one of the two MOS transistors of the input differential stage with the interposition of a capacitor. If the potential at the drain connection of the MOS output transistor changes in the direction of the other supply potential, the potential at the coupled source connections of the two MOS transistors of the input differential stage shifts in the direction of the one supply potential, while the output of the input differential amplifier stage in the direction of the other supply potential wanders. As a result, one of the two MOS transistors of the input differential amplifier stage is pressed into the start-up range even at medium modulation, and the modulation of the entire error amplifier is thus impeded. The error amplifier therefore has only a low common-mode controllability.

Aufgabe der Erfindung ist es daher, einen Fehlerverstärker der vorstehend genannten Art anzugeben, der diese Nachteile nicht aufweist.The object of the invention is therefore to provide an error amplifier of the type mentioned above which does not have these disadvantages.

Die Aufgabe wird durch einen Fehlerverstärker gemäß Patentanspruch 1 gelöst. Ausgestaltungen und Weiterbildungen des Erfindungsgedankens sind Gegenstand von Unteransprüchen.The object is achieved by an error amplifier according to claim 1. Refinements and developments of the inventive concept are the subject of dependent claims.

Die Erfindung wird nachfolgend anhand des in den Figuren der Zeichnung dargestellten Ausführungsbeispiels näher erläutert, wobei gleiche Elemente mit gleichen Bezugszeichen versehen sind.The invention is explained in more detail below on the basis of the exemplary embodiment shown in the figures of the drawing, the same elements being provided with the same reference numerals.

Es zeigt:

Figur 1
ein Anwendungsbeispiel für einen erfindungsgemäßen Fehlerverstärker und
Figur 2
ein Ausführungsbeispiel eines erfindungsgemäßen Fehlerverstärkers.
It shows:
Figure 1
an application example for an error amplifier according to the invention and
Figure 2
an embodiment of an error amplifier according to the invention.

Als Anwendungsbeispiel für einen erfindungsgemäßen Fehlerverstärker zeigt Figur 1 einen Ausgangspufferverstärker, der eine Endstufe für kleine Ausgangsleistungen und eine Endstufe für große Ausgangsleistungen, deren Ausgänge miteinander verbunden sind und einen Ausgang 20 des Ausgangspufferverstärkers bilden, eine Regelstufe, die der Endstufe für kleine Ausgangsleistungen vorgeschaltet ist, und deren einer Eingang durch einem Eingangssignal der Endstufe für große Ausgangsleistungen proportionales Signal und deren anderer Eingang durch ein einem Ausgangssignal der Endstufe für kleine Ausgangslesitungen proportionales Signal angesteuert wird. Die Endstufe für große Ausgangsleistungen besteht aus einem MOS-Transistor 9 vom p-Kanal-Typ, dessen Source- Anschluß mit einem positiven Versorgungspotential 18 und dessen Drain-Anschluß mit dem Ausgang 20 verbunden ist, und aus einem MOS-Transistor 10 vom n-Kanal-Typ, dessen Source-Anschluß mit einem negativen Versorgungspotential 19 und dessen Drain-Anschluß mit dem Ausgang 20 verbunden ist. Die Gate-Anschlüsse der beiden MOS-Transistoren 9 und 10 sind an den Ausgang jeweils eines Fehlerverstärkers 13 bzw. 14 angeschlossen, deren nichtinvertierende Eingänge miteinander und mit dem Ausgang 20 verschaltet sind. Die invertierenden Eingänge der beiden Fehlerverstärker 13 und 14 sind unter Vorschalten jeweils einer Offset-Spannungsquelle 15 bzw. 16 miteinander sowie mit dem invertierenden Eingang der als Differenzverstärker 12 ausgeführten Regelstufe verbunden.As an application example for an error amplifier according to the invention, FIG. 1 shows an output buffer amplifier which has an output stage for small output powers and an output stage for large output powers, the outputs of which are connected to one another and form an output 20 of the output buffer amplifier, a control stage which is connected upstream of the output stage for small output powers, and one input of which is driven by a signal proportional to an output signal of the output stage for high output powers and the other input of which is driven by a signal proportional to an output signal of the output stage for small output lines. The output stage for large output powers consists of a MOS transistor 9 of the p-channel type, the source connection of which is connected to a positive supply potential 18 and the drain connection of which is connected to the output 20, and a MOS transistor 10 of the n- Channel type, the source connection of which is connected to a negative supply potential 19 and the drain connection of which is connected to the output 20. The gate connections of the two MOS transistors 9 and 10 are each connected to the output of an error amplifier 13 or 14, the non-inverting inputs of which are connected to one another and to the output 20. The inverting inputs of the two error amplifiers 13 and 14 are connected to one another and to the inverting input of the control stage designed as a differential amplifier 12 with an offset voltage source 15 or 16 connected in series.

Die Endstufe für kleine Ausgangsleistungen besteht aus einem MOS-Transistor 1 vom p-Kanal-Typ, dessen Source-Anschluß mit dem positiven Versorgungspotential 18 beaufschlagt ist, und aus einem MOS-Transistor 4 vom n-Kanal-Typ, dessen Source-Anschluß mit dem negativen Versorgungspotential 19 beaufschlagt ist.The output stage for small output powers consists of a MOS transistor 1 of the p-channel type, the source connection of which is supplied with the positive supply potential 18, and of a MOS transistor 4 of the n-channel type, the source connection of which the negative supply potential 19 is applied.

Die Drain-Source-Strecke des MOS-Transistors 4 ist die Drain-Source-Strecke eines MOS-Transistors 17 vom n-Kanal-Typ parallelgeschaltet, dessen Gate-Anschluß mit dem Ausgang des Differenzverstärkers 12 verbunden ist. Die Drain-Anschlüsse der beiden MOS-Transistoren 1 und 4 sind über eine Reihenschaltung von zwei Dioden in Durchlaßrichtung miteinander verbunden. Die beiden Dioden sind im gezeigten Ausführungsbeispiel durch einen MOS-Transistor 2 vom n-Kanal-Typ, bei dem Gate- und Drain-Anschluß miteinander sowie mit dem Drain-Anschluß des MOS-Transistors 1 verbunden sind, und durch einen MOS-Transistor 3 vom p-Kanal-Typ, bei dem Gate- und Drain-Anschluß miteinander sowie mit dem Drain-Anschluß des MOS-Transistors 4 verbunden sind, gegeben. Die Source-Anschlüsse der beiden MOS-Transistoren 2 und 3 sind miteinander gekoppelt und an den nichtinvertierenden Eingang des Differenzverstärkers 12 angeschlossen. Außerdem sind ein MOS-Transistor 7 vom n-Kanal-Typ, dessen Gate-Anschluß mit dem Drain-Anschluß des MOS-Transistors 1 und dessen Drain-Anschluß mit dem positiven Versorgungspotential 18 verbunden ist, und ein MOS-Transistor 8 vom p-Kanal-Typ, dessen Gate-Anschluß mit dem Drain-Anschluß des MOS-Transistors 4 und dessen Drain-Anschluß mit dem negativen Versorgungspotential 19 verbunden ist, vorgesehen. Die Source-Anschlüsse der beiden MOS-Transistoren 7 und 8 sind miteinander gekoppelt und bilden den Ausgang der Endstufe für kleine Ausgangsleistungen. Sie sind daher zudem an den Ausgang 20 angeschlossen.The drain-source path of the MOS transistor 4 is connected in parallel with the drain-source path of a MOS transistor 17 of the n-channel type, the gate connection of which is connected to the output of the differential amplifier 12. The drain connections of the two MOS transistors 1 and 4 are connected to one another via a series connection of two diodes in the forward direction. In the exemplary embodiment shown, the two diodes are connected by a MOS transistor 2 of the n-channel type, in which the gate and drain connections are connected to one another and to the drain connection of the MOS transistor 1, and by a MOS transistor 3 of the p-channel type, in which the gate and drain connections are connected to one another and to the drain connection of the MOS transistor 4. The source connections of the two MOS transistors 2 and 3 are coupled to one another and connected to the non-inverting input of the differential amplifier 12. In addition, an MOS transistor 7 of the n-channel type, the gate connection of which is connected to the drain connection of the MOS transistor 1 and the drain connection of which is connected to the positive supply potential 18, and a MOS transistor 8 of the p- Channel type, the gate connection of which is connected to the drain connection of the MOS transistor 4 and the drain connection of which is connected to the negative supply potential 19. The source connections of the two MOS transistors 7 and 8 are coupled to one another and form the output of the output stage for low output powers. They are therefore also connected to output 20.

Weiterhin ist ein MOS-Transistor 5 vom p-Kanal-Typ über seinen Drain-Anschluß mit dem invertierenden Eingang des Differenzverstärkers 12 und über seinen Source-Anschluß mit dem positiven Versorgungspotential 18 verbunden. Außerdem ist ein MOS-Transistor 6 vom n-Kanal-Typ über seinen Source-Anschluß mit dem negativen Versorgungspotential 19 und über seinen Drain-Anschluß mit dem invertierenden Eingang des Differenzverstärkers 12 verschaltet. Der Gate-Anschluß des MOS-Transistors 5 ist mit dem Gate-Anschluß des MOS-Transistors 1 und der Gate-Anschluß des MOS-Transistors 6 mit dem Gate-Anschluß des MOS-Transistors 4, die Eingänge des Ausgangspufferverstärkers bildend, gekoppelt.Furthermore, a MOS transistor 5 of the p-channel type is connected via its drain connection to the inverting input of the differential amplifier 12 and via its source connection to the positive supply potential 18. In addition, a MOS transistor 6 of the n-channel type is connected to the negative supply potential 19 via its source connection and to the inverting input of the differential amplifier 12 via its drain connection. The gate terminal of the MOS transistor 5 is connected to the gate terminal of the MOS transistor 1 and the gate terminal of the MOS transistor 6 is connected to the gate terminal of the MOS transistor 4, forming the inputs of the output buffer amplifier, coupled.

Schließlich ist ein Eingangsverstärker 11 dem Ausgangspufferverstärker vorgeschaltet, der zum zwei Differenzeingänge 21 und 22 und zwei Differenzausgänge, die mit den Gate-Anschlüssen der MOS-Transistoren 1, 5 bzw. 4, 6 verbunden sind, aufweist.Finally, an input amplifier 11 is connected upstream of the output buffer amplifier, which has two differential inputs 21 and 22 and two differential outputs which are connected to the gate connections of the MOS transistors 1, 5 and 4, 6, respectively.

In Figur 2 der Zeichnung ist der Fehlerverstärker 14 nach Figur 1 detailiert dargestellt. Dieser weist eine Differenzverstärkerstufe mit zwei sourcegekoppelten MOS-Transistoren 23 und 24 vom n-Kanal-Typ sowie eine Stromquelle auf. Die Stromquelle besteht dabei aus einem MOS-Transistor 25 vom n-Kanal-Typ, dessen Drain- Anschluß mit den gekoppelten Source-Anschlüssen der MOS-Transistoren 23 und 24 und dessen Source-Anschluß mit dem negativen Versorgungspotential 19 verbunden ist. An den Gate-Anschluß des MOS-Transistors 25 ist ein Biaspotential 31 gelegt.The error amplifier 14 according to FIG. 1 is shown in detail in FIG. 2 of the drawing. This has a differential amplifier stage with two source-coupled MOS transistors 23 and 24 of the n-channel type and a current source. The current source consists of a MOS transistor 25 of the n-channel type, the drain connection of which is connected to the coupled source connections of the MOS transistors 23 and 24 and the source connection of which is connected to the negative supply potential 19. A bias potential 31 is applied to the gate connection of the MOS transistor 25.

Der Drain-Anschluß des MOS-Transistors 24, der den Ausgang der Differenzverstärkerstufe darstellt, ist mit dem Gate-Anschluß eines MOS-Transistors 28 vom p-Kanal-Typ gekoppelt, dessen Source-Anschluß an das positive Versorgungspotential 18 direkt und dessen Drain-Anschluß unter Zwischenschaltung einer Diode in Durchlaßrichtung an das negative Versorgungspotential 19 angeschlossen. Die Diode wird dabei bevorzugt durch einen MOS-Transistor 29 vom n-Kanal-Typ, bei dem Drain- und Gate-Anschluß miteinander verbunden sind, gebildet. An die miteinander gekoppelten Gateund Drain-Anschlüsse des MOS-Transistors 29 sowie an den DrainAnschlußes des MOS-Transistors 28, die den Ausgang des Fehlerverstärkers 14 bilden, ist gemäß Figur 1 der MOS-Transistor 10 angeschlossen.The drain connection of the MOS transistor 24, which represents the output of the differential amplifier stage, is coupled to the gate connection of a MOS transistor 28 of the p-channel type, whose source connection is connected directly to the positive supply potential 18 and whose drain Connection connected with the interposition of a diode in the forward direction to the negative supply potential 19. The diode is preferably formed by an MOS transistor 29 of the n-channel type, in which the drain and gate connections are connected to one another. According to FIG. 1, the MOS transistor 10 is connected to the mutually coupled gate and drain connections of the MOS transistor 29 and to the drain connection of the MOS transistor 28, which form the output of the error amplifier 14.

In Weiterbildung der Erfindung ist mindestens einem Eingang der Differenzverstärkerstufe eine Pegelschieberstufe vorgeschaltet. Dazu ist der Gate-Anschluß des MOS-Transistors 24 zum einen über eine Stromquelle 30 mit dem positiven Versorgungspotential 18 und zum anderen über die Source-Drain-Strecke eines MOS-Transistors 27 vom p-Kanal-Typ mit dem negativen Versorgungspotential 19 verbunden. Zudem ist beim gezeigten Ausführungsbeispiel dem Gate-Anschluß des MOS-Transistors 23 eine weitere, identisch aufgebaute Pegelschieberstufe, bestehend aus einer Stromquelle 34 und einem MOS-Transistor 33 vom p-Kanal-Typ, vorgeschaltet. Der Gate-Anschluß des MOS-Transistors 27 stellt den nichtinvertierenden Eingang des Fehlerverstärkers 14 dar, während der Gate-Anschluß des MOS-Transistors 33 seinen invertierenden Eingang bildet. Gemäß Figur 1 ist der nichtinvertierende Eingang des Regelverstärkers 14 mit dem Ausgang 20 verbunden. Der in Figur 1 ebenfalls gezeigte Fehlerverstärker 13, der im weiteren nicht näher dargelegt wird, ist komplementär zu dem gezeigten Regelverstärker 14 aufgebaut.In a development of the invention, a level shifter stage is connected upstream of at least one input of the differential amplifier stage. For this purpose, the gate connection of the MOS transistor 24 connected on the one hand via a current source 30 to the positive supply potential 18 and on the other hand via the source-drain path of a MOS transistor 27 of the p-channel type to the negative supply potential 19. In addition, in the exemplary embodiment shown, the gate connection of the MOS transistor 23 is preceded by a further, identically constructed level shift stage, consisting of a current source 34 and a MOS transistor 33 of the p-channel type. The gate of MOS transistor 27 is the non-inverting input of error amplifier 14, while the gate of MOS transistor 33 is its inverting input. According to FIG. 1, the non-inverting input of the control amplifier 14 is connected to the output 20. The error amplifier 13 also shown in FIG. 1, which will not be described in more detail below, is constructed complementarily to the control amplifier 14 shown.

Die Erfindung weiterbildend ist die Differenzverstärkerstufe zudem unsymmetrisch ausgeführt. Dies wird dadurch erreicht, daß der Drain-Anschluß des MOS-Transistors 23 direkt und der Drain-Anschluß des MOS-Transistors 24 über die Drain-Source-Strecke eines MOS-Transistors 26 vom p-Kanal-Typ mit dem positiven Versorgungspotential 18 verbunden ist. An den Gate-Anschluß des MOS-Transistors 32 ist ein Biaspotential 32 gelegt.Further developing the invention, the differential amplifier stage is also designed asymmetrically. This is achieved in that the drain connection of the MOS transistor 23 is connected directly and the drain connection of the MOS transistor 24 is connected to the positive supply potential 18 via the drain-source path of a MOS transistor 26 of the p-channel type is. A bias potential 32 is applied to the gate connection of the MOS transistor 32.

Bei dem in Figur 2 gezeigten erfindungsgemäßen Fehlerverstärker wird durch eine Umspiegelung des Potentials am Ausgang der Differenzverstärkerstufe auf den Gate-Anschluß des MOS-Transistors 10 erreicht, daß das Potential am Ausgang 20 und das Potential am Ausgang der Differenzverstärkerstufe, also am Drainanschluß des MOS-Transistors 24, in Gleichtakt sind. Dies wird mittels der beiden MOS-Transistoren 28 und 29 erreicht, wobei der als Diode geschaltete MOS-Transistor 29 und der MOS-Transistor 10 einen Stromspiegel bilden, der mittels des MOS-Transistors 28 von der Spannung am Ausgang der Differenzverstärkerstufe gesteuert wird. Zusätzlich wird bei der Gegenkopplung eine Pegelschieberstufe eingesetzt, damit bei negativer Aussteuerung der Differenzverstärkerstufe der Stromquellentransistor, nämlich der MOS-Transistor 25, in Sättigung bleibt. Schließlich wird durch den unsymmetrischen Aufbau der Differenzstufe verhindert, daß bei positiver Aussteuerung das Potential am Ausgang der Differenzverstärkerstufe annähernd gleich dem positiven Versorgungspotential 18 bleibt und nicht in Richtung des negativen Versorgungspotentials 19 umkippt. Mit diesen Maßnahmen wird eine viel höhere Aussteuerbarkeit des Fehlerverstärkers erreicht und damit eine optimale Ansteuerung der Ausgangstransistoren, d.h. der MOS-Transistoren 9 und 10, erzielt.In the inventive error amplifier shown in FIG. 2, by reflecting the potential at the output of the differential amplifier stage onto the gate connection of the MOS transistor 10, the potential at the output 20 and the potential at the output of the differential amplifier stage, that is to say at the drain connection of the MOS transistor 10, is achieved. Transistor 24, are in common mode. This is achieved by means of the two MOS transistors 28 and 29, the MOS transistor 29 connected as a diode and the MOS transistor 10 forming a current mirror which is controlled by the voltage at the output of the differential amplifier stage by means of the MOS transistor 28. In addition, a level shifter is used for the negative feedback, so with negative Control of the differential amplifier stage of the current source transistor, namely the MOS transistor 25, remains in saturation. Finally, the asymmetrical structure of the differential stage prevents the potential at the output of the differential amplifier stage from remaining approximately the same as the positive supply potential 18 and not toppling over in the direction of the negative supply potential 19 when there is positive modulation. With these measures, a much higher controllability of the error amplifier is achieved and thus an optimal control of the output transistors, ie the MOS transistors 9 and 10, is achieved.

Claims (5)

Fehlerverstärker
mit einer Differenzverstärkerstufe (23, 24, 25), die zwei Eingänge und einen Ausgang aufweist,
mit einem MOS-Transistor (28), dessen Gate-Anschluß an den Ausgang der Differenzverstärkerstufe (23, 24, 25) und dessen Source-Anschluß an ein erstes Versorgungspotential (18) angeschlossen ist,
mit einer Diode (29), die in Durchlaßrichtung zwischen den als Ausgang des Fehlerverstärkers vorgesehen Drain-Anschluß des MOS-Transistors (28) und ein zweites Versorgungspotential (19) geschaltet ist.Error amplifier
with a differential amplifier stage (23, 24, 25) which has two inputs and one output,
with a MOS transistor (28), the gate connection of which is connected to the output of the differential amplifier stage (23, 24, 25) and the source connection of which is connected to a first supply potential (18),
with a diode (29) which is connected in the forward direction between the drain connection of the MOS transistor (28) provided as the output of the error amplifier and a second supply potential (19). Fehlerverstärker nach Anspruch 1,
dadurch gekennzeichnet, daß einem Eingang der Differenzverstärkerstufe mindestens eine Pegelschieberstufe (27, 30; 33, 34) vorgeschaltet ist.Error amplifier according to claim 1,
characterized in that at least one level shift stage (27, 30; 33, 34) is connected upstream of an input of the differential amplifier stage. Fehlerverstärker nach Anspruch 1 oder 2,
dadurch gekennzeichnet, daß die Differenzverstärkerstufe (23 bis 26) unsymmetrisch ausgebildet ist.Error amplifier according to claim 1 or 2,
characterized in that the differential amplifier stage (23 to 26) is asymmetrical. Fehlerverstärker nach Anspruch 2,
dadurch gekennzeichnet, daß die Pegelschieberstufe jeweils aus einem als Sourcefolger geschalteten MOS-Transistor (27, 33) bestehen.Error amplifier according to claim 2,
characterized in that the level shift stage each consist of a MOS transistor (27, 33) connected as a source follower. Fehlerverstärker nach Anspruch 3,
dadurch gekennzeichnet, daß die Unsymmetrie der Differenzvestärkerstufe (23 bis 26) durch einen mit seinem Gate-Anschluß auf einem Biaspotential (32) liegenden MOS-Transistor (26) im Ausgangskreis der Differenzverstärkerstufe (23 bis 26) erzeugt wird.Error amplifier according to claim 3,
characterized in that the asymmetry of the differential amplifier stage (23 to 26) is generated by a MOS transistor (26) with its gate connection at a bias potential (32) in the output circuit of the differential amplifier stage (23 to 26).
EP91106067A 1991-04-16 1991-04-16 Output buffer amplifier Expired - Lifetime EP0509112B1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP91106067A EP0509112B1 (en) 1991-04-16 1991-04-16 Output buffer amplifier
DE59108506T DE59108506D1 (en) 1991-04-16 1991-04-16 Output buffer amplifier
JP4119783A JPH05136637A (en) 1991-04-16 1992-04-13 Error amplifier
US08/046,124 US5337009A (en) 1991-04-16 1993-04-12 Error amplifier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP91106067A EP0509112B1 (en) 1991-04-16 1991-04-16 Output buffer amplifier

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EP0509112A1 true EP0509112A1 (en) 1992-10-21
EP0509112B1 EP0509112B1 (en) 1997-01-22

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Cited By (2)

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US7776523B2 (en) 2000-12-07 2010-08-17 Novartis Vaccines And Diagnostics, Inc. Endogenous retroviruses up-regulated in prostate cancer
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JPH05136637A (en) 1993-06-01
DE59108506D1 (en) 1997-03-06
US5337009A (en) 1994-08-09
EP0509112B1 (en) 1997-01-22

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