EP0405594B1

EP0405594B1 - Electronic cash register system

Info

Publication number: EP0405594B1
Application number: EP19900112485
Authority: EP
Inventors: Seiji Itoh; Masayuki Sumimoto
Original assignee: Sharp Corp
Current assignee: Sharp Corp
Priority date: 1989-06-30
Filing date: 1990-06-29
Publication date: 1995-02-01
Anticipated expiration: 2010-06-29
Also published as: JPH0335397A; DE69016512D1; DE69016512T2; EP0405594A3; EP0405594A2; JPH0823911B2

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an electronic cash register system having a plurality of cash registers which operate in systematic fashion.

2. Description of the Related Art

An electronic cash register system having a plurality of electronic cash registers includes a parent electronic cash register, which is provided with a memory serving as a master file, a child electronic cash register, and a line, which communicates the parent cash register and the child cash register with each other in such a manner as to allow mutual communication therebetween. This arrangement is often referred to as an in-line system.
The foregoing system typically operates based on the following steps.

(a) The child cash register sends a request message about transaction data to the parent cash register through the line when a user performs the operation of registering the transaction data, that is, the look-up operation at the child cash register.
(b) In response to the request message sent at the step (a), the parent cash register draws the corresponding transaction data from the master file and transfers the transaction data to the child cash register through the line.
(c) In response to the transaction data received from the parent cash register, the child cash register performs the operation of registering the additional data and then temporarily balances the book.
(d) In temporarily balancing the book, the child cash register transfers the updated transaction data to the parent cash register.
(e) In response to the transaction data transferred from the child cash register, the parent cash register updates the corresponding transaction data in the master file.
(f) The steps (a) to (e) are repeated.

The foregoing system, however, has a shortcoming that when a failure causes the parent cash register to be inoperative, the overall in-line system must be inoperative, because the master file for storing the transaction data is provided only in the parent cash register. While the parent cash register is inoperative, the child cash register has to be operated as an individual device. If, therefore, the in-line system is provided with a plurality of child cash registers, it is impossible to draw the transaction data from all the child cash registers.
EP 0 187 523 A3 discloses a point of sales (POS) system in which a POS terminal can obtain data such as article prices from a central computer having a price look-up (PLU) table storing such article data. More particularly, it relates to a POS system in which article data stored in the PLU table can be immediately and easily updated from individual POS terminals. The POS system of the present invention can be used for sales management in a department store or supermarket.
A total of n-units of POS terminals disposed at counters are respectively connected to two controllers disposed at an office and acting as central computers via a line. The constitution of each of the POS terminals is the same, as is the constitution of each of the controllers. One of the controllers is utilized as a backup for the other controller.
Each of the controllers comprises a main central processing unit (CPU) for processing the task demanded by the POS terminal, a line sub CPU for executing control of the line for the POS terminals, an arithmetic CPU for executing an arithmetic process, a release processing portion for processing a release process when a controller malfunctions, and polling supervisory portion for supervising a polling signal generated at the other side controller and checking whether the other side controller is in a normal condition or in a failure condition, etc. The main CPU holds a prize look-up (PLU) file. The PLU file comprises a PLU table and a classified total file.
US-4 169 288 discloses another point of sale system having an active and a spare data processing system. Each of these systems includes separate read/write memories with only one of the systems being active at a given time, but with the active system being able to selectively acquire data from the read/write memory of the spare system upon start-up. It further includes means for verifying which read/write memory of the active or the spare system contains valid, most current data which is then transferred to whichever system is the active system. The read/write memories of each of the two systems have a built-in generation number counter which is incremented by one whenever either the data of the inactive read/write memory is caused to be transferred to the active read/write memory or whenever the counts in the generation number counters of both read/write memories are equal. This change in the generation number counters takes place only at the start-up of the system.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to provide an electronic cash register system having a plurality of cash registers including a parent cash register, which can keep operating even if the parent cash register becomes inoperative.
According to the present invention, the above object can be achieved by an electronic cash register system including: a parent electronic cash register provided with a first control device and a first memory for registering a transaction data inputted thereto; a quasi-parent electronic cash register provided with a second control device and a second memory for registering a transaction data inputted thereto; a child electronic cash register provided with a third control device for registering a transaction data inputted thereto; and a line for communicating the registers to one another. The first, second and third control devices accomplish a mutual communication between the parent, quasi-parent and child registers through the line and controlling the registers so as to store the data registered by the parent, quasi-parent and child registers into the first and second memories respectively when the parent register operates normally, store the data registered by the quasi-parent and child registers into the second memory when the parent register becomes inoperative, and transfer the data stored in the second memory to the first memory after the parent register is recovered to operate normally.
In the system of the present invention, as mentioned above, the parent register is provided with the first memory while the quasi-parent memory is provided with the second memory. These first and second memories store the same content when these parent and quasi-parent registers operate normally in the in line operation of the system. When the parent register becomes inoperative by a failure, the second and third control devices of the quasi-parent and child registers notice this inoperative condition of the parent register by the mutual communication with the first control device of the parent register. Then, the second and third control devices control the quasi-parent and child devices such that the second memory stores the transaction data inputted to the quasi-parent and child registers so as to continue the in-line operation of the system. After the parent register is recovered to operate normally, the first control device instructs to the second control device such that the quasi-parent register transfers the data content stored in the second memory to the first memory. Then, the first, second and third control devices control the registers so as to resume the normal in-line operation of the system.
As described above, the system of the present invention makes it possible to make the quasi-parent register acting as an alternative of the parent register when some cause brings the parent register into the inoperative condition, and thus the system can keep operating by the cooperation of the remaining quasi-parent and child registers even if the parent register becomes inoperative.
Further objects and advantages of the present invention will be apparent from the following description of the preferred embodiment of the invention as illustrated in the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

Fig. 1 is a block diagram showing the overall arrangement of one embodiment of the invention;
Fig. 2 is a view exemplarily illustrating how the in-line system shown in Fig. 1 operates normally;
Fig. 3 is a flowchart illustrating how a processing circuit of a child cash register operates;
Fig. 4 is a flowchart illustrating how the processing circuit of the child cash register operates when the parent cash register becomes inoperative;
Fig. 5 is a flowchart illustrating how the processing circuit of the child cash register operates after the parent cash register is recovered;
Fig. 6 is a flowchart illustrating how a processing circuit of a parent cash register operates;
Fig. 7 is a flowchart illustrating how the processing circuit of the parent cash register operates when it receives a response indicating the presence of transaction data;
Fig. 8 is a flowchart illustrating how the processing circuit of the parent cash register operates when the parent cash register is recovered to operate normally;
Fig. 9 is a flowchart illustrating how a processing circuit of a quasi-parent cash register operates;
Fig. 10 is a flowchart illustrating how the processing circuit of the quasi-parent cash register operates as an alternative of the parent cash register when the parent cash register becomes inoperative; and
Fig. 11 is a flowchart illustrating how the processing circuit of the quasi-parent cash register operates when the parent cash register is recovered to operate normally.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

A preferred embodiment of the present invention will be described below with reference to the accompanying drawings.
Fig. 1 is a block diagram showing the overall in-line system according to an embodiment of the invention. The in-line system includes a parent electronic cash register 11, a quasi-parent electronic cash register 12, a child electronic cash register 13, and a line 14 consisting of a cable. Those registers 11, 12 and 13 are connected through the line 14 for communicating them with one another. The parent cash register 11 and the quasi-parent cash register 12 respectively have master files 15 and 16.
Fig. 2 exemplarily illustrates how the in-line system shown in Fig. 1 operates normally. The operation will be carried out as follows.

(A) A user registers the new transaction data, that is, performs the look-up operation at the child cash register 13. Thus, the child cash register 13 sends out a request message 17 about the transaction data to the parent cash register 11 through the line 14.
(B) In response to the request message 17 about the transaction data sent at the step (A), the parent cash register 11 serves to draw the corresponding transaction data from the master file 15 and then transfer it to the child cash register 13 as indicated by an arrow 18. At the same time, the parent cash register 11 sends out a check message 19 for checking the presence or absence of the transaction data to the quasi-parent cash register 12. This check message 19 is used for making sure if the master file 15 of the parent cash register 11 has the same store content as the master file 16 of the quasi-parent cash register 12. The quasi-parent cash register 12 serves to send out a response 20 indicating the presence or absence of the corresponding transaction data to the parent cash register 11. If the quasi-parent 12 does not have the corresponding transaction data, that is, it sends out the response indicating that it does not operate normally, the parent cash register 11 displays the error condition on a display 21 or prints it on paper so as to allow the user to see it.
(C) The child cash register 13 serves to perform additional registration for, that is, update the transaction data received from the parent cash register 11 and then temporarily balance the book.
(D) The transaction data updated in the child cash register 13 is transferred to the parent cash register 11.
(E) In response to the transaction data sent from the child cash register 13, the parent cash register 11 serves to update the corresponding transaction data in the master file 15 of the parent cash register 11. At the same time, the parent cash register 11 serves to transfer the transaction data to the quasi-parent cash register 12.
(F) In response to the transaction data sent from the parent cash register 11, the quasi-parent cash register 12 serves to update the corresponding transaction data.
(G) Later, the foregoing steps (A) to (F) are repeated.

The parent cash register 11 and the quasi-parent cash register 12 are effective as the child cash register and can perform those steps (A) to (F) as the child cash register. In this operation as the child cash register, these registers 11 and 12 allow the transaction data to be directly transferred to each of the master files 15 and 16 without transferring the transaction data through the line 14.
The parent cash register 11, the quasi-parent cash register 12, and the child cash register 13 respectively include input means 22, 23, 24 and processing circuits 25, 26, 27 realized by microcomputers, for example. These input means are used for registering the transaction data and performing the look-up operation. The parent cash register 11 includes the display 21 as mentioned above. Likewise, the quasi-parent cash register 12 and the child cash register 13 respectively provide displays 28 and 29.
Figs. 3, 4 and 5 are flowcharts illustrating how the processing circuit 27 included in the child cash register 13 operates.
As shown in Fig. 3, the operation of the child cash register 13 starts at a step a1, then the transaction data is registered at a step a2. Then, at a step a3, the child cash register 13 sends out the request message about the transaction data to the parent cash register 11 through the line 14. At a step a4, the child cash register 13 receives the transaction data stored in the master file 15 of the parent cash register 11. Proceeding to a step a5, the new data is registered on the input means 24. At a step a6, the child cash register 13 temporarily balances the book. Then, at a step a7, the child cash register 13 transfers the resulting transaction data to the parent cash register 11 through the line 14. Then, this sequential operation of the child cash register 13 is finished at a step a8.
Fig. 4 is a flowchart illustrating how the child cash register 13 operates when the parent cash register 11 becomes inoperative. The flow starts at a step C1 when the child cash register is operating normally as in Fig. 3. Then, when a failure causes the parent cash register 11 to be inoperative, at a step c2, the child cash register 13 judges if it receives a declaration message from the quasi-parent cash register 12 for acting as an alternative of the parent cash register 11. If the child cash register 13 receives the declaration message, at a step c3, it sets to communicate with the quasi-parent cash register 12 in place of the parent cash register 11 and this setting operation of the child cash register 13 is finished at a step c4.
Fig. 5 is a flowchart illustrating how the child cash register 13 operates after the parent cash register 11 is recovered. At a step d1, the child cash register 13 is communicating with the quasi-parent cash register 12. When the child cash register 13 judges that the parent cash register 11 is recovered to operate normally at a step d2, the child cash register 13 is reset to communicate with the parent cash register 11 at a step d3. Then, at a step d4, this resetting operation is finished.
When the child cash register 13 sets to communicate with the quasi-parent cash register 12 at the step c3 in Fig. 4 in response to the parent-declaration message sent from the quasi-parent cash register 12, the communication of the transaction data done at the steps a2 to a7 in Fig. 3 is executed between the child cash resister 13 and the master file 16 of the quasi-parent cash register 12.
Fig. 6 is a flowchart illustrating how the processing circuit 25 provided in the parent cash register 11 operates. The flow starts at a step b1 when the parent cash register is operating normally. At a step b2, the parent cash register 11 receives the request message about the transaction data from the child cash register 13 or the quasi-parent cash register 12. Proceeding to a step b3, the parent cash register 11 serves to retrieve the master file 15 and then, at a step b4, transfer the corresponding transaction data retrieved from the master file 15 to the child cash register 13. At a step b5, the parent cash register 11 sends out a check message for checking the presence or absence of the transaction data to the quasi-parent cash register 12. Then, at a step b6, the register 11 judges if it receives a response indicating the presence or absence of the corresponding transaction data from the quasi-parent cash register 12. If no transaction data is found, that is, an error takes place in the quasi-parent cash register 12, at a step b7, the display 21 indicates the error condition. If it is judged that there takes place no error, this sequential operation of the processing circuit 25 is finished at a step b8.
Fig. 7 is a flowchart illustrating how the processing circuit 25 provided in the parent cash register 11 operates when it receives the response indicating the presence of the corresponding transaction data. The flow starts at a step el when the parent cash register 11 is operating normally. At a step e2, the parent cash register 11 receives the transaction data inputted and temporarily balanced in the child cash register 13 or the quasi-parent cash register 12. Then, at a step e3, the register 11 serves to update the corresponding data in the master file 15. In addition, before receiving the transaction data from the child cash register 13 or the quasi-parent cash register 12, the parent cash register 11 can execute the other process. At a step e4, if no error takes place at the step b6, the register 11 serves to send out the corresponding transaction data to the quasi-parent cash register 12 in such a manner as to allow the content stored in the master file 16 to be equal to that stored in the master file 15. Then, this sequential operation of the processing circuit 25 is finished at a step e5.
Fig. 8 is a flowchart illustrating how the processing circuit 25 of the parent cash register 11 operates when the register 11 is recovered to operate normally after a failure caused it to stop. The flow starts at a step f1 when the operation of the parent cash register 11 is inoperative by the failure. If it is judged that the parent cash register 11 is recovered to operate normally at a step f2, then at a step f3, the parent cash register 11 receives and collects the transaction data from the master file 16 provided in the quasi-parent cash register 12 and stores it in the master file 15. At a step f4, the parent cash register 11 sends out the declaration data for acting as a parent cash register to the child cash register 13. Then, at a step f5, this sequential operation of the processing circuit 25 is finished.
Fig. 9 is a flowchart illustrating how the processing circuit 26 provided in the quasi-parent cash register 12 operates. The flow starts at a step g1 when the registers 11 and 12 are communicating with each other. At a step g2, the quasi-parent cash register 12 receives a check message indicating the presence or absence of the transaction data from the parent cash register 11. At a step g3, the register 12 sends out a response. Then, at a step g4, the register 12 receives the transaction data from the parent cash register 11 in normal operation and updates the master file 16 at a step g5. Then this operation of the registers 11 and 12 is finished at a step g6.
Fig. 10 is a flowchart illustrating how the quasi-parent cash register 12 operates as an alternative of the parent cash register 11 when the parent cash register 11 is made inoperative. The flow starts at a step h1 when the parent cash register 11 is inoperative. At a step h2, it is judged if an external operation to make the quasi-parent cash register 12 act as an alternative of the parent cash register 11 is performed via the input means 23 or not when the register 11 is inoperative. If the judgement is YES, at a step h3, the quasi-parent cash register 12 sends out the declaration data for acting as a parent cash register to the child cash register 13 through the line 14. In response to the declaration data, the child cash register 13 can communicate with the quasi-parent cash register 12 in the similar manner that it communicates with the parent cash register 11. At a step h4, the quasi-parent cash register 12 instructs the child cash register 13 to prohibit the communication with the parent cash register 11. Then, this alternative setting operation is finished at a step h5.
Fig. 11 is a flowchart illustrating how the quasi-parent cash register 12 operates when the parent cash register 11 is recovered to operate normally. The flow starts at a step j1 when the quasi-parent cash register 12 is operating as the alternative of the parent cash register 11. At a step j2, the quasi-parent cash register 12 receives a parent-cash-register-recovering declaration from the parent cash register 11. Then, at a step j3, the register 12 serves to transfer the transaction data stored in the master file 16 to the master file 15 of the parent cash register 11. Thus, after recovering the parent cash register 11, the parent cash register 11 accomplishes the following operation based on the content stored in the master file 15. At a step j4, the registers 12 and 13 are reset to communicate with the parent cash register 11. Then, this recovering operation is finished at a step j5.
When the parent cash register 11 is recovered, with the operation of the input means 22, the quasi-parent cash register 12 serves to transfer the latest transaction data stored in the master file 16 to the master file 15 of the parent cash register 11 in such a manner as to allow the register 11 to collect the transaction data. This operation is carried out at the step f3 as shown in Fig. 8. The operations illustrated in Figs. 3, 8 and 10 are main process and the operations illustrated in Figs. 4, 5, 6, 7, 9 and 11 are sub process.
As discussed above, when some cause makes the parent cash register 11 inoperative, the quasi-parent cash register 12 can act as the alternative of the parent cash register 11. It results in being able to prevent the overall in-line system from being inoperative until the parent cash register 11 is recovered. When the parent cash register 11 is recovered, the parent cash register 11 can draw the latest transaction data from the master file 16 of the quasi-parent cash register 12 to the master file 15 and collect all the data in the master file 15. This operation makes it possible to precisely return the transaction data involved in the overall in-line system to the parent cash register 11.

Claims

An electronic cash register system comprising:
a parent electronic cash register (11) provided with a first control means (25) and a first memory (15) for registering a transaction data inputted thereto;
a quasi-parent electronic cash register (12) provided with a second control means (26) and a second memory (16) for registering a transaction data inputted thereto;
a child electronic cash register (13) provided with a third control means (27) for registering a transaction data inputted thereto; and
a line (14) for communicating said registers to one another;
said first to third control means (25,26,27) accomplishing a mutual communication between said parent, quasi-parent and child registers (11,12,13) through said line (14) and controlling said registers (11,12,13) so as to store said data registered by said parent, quasi-parent and child registers into said first (15) and second (16) memories, respectively, when said parent register (11) operates normally, store said data registered by said quasi-parent and child registers (12,13) into said second memory (16) when said parent register (11) becomes inoperative, and transfer said data stored in said second memory (16) to said first memory (15) after said parent register (11) is recovered to operate normally.
A system according to Claim 1, wherein each of said first to third control means (25,26,27) comprises a processing circuit.
A system according to Claim 2, wherein said processing circuit comprises a microcomputer.
A system according to Claim 1, wherein each of said parent, quasi-parent and child registers (11,12,13) are provided with an input means (22, 23, 24) at which said transaction data are inputted.
A system according to Claim 1, wherein each of said quasi-parent and child registers (12, 13) are provided with a display means (28, 29) for displaying a message indicating that said parent register (11) becomes inoperative.
A system according to Claim 1, wherein said parent register (11) is provided with a display means (21) for displaying a message indicating that an error takes place in said system.
A system according to Claim 1, wherein control signals made by each of said first to third control means (25,26,27) are sent between said parent, quasi-parent and child registers (11,12,13) through said line (14) so as to notice a condition of said parent, quasi-parent and child registers (11,12,13) to one another.
A system according to Claim 7, wherein said control signals include a declaration message signal, which indicates that said quasi-parent register (12) acts as an alternative of said parent register (11) and is sent to said child register (13) from said quasi-parent register (12) when said parent register (11) becomes inoperative.
A system according to Claim 7, wherein said control signals include a declaration message signal, which indicates that said parent register (11) is recovered to operate normally and is sent to said child register (13) from said parent register (11) when said parent register (11) is recovered to operate normally.