EP0365071A2 - Method for distributing data signals over broadcast satellites - Google Patents

Abstract

Matching circuits can be used for transmitting data streams of up to 704 kbit/s, protected against bit errors, and, at the same time, data streams of up to 192 kbit/s, unprotected against bit errors, in a stereo channel of the digital satellite radio system (DSR). This provides the possibility of inexpensive distribution of the data streams over a large area. The DSR system transmits 16 stereo audio channels, one or several channels of which can be utilised for data transmission without influencing the audio transmission of the remaining audio channels. The normal DSR tuners can be used for receiving the data. The data streams of, for example 64 kbit/s, must be processed at the transmitting end in such a manner that changes in transit time on the feed line do not cause any bit errors and that the data, divided into substreams of 32 kbit/s each, are offered synchronously with the transmit clock to a radio coder as input to the system. At the receiving end, the original continuous data stream including the associated clock must be restored from the data stream emitted as data burst. <IMAGE>

Description

The invention relates to a method for distributing data signals via a transmission system for digital radio via radio satellites.

In the publication "Digital radio via radio satellites", published by the Federal Minister for Research and Technology, 2nd revised edition, a transmission system for radio via radio satellites is described. This transmission system can be assigned 16 stereo or 32 mono sound signals. 4 mono sound signals each form a subframe with the bits required for error protection. Two additional bits per subframe offer the possibility of transmitting a narrowband data channel. However, this data channel is reserved for the transmission of a scale factor. The system also includes a narrow-band data channel, on which data accompanying the program is transmitted.

A transmission device as a feeder for this transmission system is in the Rohde u. Black "AUDIO CODER DCA" described. This device also offers the option of entering tone code words in parallel. The disadvantage of these devices in data transmission is that a 14-bit tone code word is formed from a 16-bit tone code word at the input. This formation takes place with the help of a scale factor, which is in the newly formed

Tone code word is not included, but is transmitted separately. The transcoding means that the transmission of data signals is not readily possible, since they cannot always be reconstructed correctly on the receiving end.

A receiver for digital sound signals "DSR tuner St 900 SAT" from Telefunken includes a digital signal interface, on which the received bits of several sound channels are only available as a burst and uncorrected. A disadvantage of this receiver is that an error coverage method is used for transmission errors, which causes an unacceptable failure of data bits during data transmission when the data of a channel is evaluated.

In general, it should be noted that, although this transmission system is in principle suitable for transmitting a data signal instead of coded audio signals, the terminals on the market without modifications or additional circuits are not suitable for this. The mere fact that the data on the sending side can only be fed in at 14 kBit / s step speed in 14-bit parallel and that on the receiving side is available in a data burst with about 5 Mbit / s step speed would make completely new interfaces and possibly require changed transmission protocols for the end devices.

The invention is based on the object of specifying a method with which a plurality of data signals, each preferably 64 kbit / s, can be transmitted and distributed over a stereo audio channel and that on the receiving side, these data signals can be divided into continuous bit streams.

This invention is solved by the characterizing part of the main claim.

Advantageous developments of the inventions are explained in more detail in the subclaims.

Embodiments according to the invention are explained in more detail in the drawing.

• Fig. 1 den Aufbau eines Unterrahmens eines Übertragungssystems für digitalen Hörfunk über Rundfunksatelliten,
• Fig. 2 eine sendeseitige Anpaßschaltung zur Übertragung von Datensignalen,
• Fig. 3 die maßgeblichen Impulsdiagramme innerhalb der Anpaß­schaltung nach Fig. 2,
• Fig. 4 das Schaltbild einer zugehörigen empfangsseitigen Anpaßschaltung zur Übertragung von Datensignalen.

It shows

• 1 shows the structure of a subframe of a transmission system for digital radio via radio satellites,
• 2 shows a transmitter-side adapter circuit for the transmission of data signals,
• 3 shows the relevant pulse diagrams within the matching circuit according to FIG. 2,
• Fig. 4 shows the circuit diagram of an associated receiving circuit for the transmission of data signals.

The subframe UR shown in FIG. 1 of the transmission system for radio via radio satellites consists of each eleven high-order bits of four tone code words W1 to W4, which are protected against bit errors with a total of 19 bits CB by means of a BCH error precoding and together form a BCH block BCH; two additional information bits IB for the transmission of the scale factor and the remaining three low-order bits LB of the four tone code words W1 to W4. Each subframe UR thus consists of 77 bits and has a repetition frequency of 32 kHz, which corresponds to the frame repetition frequency of the entire system.

If, as indicated in FIG. 1, the first two useful bits MB of the BCH block BCH are occupied with data bits DB, a transmission channel for a 64 kbit / s data signal is created. This data channel is error-protected by the BCH coding. The low-order bits of this tone code word that have been released by the transmission of data bits instead of a tone code word can also be used for the transmission of data signals. However, these data signals are not protected by any coding method during transmission. A maximum of twenty-two 64 kbit / s data signals can be saved and six 64 kbit / s data signals can be transmitted unsecured per subframe.

A mixed transfer of e.g. B. low-value 32kBit / s data signals and high-quality data signals in nx 32kBit / s staggering with simultaneous transmission of sound signals is also possible.

By means of the arrangement shown in FIG. 2, a data signal DS of 64 kbit / s is to be fed to a digital broadcast satellite transmission system, the data source and transmitter of the transmission system being spatially separated.

The data source and the transmission system are synchronized to the same frequency. Due to changes in transit time, caused by changes in path length, as can occur when switching to other supply paths of the data signal DS to the transmitter, the clock TG4g of the data signal is not phase-locked to the clock of the transmission system.

The data signal DS with the associated clock T64q of the data source passes through a matching circuit 21 to a serial / parallel converter 22, which divides the data signal DS into two partial data streams Dq1 and Dq2 of half the bit rate. At the same time, the clock of the data source T64q is halved in a divider 23 and fed to a first-in / first-out memory 24 as a read-in clock T32q for the partial data streams Dq1 and Dq2.

The reading of the data from the first-in / first-out memory 24 is controlled by the clock of the transmitter T32s, so that the partial data streams Ds1 and Ds2 which have been stored out are bit-synchronous with this clock. After passing through an output register 25 and an output driver 26, the partial data streams Ds1 and Ds2 can be fed into the transmission system.

If the first-in / first-out memory 24 is filled up to half of its memory capacity with the incoming partial data streams Dq1 and Dq2 before the first write-out, runtime differences in the positive and negative direction can be compensated for up to half the memory capacity.

In addition, an auxiliary clock T64s can be generated from the transmitter clock T32s via a frequency doubler 27, which is supplied to the data source for synchronization or control in the absence of a common network clock.

In transmitters of the transmission system with input bit reduction of the tone code words from 16 bits to 14 bits, the transmitter must be given a fixed scale factor so that none of the 14 data bits is suppressed.

3 shows the clock of the data source T64q over time in the first row and the data signal DS in the second row.

The partial data streams Dq1 and Dq2 resulting from the serial / parallel conversion are plotted in the third and fourth rows.

The fifth row shows the clock of the transmitter T32s, which is not phase-locked to the (halved) clock of the data source T64q.

Because of the known mode of operation of the first-in / first-out memory, the partial data streams Ds1 (sixth row) and Ds2 (seventh row) are created. In reality, the delay time VZ, which is caused by the reading of the memory offset for reading in to compensate for the runtime, is substantially greater than the approx. Four bit lengths indicated here.

The function of the matching circuit at the receiving end is explained with reference to FIG. 4. The signals clock burst TB, data burst DB and synchronizing pulse S reach the circuit via input amplifier 41. A first counter 42 counts the number of clock pulses in the clock burst, predetermined by a switch 43, following a synchronizing pulse, and releases a second counter 44 after the predetermined counter position has been reached. In this exemplary embodiment, eight clocks, corresponding to four 64 kbit / s data signals to be transmitted, are counted. For this time, the clock burst is switched via an AND gate 45 to the clock input of a serial / parallel converter 46, so that exactly eight data bits are read into this converter.

From the sequence of the synchronizing pulses S (exactly one pulse per frame), a phase-controlled oscillator 47 and a third divider 48 are used to generate a phase-locked clock with a synchronous pulse sequence (32 kHz) with a clock frequency of 64 kHz, which corresponds to the data clock T64e of 64 kHz / s data signals.

The data are read from the serial / parallel converter 46 with the synchronous pulse sequence S as a clock into an intermediate register 49. In a subsequent parallel / serial converter 410, the data sequences are converted in such a way that a serial data stream with 64 kbit / s arises from two parallel data streams with 32 kbit / s each. The writing and reading out into or from this parallel / serial converter 410 is controlled by the synchronizing pulses S.

The four higher-rate data streams obtained in this way are clocked in an output register 411 and are available together with the data clock T64e via output drivers 412 as 64 kbit / s data signals DS1 to DS4 for further processing.

Claims (10)

1. Method for distributing data signals via a transmission system for digital radio via radio satellites, the repetition frequency of the audio signal words (W1-W4) being 32 kHz and the 11 higher-order bits of four 14-bit audio signal words using a 44/63 bit BCH coding method for fail-safe transmission to a BCH block (BCH), consisting of the 44 useful bits (MB) and 19 bits for error pre-coding (CB), and the remaining four times 3 low-order, non-error-protected bits (LB) of these Tone signal words and the additional information bits (IB) form a subframe (UR),
characterized,
that instead of a useful bit (MB) of a BCH block (BCH), a bit of a 32 kbit / s data signal (DB) is transmitted protected against bit errors and / or that instead of a non-error-protected bit (LB) of a subframe (UR) a bit of a 32 kbit / s data signal (DB) is transmitted unprotected against bit errors. 2. The method according to claim 1, characterized in that instead of a mono audio signal, eleven 32 kbit / s data signals are transmitted protected against bit errors and three 32 kbit / s data signals are transmitted unprotected against bit errors. 3. The method according to claim 1, characterized in that a higher-rate data signal is divided into a plurality of 32 kbit / s data signals on the transmission side. 4. The method according to claim 3, characterized in that a plurality of 32 kbit / s data channels are combined at the receiving end to form the original higher-rate data signal. 5. The method according to claim 1, 3 and 4, characterized in that instead of a stereo sound signal, eleven 64 kbit / s data signals secured against bit errors and three 64 kbit / s data signals unsecured against bit errors are transmitted. 6. The method according to claims 2 to 4, characterized in that audio signals and data signals are simultaneously transmitted in different channels via the transmission system. 7. The method according to claim 1, characterized in that the original instead of a previous bit reduction sound signals to be transmitted by means of a floating point technique (scale factor), a scale factor that is dependent on the data content and is not dynamically changing is generated for the 14 bits of a digital word occupied by data signals, the maximum amplitude of the sound signal is constantly signaled and a constant scale factor is thus specified. 8. The method according to claim 6, characterized in that the transmission system and the data source of the data signals are synchronized to a common clock. 9. The method according to claim 8, characterized in that phase differences between the clock of the transmission system and the clock of the data source due to runtime changes of the data signal in a first-in / first-out memory (24) for the bits of the data signals are compensated. 10. The method according to claim 6, characterized in that on the receiving side the clock of the data signals (T64e) is derived phase-locked from the clock of the transmission system.

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