EP0288353B1 - Method for switching asyschronous digital signals, and device for carrying out this method - Google Patents

Method for switching asyschronous digital signals, and device for carrying out this method Download PDF

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Publication number
EP0288353B1
EP0288353B1 EP88400857A EP88400857A EP0288353B1 EP 0288353 B1 EP0288353 B1 EP 0288353B1 EP 88400857 A EP88400857 A EP 88400857A EP 88400857 A EP88400857 A EP 88400857A EP 0288353 B1 EP0288353 B1 EP 0288353B1
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Prior art keywords
switching
signal
digital signal
multiplexer
signals
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German (de)
French (fr)
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EP0288353A1 (en
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Alain Weisser
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Telediffusion de France ets Public de Diffusion
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Telediffusion de France ets Public de Diffusion
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04H—BROADCAST COMMUNICATION
    • H04H60/00—Arrangements for broadcast applications with a direct linking to broadcast information or broadcast space-time; Broadcast-related systems
    • H04H60/02—Arrangements for generating broadcast information; Arrangements for generating broadcast-related information with a direct linking to broadcast information or to broadcast space-time; Arrangements for simultaneous generation of broadcast information and broadcast-related information
    • H04H60/04—Studio equipment; Interconnection of studios

Definitions

  • the subject of the present invention is a method for switching asynchronous digital signals, and a device for implementing this method.
  • the invention applies in all fields where it is necessary to switch asynchronous digital signals, in which each digital signal is composed of a series of independent data blocks such as a series of frames.
  • the invention finds particular application in audiovisual production or transmission centers in which switching grids are used to establish communication paths between different pieces of equipment by switching links.
  • switching grids are used to establish communication paths between different pieces of equipment by switching links.
  • Digital audio signals are exchanged between equipment in an audiovisual production or transmission center via a serial interface, known as the EBU / AES studio interface, standardized by the International Telecommunication Advisory Committee (CCIT).
  • the digital signal emitted by an interface is organized in 64-bit frames allowing the transmission of the left and right samples of a stereophonic program. For example, with a sampling frequency of 48 kilohertz, the online throughput is 3.072 megabits per second.
  • the signal transmitted on the line is coded in two-phase code, which provides significant redundancy to the transmitted signal.
  • This signal contains all the necessary synchronization information and in particular the bit and sample rates. Synchronization at the level of the sample is obtained by the use of preambles violating the laws of coding of the biphase code.
  • the serial structure of the EBU / AES interface lends itself well to the creation of spatial type switching grids, which are the functional replica of the switching grids used for analog signals.
  • the switching function therefore consists in sending the signal present on the appropriate input to a given output of the grid using a logic multiplexer, as shown in the diagram in FIG. 1.
  • This switching device mainly comprises a logic multiplexer 2 having for example 16 inputs Y0, Y1, ..., Y15, and an output. It also has 16 input stages 40, 41, ..., 415 to adapt a signal received from a standardized interface to make it compatible with the multiplexer, for example to convert a signal according to the RS432 standard, received from the EBU / AES interface, in a TTL signal.
  • the switching device finally comprises an output stage 6 for adapting the signal delivered by the multiplexer 2 in order to make it compatible with the standardized interfaces.
  • This spatial switching device has the advantage, compared to a time type switching such as that conventionally used in telephone auto-switches, of not requiring precise synchronization between the digital signals to be switched.
  • the switching device represented in FIG. 1 thus makes it possible to ensure switching between digital signals coming from interfaces whose frames are not in phase, either because the sampling frequencies differ slightly, or because the times of transit in the equipment and cables involved will not be matched.
  • FIG. 2 A switching is effected between a signal S1 composed of a sequence of frames i, i + 1, i + 2, ... and a signal S2 composed of a sequence of frames j , j + 1, j + 2, ... Switching takes place during frame i + 1 for signal S1 and frame j + 1 for signal S2.
  • the resulting signal SR therefore comprises the frame i of the signal S1, a sequence SQ containing the start of the frame i + 1 and the end of the frame j + 1, the frame j + 2 of the signal S2, ...
  • the sequence SQ between frame i and frame j + 2 of the resulting signal SR is an abnormal sequence on the one hand by its length, and on the other hand because it is not a frame.
  • a suitably designed receiver can recognize this anomaly thanks to the discontinuity of the frame rate in the resulting signal SR and use known methods of concealment, for example by repetition or by interpolation, to recreate the samples missing in the resulting signal SR.
  • the digital signals S1 and S2 are synchronous.
  • the signal SR resulting from the switching therefore consists of a series of frames, because the sequence SQ composed of the start of the frame i + 1 of the signal S1 and the end of the frame j + 1 of the signal S2 also has a structure weft.
  • the receiver receiving the resulting signal SR cannot therefore detect the switching and interprets the erroneous data contained in the abnormal sequence SQ. Switching can then result, during the sound reproduction of the digital audio signal, by a loud "click" sound.
  • the result of switching during transmission of a data sample of a frame is shown in Figure 4, in the case where the frames of the two digital audio signals are synchronous.
  • the data D1 and D2 are contained respectively in the frames i + 1 and j + 1 (cf. FIG. 3) and each represents the coded value of a sample of an audible signal. These samples are coded in complement to two, typically on 16 bits, that is to say over the interval -32768 to +32767.
  • Data D1 of value 0 represents a level 0 sample, resulting from perfect silence.
  • the data D2 composed of a series of symbols "1”, represents in complement code for two a sample of level -1, that is to say a negative sound signal of very low relative amplitude.
  • the data DR resulting from the switching represents a relatively high amplitude sample, that is to say a very different level sample from each of the two signals which have been switched. During the restitution of the sound signal, there therefore appears at the time of switching a parasitic sample of high amplitude which is perceived as a sound "click".
  • One method of overcoming this drawback could consist in switching frames at a determined point, for example during the preamble, auxiliary data or insignificant bits of the coded samples.
  • a method comparable to that which is implemented in the video domain where one switches during the suppression of frame, would require the extraction of the frame rate of at least one of the two signals. This would greatly complicate the switching method and would not improve the situation when the frames are not synchronous.
  • the object of the invention is a simple switching method which can be detected by the receiver receiving the signal resulting from the switching. Since the switching is recognized by the receiver, the receiver can use conventional concealment methods to mask this switching.
  • the invention relates to a method asynchronous digital signal switching, for producing a resultant signal by switching between a first digital signal and a second digital signal, said first and second signals each being composed of a sequence of frames and being asynchronous, this method being characterized in that it consists, during switching, in introducing into the resulting signal a characteristic sequence between said first signal and said second signal.
  • said characteristic sequence is a predetermined digital signal violating the code used to represent the data contained in the first or the second digital signal.
  • This predetermined digital signal can in particular be a clock signal.
  • said characteristic sequence consists of a permanent state.
  • the device further comprises means for synthesizing a predetermined digital signal
  • the multiplexer comprises a third input receiving said predetermined digital signal, the control means controlling the transmission of said predetermined digital signal as a characteristic sequence during switching.
  • said predetermined digital signal is a violation of the code used for coding the data of the first or second digital signal.
  • the transmission means can be a clock generator.
  • said control means is connected to an input for selecting the multiplexer, said characteristic sequence consisting of a permanent state corresponding to an inhibition of the multiplexer.
  • the switching device shown in Figure 5 mainly comprises a multiplexer 2 and a control means 8.
  • the switching device can also include input stages 40, ..., 415, and an output stage 6 placed respectively on the inputs and on the output of the multiplexer 2 .
  • the inputs of the multiplexer are connected to means for transmitting digital signals, such as interfaces for production center equipment or audiovisual transmission.
  • means for transmitting digital signals such as interfaces for production center equipment or audiovisual transmission.
  • one of the inputs of the multiplexer 2 is connected to a means 10 for transmitting a predetermined digital signal, for example a clock signal generator.
  • the selection of the inputs of the multiplexer is carried out by the control means 8 via a channel 12.
  • the multiplexer 2 has 16 inputs Y0, Y1, ..., Y15, and therefore channel 12 has 4 wires C0-C3.
  • This control means 8 comprises a microprocessor 14, a data bus 16, a register 18 whose data input is connected to the data bus 16 and the output to channel 12, an address bus 20, and a decoder with address 22, the input of which is connected to the address bus 20 and the output of which is connected to a selection input CS of the register 18.
  • the register 18 is used to store data corresponding to the selection of an input of the multiplexer 2, and the address decoder 22 makes it possible to load the content of the register from the data bus of the microprocessor.
  • the switching method implemented by the device shown in FIG. 5 for switching from a signal S1 applied to the input Y i of the multiplexer to a signal S2 applied to the input Y j of the multiplexer is as follows. Firstly, the microprocessor 14 delivers to the register 18 data corresponding to the selection of the input Y15 of the multiplexer so that the digital signal predetermined by the transmission means 10 replaces the signal S1 on the output of the multiplexer. In a second step, the microprocessor 14 delivers to the register 18 a data item corresponding to the selection of the input Y j of the multiplexer.
  • the predetermined digital signal delivered by the transmission means 10 can be constituted for example by the permanent transmission of the preamble of the frames of the digital signals S1 and S2, or of any other signal violating the coding rules used for the coding of the samples .
  • the transmission means 10 can for example transmit a clock signal at 1024 kilohertz, the interval between corresponding transitions then at 1.5 times the duration of a bit, which violates the rules of the coding used.
  • FIG. 6 shows a second embodiment of the switching device of the invention.
  • the elements identical to those of Figure 5 have the same reference.
  • the essential difference with the device of FIG. 5 resides in that there is not provided a means of transmitting a particular signal connected to one of the data inputs of the multiplexer, but in that the characteristic sequence entered at the time of switching is a permanent logic state resulting from a control pulse applied to the selection input CS of multiplexer 2.
  • the signal delivered by the address decoder 22 to select the register 18 is also applied to the selection input of the multiplexer 2, to deselect the multiplixer and thus force its output into a determined state.
  • the signal applied to the selection input of multiplexer 2 has a duration at least equal to 1.5 times the duration of a bit.
  • the duration of this pulse can be obtained by any suitable means, such as for example an adequate management of the acknowledgment line ACK of the address decoder 22.
  • FIG. 7 shows the resulting signal SR produced by the switching of two digital signals S1 and S2, according to the invention.
  • This SR signal has a sequence particular SP inserted between the digital signal S1 and the digital signal S2.
  • This signal is received by a receiver, which can be included in the EBU / AES studio interface, and which is conventionally designed to appropriately detect transmission errors and / or code breaches, and therefore in particular the SP sequence, and to ensure appropriate processing of the data received.

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  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Time-Division Multiplex Systems (AREA)

Description

La présente invention a pour objet un procédé de commutation de signaux numériques asynchrones, et un dispositif pour la mise en oeuvre de ce procédé.The subject of the present invention is a method for switching asynchronous digital signals, and a device for implementing this method.

L'invention s'applique dans tous les domaines où il est nécessaire de commuter des signaux numériques asynchrones, dans lesquels chaque signal numérique est composé d'une suite de blocs de données indépendants telle qu'une suite de trames.The invention applies in all fields where it is necessary to switch asynchronous digital signals, in which each digital signal is composed of a series of independent data blocks such as a series of frames.

L'invention trouve notamment une application dans les centres de production ou de transmission audiovisuels dans lesquels des grilles de commutation sont utilisées pour établir des chemins de communication entre différents équipements par commutation de liaisons. Dans la description qui suit, on se réfèrera, à titre d'exemple, à cette application.The invention finds particular application in audiovisual production or transmission centers in which switching grids are used to establish communication paths between different pieces of equipment by switching links. In the description which follows, reference will be made, by way of example, to this application.

Les signaux audio numériques sont échangés entre les équipements d'un centre de production ou de transmission audiovisuels par l'intermédiaire d'une interface série, connue sous le nom d'interface de studio UER/AES, normalisée par le Comité Consultatif International des Télécommunications (C.C.I.T.). Le signal numérique émis par une interface est organisé en trames de 64 bits permettant la transmission des échantillons gauche et droite d'un programme stéréophonique. Par exemple, avec une fréquence d'échantillonnage de 48 kilohertz, le débit en ligne est de 3,072 mégabits par seconde.Digital audio signals are exchanged between equipment in an audiovisual production or transmission center via a serial interface, known as the EBU / AES studio interface, standardized by the International Telecommunication Advisory Committee (CCIT). The digital signal emitted by an interface is organized in 64-bit frames allowing the transmission of the left and right samples of a stereophonic program. For example, with a sampling frequency of 48 kilohertz, the online throughput is 3.072 megabits per second.

Le signal émis sur la ligne est codé en code biphase, ce qui assure une redondance importante au signal transmis. Ce signal contient toutes les informations de synchronisation nécessaires et en particulier les rythmes bits et échantillons. La synchronisation au niveau de l'échantillon est obtenue par l'utilisation de préambules violant les lois de codage du code biphase.The signal transmitted on the line is coded in two-phase code, which provides significant redundancy to the transmitted signal. This signal contains all the necessary synchronization information and in particular the bit and sample rates. Synchronization at the level of the sample is obtained by the use of preambles violating the laws of coding of the biphase code.

La structure série de l'interface UER/AES se prête bien à la réalisation de grilles de commutation de type spatial, qui sont la réplique fonctionnelle des grilles de commutation utilisées pour les signaux analogiques. La fonction de commutation consiste donc à envoyer sur une sortie donnée de la grille le signal présent sur l'entrée appropriée à l'aide d'un multiplexeur logique, tel que représenté sur le schéma de la figure 1.The serial structure of the EBU / AES interface lends itself well to the creation of spatial type switching grids, which are the functional replica of the switching grids used for analog signals. The switching function therefore consists in sending the signal present on the appropriate input to a given output of the grid using a logic multiplexer, as shown in the diagram in FIG. 1.

Ce dispositif de commutation comporte principalement un multiplexeur logique 2 ayant par exemple 16 entrées Y₀ , Y₁ , ..., Y₁₅ , et une sortie. Il comporte également 16 étages d'entrée 4₀, 4₁, ..., 4₁₅ pour adapter un signal reçu d'une interface normalisée afin de le rendre compatible avec le multiplexeur, par exemple pour convertir un signal selon la norme RS432, reçu de l'interface UER/AES, en un signal TTL. Le dispositif de commutation comprend enfin un étage de sortie 6 pour adapter le signal délivré par le multiplexeur 2 afin de la rendre compatible avec les interfaces normalisées.This switching device mainly comprises a logic multiplexer 2 having for example 16 inputs Y₀, Y₁, ..., Y₁₅, and an output. It also has 16 input stages 4₀, 4₁, ..., 4₁₅ to adapt a signal received from a standardized interface to make it compatible with the multiplexer, for example to convert a signal according to the RS432 standard, received from the EBU / AES interface, in a TTL signal. The switching device finally comprises an output stage 6 for adapting the signal delivered by the multiplexer 2 in order to make it compatible with the standardized interfaces.

Ce dispositif de commutation spatiale présente l'avantage, par rapport à une commutation de type temporel telle que celle utilisée de manière classique dans les auto-commutateurs téléphoniques, de ne pas exiger une synchronisation précise entre les signaux numériques à commuter.This spatial switching device has the advantage, compared to a time type switching such as that conventionally used in telephone auto-switches, of not requiring precise synchronization between the digital signals to be switched.

Le dispositif de commutation représenté sur la figure 1 permet ainsi d'assurer la commutation entre des signaux numériques issus d'interfaces dont les trames ne sont pas en phase, soit parce que les fréquences d'échantillonnage diffèrent légèrement, soit parce que les temps de transit dans les équipements et les câbles mis en jeu ne seront pas appariés.The switching device represented in FIG. 1 thus makes it possible to ensure switching between digital signals coming from interfaces whose frames are not in phase, either because the sampling frequencies differ slightly, or because the times of transit in the equipment and cables involved will not be matched.

De manière générale, le commutation entre deux signaux audio numériques se fait de façon brutale, sans fondu. Ceci peut donner naissance à des discontinuités sonores sous la forme de "clic". Ces défauts, dont l'amplitude maximale varie avec le niveau du programme sonore, sont acceptables dans un nombre important d'applications. Cependant, il peut arriver que la commutation conduise à un "clic" de forte amplitude, même en présence d'un signal sonore à faible niveau.Generally speaking, switching between two digital audio signals takes place suddenly, without fading. This can give rise to sound discontinuities in the form of a "click". These faults, the maximum amplitude of which varies with the level of the sound program, are acceptable in a large number of applications. However, it may happen that the switching results in a large amplitude "click", even in the presence of a low level audio signal.

Ces défauts peuvent apparaître lors de la commutation entre deux signaux audio numérique asynchrones. Une telle situation est représentée sur la figure 2. Une commutation est opérée entre un signal S1 composé d'une suite de trames i, i+1, i+2,... et un signal S2 composé d'une suite de trames j, j+1, j+2,... La commutation a lieu pendant la trame i+1 pour le signal S1 et la trame j+1 pour le signal S2. Le signal résultant SR comporte donc la trame i du signal S1, une séquence SQ contenant le début de la trame i+1 et la fin de trame j+1, la trame j+2 du signal S2,...These faults can appear when switching between two asynchronous digital audio signals. Such a situation is represented in FIG. 2. A switching is effected between a signal S1 composed of a sequence of frames i, i + 1, i + 2, ... and a signal S2 composed of a sequence of frames j , j + 1, j + 2, ... Switching takes place during frame i + 1 for signal S1 and frame j + 1 for signal S2. The resulting signal SR therefore comprises the frame i of the signal S1, a sequence SQ containing the start of the frame i + 1 and the end of the frame j + 1, the frame j + 2 of the signal S2, ...

La séquence SQ entre la trame i et la trame j+2 du signal résultant SR est une séquence anormale d'une part par sa longueur, et d'autre part car ce n'est pas une trame. De manière classique, un récepteur convenablement conçu peut reconnaitre cette anomalie grâce à la discontinuité du rythme de trame dans le signal résultant SR et utiliser les méthodes connues de dissimulation, par exemple par répétition ou par interpolation, pour recréer les échantillons manquant dans le signal résultant SR.The sequence SQ between frame i and frame j + 2 of the resulting signal SR is an abnormal sequence on the one hand by its length, and on the other hand because it is not a frame. Conventionally, a suitably designed receiver can recognize this anomaly thanks to the discontinuity of the frame rate in the resulting signal SR and use known methods of concealment, for example by repetition or by interpolation, to recreate the samples missing in the resulting signal SR.

Au contraire, lorsque les deux signaux commutés sont synchrones, aucune discontinuité de rythme ne peut être décelée par le récepteur. La figure 3 illustre une telle commutation.On the contrary, when the two switched signals are synchronous, no rhythm discontinuity can be detected by the receiver. Figure 3 illustrates such switching.

Les signaux numériques S1 et S2 sont synchrones. Le signal SR résultant de la commutation est donc constitué d'une suite de trames, car la séquence SQ composée du début de la trame i+1 du signal S1 et de la fin de la trame j+1 du signal S2 a également une structure de trame.The digital signals S1 and S2 are synchronous. The signal SR resulting from the switching therefore consists of a series of frames, because the sequence SQ composed of the start of the frame i + 1 of the signal S1 and the end of the frame j + 1 of the signal S2 also has a structure weft.

Le récepteur recevant le signal résultant SR ne peut donc pas détecter la commutation et interprête les données erronées contenues dans la séquence anormale SQ. La commutation peut alors se traduire, lors de la restitution sonore du signal audio numérique, par un "clic" sonore de forte amplitude.The receiver receiving the resulting signal SR cannot therefore detect the switching and interprets the erroneous data contained in the abnormal sequence SQ. Switching can then result, during the sound reproduction of the digital audio signal, by a loud "click" sound.

Le résultat de la commutation pendant la transmission d'un échantillon de données d'une trame est représenté sur la figure 4, dans le cas où les trames des deux signaux audio numériques sont synchrones. Les données D1 et D2 sont contenues respectivement dans les trames i+1 et j+1 (cf. figure 3) et représentent chacune la valeur codée d'un échantillon d'un signal sonore. Ces échantillons sont codés en complément à deux, typiquement sur 16 bits, c'est-à-dire sur l'intervalle -32768 à +32767.The result of switching during transmission of a data sample of a frame is shown in Figure 4, in the case where the frames of the two digital audio signals are synchronous. The data D1 and D2 are contained respectively in the frames i + 1 and j + 1 (cf. FIG. 3) and each represents the coded value of a sample of an audible signal. These samples are coded in complement to two, typically on 16 bits, that is to say over the interval -32768 to +32767.

La donnée D1, de valeur 0, représente un échantillon de niveau 0, issu d'un silence parfait. De même, la donnée D2 composée d'une suite de symboles "1", représente en code complément à deux un échantillon de niveau -1, c'est-à-dire un signal sonore négatif de très faible amplitude relative.Data D1, of value 0, represents a level 0 sample, resulting from perfect silence. Likewise, the data D2 composed of a series of symbols "1", represents in complement code for two a sample of level -1, that is to say a negative sound signal of very low relative amplitude.

La donnée DR résultant de la commutation représente un échantillon d'amplitude relativement élevée, c'est-à-dire un échantillon de niveau très différent de chacun des deux signaux qui ont été commutés. Lors de la restitution du signal sonore, il apparaît donc au moment de la commutation un échantillon parasite de forte amplitude qui est perçu comme un "clic" sonore.The data DR resulting from the switching represents a relatively high amplitude sample, that is to say a very different level sample from each of the two signals which have been switched. During the restitution of the sound signal, there therefore appears at the time of switching a parasitic sample of high amplitude which is perceived as a sound "click".

Une méthode pour pallier cet inconvénient pourraît consister à effectuer la commutation en un point déterminé des trames, par exemple pendant le préambule, des données auxiliaires ou des bits peu significatifs des échantillons codés. Cependant, une telle méthode, comparable à celle qui est mise en oeuvre dans le domaine vidéo où l'on commute pendant la suppression de trame, nécessiterait l'extraction du rythme de trame d'au moins l'un des deux signaux. Ceci compliquerait singulièrement la méthode de commutation et ne permettrait pas d'améliorer la situation lorsque les trames ne sont pas synchrones.One method of overcoming this drawback could consist in switching frames at a determined point, for example during the preamble, auxiliary data or insignificant bits of the coded samples. However, such a method, comparable to that which is implemented in the video domain where one switches during the suppression of frame, would require the extraction of the frame rate of at least one of the two signals. This would greatly complicate the switching method and would not improve the situation when the frames are not synchronous.

L'invention a pour but un procédé de commutation simple, et qui soit décelable par le récepteur recevant le signal résultant de la commutation. La commutation étant reconnue par le récepteur, celui-ci peut utiliser les méthodes classiques de dissimulation pour masquer cette commutation.The object of the invention is a simple switching method which can be detected by the receiver receiving the signal resulting from the switching. Since the switching is recognized by the receiver, the receiver can use conventional concealment methods to mask this switching.

De manière précise, l'invention a pour objet un procédé de commutation de signaux numériques asynchrones, pour produire un signal résultant par commutation entre un premier signal numérique et un second signal numérique, lesdits premier et second signaux étant composés chacun d'une suite de trames et étant asynchrones, ce procédé étant caractérisé en ce qu'il consiste, lors de la commutation, à introduire dans le signal résultant une séquence caractéristique entre ledit premier signal et ledit second signal.Specifically, the invention relates to a method asynchronous digital signal switching, for producing a resultant signal by switching between a first digital signal and a second digital signal, said first and second signals each being composed of a sequence of frames and being asynchronous, this method being characterized in that it consists, during switching, in introducing into the resulting signal a characteristic sequence between said first signal and said second signal.

Selon un premier mode de réalisation, ladite séquence caractéristique est un signal numérique prédéterminé violant le code utilisé pour représenter les données contenues dans le premier ou le second signal numérique. Ce signal numérique prédéterminé peut notamment être un signal d'horloge.According to a first embodiment, said characteristic sequence is a predetermined digital signal violating the code used to represent the data contained in the first or the second digital signal. This predetermined digital signal can in particular be a clock signal.

Selon un second mode de réalisation, ladite séquence caractéristique consiste en un état permanent.According to a second embodiment, said characteristic sequence consists of a permanent state.

L'invention a également pour objet un dispositif de commutation de signaux numériques asynchrones pour produire un signal résultant par commutation entre un premier signal numérique et un second signal numérique, lesdits premier et second signaux étant composés chacun d'une suite de trames et étant asynchrones, ledit dispositif étant caractérisé en ce qu'il comprend :

  • un multiplexeur comportant une première entrée pour recevoir ledit premier signal numérique, une seconde entrée pour recevoir ledit second signal numérique, et une sortie pour délivrer un signal résultant, ledit multiplexeur comprenant en outre au moins une entrée de commande, et
  • un moyen de commande pour délivrer des signaux de commande sur les entrées de commande du multiplexeur pour commuter ledit multiplexeur de la première entrée à la seconde entrée et pour introduire, pendant cette commutation, une séquence caractéristique sur la sortie du multiplexeur.
The invention also relates to a device for switching asynchronous digital signals to produce a resulting signal by switching between a first digital signal and a second digital signal, said first and second signals each being composed of a sequence of frames and being asynchronous. , said device being characterized in that it comprises:
  • a multiplexer having a first input for receiving said first digital signal, a second input for receiving said second digital signal, and an output for delivering a resulting signal, said multiplexer further comprising at least one control input, and
  • control means for supplying control signals to the control inputs of the multiplexer for switching said multiplexer from the first input to the second input and for introducing, during this switching, a characteristic sequence on the output of the multiplexer.

Selon un premier mode de réalisation, le dispositif comporte en outre un moyen de synthèse d'un signal numérique prédéterminé, et le multiplexeur comporte une troisième entrée recevant ledit signal numérique prédéterminé, le moyen de commande commandant l'émission dudit signal numérique prédéterminé comme séquence caractéristique lors de la commutation.According to a first embodiment, the device further comprises means for synthesizing a predetermined digital signal, and the multiplexer comprises a third input receiving said predetermined digital signal, the control means controlling the transmission of said predetermined digital signal as a characteristic sequence during switching.

De manière préférée, ledit signal numérique prédéterminé est un viol du code utilisé pour le codage des données du premier ou du second signal numérique. En particulier, le moyen d'émission peut être un générateur d'horloge.Preferably, said predetermined digital signal is a violation of the code used for coding the data of the first or second digital signal. In particular, the transmission means can be a clock generator.

Selon un second mode de réalisation, ledit moyen de commande est relié à une entrée de sélection du multiplexeur, ladite séquence caractéristique consistant en un état permanent correspondant à une inhibition du multiplexeur.According to a second embodiment, said control means is connected to an input for selecting the multiplexer, said characteristic sequence consisting of a permanent state corresponding to an inhibition of the multiplexer.

Les caractéristiques et avantages de l'invention ressortiront mieux de la description qui va suivre, donnée à titre illustratif mais non limitatif, en référence aux dessins annexés, sur lesquels :

  • la figure 1, déjà décrite, illustre la structure générale d'un dispositif de commutation spatial,
  • la figure 2, déjà décrite, représente deux signaux numériques asynchrones et le signal résultant de la commutation de ces signaux,
  • la figure 3, déjà décrite, représente deux signaux numériques synchrones, et le signal résultant de la commutation de ce signaux,
  • la figure 4, déjà décrite, montre l'apparition d'une donnée erronée lors de la commutation de deux signaux numériques synchrones,
  • la figure 5 illustre un premier mode de réalisation du dispositif de l'invention, dans lequel la séquence introduite lors de la commutation est un signal d'horloge,
  • la figure 6 illustre un second mode de réalisation de l'invention, dans lequel la séquence introduite lors de la commutation est produite par un état permanent sur la sortie du multiplexeur, et
  • la figure 7 illustre le signal numérique résultant SR produit par le dispositif de l'invention.
The characteristics and advantages of the invention will emerge more clearly from the description which follows, given by way of illustration but not limitation, with reference to the appended drawings, in which:
  • FIG. 1, already described, illustrates the general structure of a spatial switching device,
  • FIG. 2, already described, represents two asynchronous digital signals and the signal resulting from the switching of these signals,
  • FIG. 3, already described, represents two synchronous digital signals, and the signal resulting from the switching of this signals,
  • FIG. 4, already described, shows the appearance of an erroneous datum during the switching of two synchronous digital signals,
  • FIG. 5 illustrates a first embodiment of the device of the invention, in which the sequence introduced during switching is a clock signal,
  • FIG. 6 illustrates a second embodiment of the invention, in which the sequence introduced during switching is produced by a permanent state on the output of the multiplexer, and
  • FIG. 7 illustrates the resulting digital signal SR produced by the device of the invention.

Le dispositif de commutation représenté sur la figure 5 comprend principalement un multiplexeur 2 et un moyen de commande 8. Le dispositif de commutation peut également comprendre des étages d'entrée 4₀, ..., 4₁₅, et un étage de sortie 6 placé respectivement sur les entrées et sur la sortie du multiplexeur 2.The switching device shown in Figure 5 mainly comprises a multiplexer 2 and a control means 8. The switching device can also include input stages 4₀, ..., 4₁₅, and an output stage 6 placed respectively on the inputs and on the output of the multiplexer 2 .

Les entrées du multiplexeur sont reliées à des moyens d'émission de signaux numériques, telles que des interfaces d'équipement de centre de production ou de transmission audiovisuels. Cependant, conformément à l'invention, l'une des entrées du multiplexeur 2 est relié à un moyen d'émission 10 d'un signal numérique prédéterminé, par exemple un générateur de signal d'horloge.The inputs of the multiplexer are connected to means for transmitting digital signals, such as interfaces for production center equipment or audiovisual transmission. However, in accordance with the invention, one of the inputs of the multiplexer 2 is connected to a means 10 for transmitting a predetermined digital signal, for example a clock signal generator.

La sélection des entrées du multiplexeur est réalisée par le moyen de commande 8 par l'intermédiaire d'une voie 12. Dans le mode de réalisation représenté, le multiplexeur 2 comporte 16 entrée Y₀, Y₁, ..., Y₁₅, et par conséquent la voie 12 comporte 4 fils C0-C3.The selection of the inputs of the multiplexer is carried out by the control means 8 via a channel 12. In the embodiment shown, the multiplexer 2 has 16 inputs Y₀, Y₁, ..., Y₁₅, and therefore channel 12 has 4 wires C0-C3.

Ce moyen de commande 8 comprend un microprocesseur 14, un bus de données 16, un registre 18 dont l'entrée de données est reliée au bus de données 16 et la sortie à la voie 12, un bus d'adresse 20, et un décodeur d'adresse 22 dont l'entrée est reliée au bus d'adresse 20 et dont une sortie est reliée à une entrée de sélection CS du registre 18.This control means 8 comprises a microprocessor 14, a data bus 16, a register 18 whose data input is connected to the data bus 16 and the output to channel 12, an address bus 20, and a decoder with address 22, the input of which is connected to the address bus 20 and the output of which is connected to a selection input CS of the register 18.

Le registre 18 est utilisé pour mémoriser une donnée correspondant à la sélection d'une entrée du multiplexeur 2, et le décodeur d'adresse 22 permet de charger le contenu du registre à partir du bus de données du microprocesseur.The register 18 is used to store data corresponding to the selection of an input of the multiplexer 2, and the address decoder 22 makes it possible to load the content of the register from the data bus of the microprocessor.

Le procédé de commutation mis en oeuvre par le dispositif représenté sur la figure 5 pour la commutation d'un signal S1 appliqué sur l'entrée Yi du multiplexeur à un signal S2 appliqué sur l'entrée Yj du multiplexeur est le suivant. Dans un premier temps le microprocesseur 14 délivre vers le registre 18 une donnée correspondant à la sélection de l'entrée Y₁₅ du multiplexeur pour que le signal numérique prédéterminé par le moyen d'émission 10 remplace le signal S1 sur la sortie du multiplexeur. Dans un second temps, le microprocesseur 14 délivre vers le regitre 18 une donnée correspondant à la sélection de l'entrée Yj du multiplexeur.The switching method implemented by the device shown in FIG. 5 for switching from a signal S1 applied to the input Y i of the multiplexer to a signal S2 applied to the input Y j of the multiplexer is as follows. Firstly, the microprocessor 14 delivers to the register 18 data corresponding to the selection of the input Y₁₅ of the multiplexer so that the digital signal predetermined by the transmission means 10 replaces the signal S1 on the output of the multiplexer. In a second step, the microprocessor 14 delivers to the register 18 a data item corresponding to the selection of the input Y j of the multiplexer.

Le signal numérique prédéterminé délivré par le moyen d'émission 10 peut être constitué par exemple par l'émission en permanence du préambule des trames des signaux numériques S1 et S2, ou de tout autre signal violant les règles de codage utilisé pour le codage des échantillons. Dans le cas où les signaux sont émis par l'interface de studio UER/AES, évoqué au début de la description, le moyen d'émission 10 peut émettre par exemple un signal d'horloge à 1024 kilohertz, l'intervalle entre transition correspondant alors à 1,5 fois la durée d'un bit, ce qui viole les règles du codage utilisé.The predetermined digital signal delivered by the transmission means 10 can be constituted for example by the permanent transmission of the preamble of the frames of the digital signals S1 and S2, or of any other signal violating the coding rules used for the coding of the samples . In the case where the signals are transmitted by the EBU / AES studio interface, mentioned at the beginning of the description, the transmission means 10 can for example transmit a clock signal at 1024 kilohertz, the interval between corresponding transitions then at 1.5 times the duration of a bit, which violates the rules of the coding used.

On a représenté sur la figure 6 un second mode de réalisation du dispositif de commutation de l'invention. Sur cette figure, les éléments identiques à ceux de la figure 5 portent la même référence. La différence essentielle avec le dispositif de la figure 5 réside en ce qu'il n'est pas prévu un moyen d'émission d'un signal particulier relié à l'une des entrées de données du multiplexeur, mais en ce que la séquence caractéristique introduite au moment de la commutation est un état logique permanent résultant d'une impulsion de commande appliquée sur l'entrée de sélection CS du multiplexeur 2.FIG. 6 shows a second embodiment of the switching device of the invention. In this figure, the elements identical to those of Figure 5 have the same reference. The essential difference with the device of FIG. 5 resides in that there is not provided a means of transmitting a particular signal connected to one of the data inputs of the multiplexer, but in that the characteristic sequence entered at the time of switching is a permanent logic state resulting from a control pulse applied to the selection input CS of multiplexer 2.

Dans ce mode de réalisation, le signal délivré par le décodeur d'adresse 22 pour sélectionner le registre 18 est appliqué également sur l'entrée de sélection du multiplexeur 2, pour déselectionner le multiplixeur et forcer ainsi sa sortie dans un état déterminé. Le signal appliqué sur l'entrée de sélection du multiplexeur 2 a une durée au moins égale à 1,5 fois la durée d'un bit. La durée de cette impulsion peut être obtenue par tout moyen approprié, comme par exemple une gestion adéquate de la ligne d'acquittement ACK du décodeur d'adresse 22.In this embodiment, the signal delivered by the address decoder 22 to select the register 18 is also applied to the selection input of the multiplexer 2, to deselect the multiplixer and thus force its output into a determined state. The signal applied to the selection input of multiplexer 2 has a duration at least equal to 1.5 times the duration of a bit. The duration of this pulse can be obtained by any suitable means, such as for example an adequate management of the acknowledgment line ACK of the address decoder 22.

On a représenté sur la figure 7 le signal résultant SR produit par la commutation de deux signaux numériques S1 et S2, selon l'invention. Ce signal SR comporte une séquence particulière SP insérée entre le signal numérique S1 et le signal numérique S2. Ce signal est reçu par un récepteur, qui peut être inclus dans l'interface de studio UER/AES, et qui est conçu de manière classique pour détecter de façon appropriée les erreurs de transmission et/ou les viols du code, et donc en particulier la séquence SP, et pour assurer un traitement approprié des données reçues.FIG. 7 shows the resulting signal SR produced by the switching of two digital signals S1 and S2, according to the invention. This SR signal has a sequence particular SP inserted between the digital signal S1 and the digital signal S2. This signal is received by a receiver, which can be included in the EBU / AES studio interface, and which is conventionally designed to appropriately detect transmission errors and / or code breaches, and therefore in particular the SP sequence, and to ensure appropriate processing of the data received.

Claims (10)

1. Process for switching digital signals which are to be transmitted to receivers equipped with error masking and detection devise, the process making it possible to produce a resultant signal (SR) by switching between a first digital signal (S1) and a second digital signal (S2), said first and second signals being in each case transmitted in serial form by means of frames, said process being characterized in that it comprises, during switching, introducing into the resultant signal a characteristic sequence (SP) between said first signal and said second signal for activating the masking error and detection devices of the dowstream receivers, so that the receivers do not exploit the incoherent data in the vicinity of the switching.
2. Switching process according to claim 1, characterized in that said characteristic sequence is a characteristic digital signal breaking the code used for representing the data contained in the first and second digital signals.
3. Process according to claim 2, characterized in that the characteristic digital signal is a clock signal.
4. Process according to claim 2, characterized in that the characteristic sequence consists of a permanent state.
5. Device for switching digital signals, which are to be transmitted to receivers equipped with detection and error masking devices, said device making it possible to produce a resultant signal by switching between a first digital signal and a second digital signal, said first and second signals being in each case transmitted in serial first by means of frames, said device being characterized in that it comprises
- a multiplexer (2) having a first first for receiving said first digital signal, a second input for receiving said second digital signal and an output for supplying a resultant digital signal, said multiplexer also having at least one control input and
- a control means (8) for supplying control signals to the control inputs of the multiplexer for switching said multiplexer from the first input to the second and for introducing, during said switching, a chacteristic sequence on the output of the multiplexer for activating the masking error and detection devices of the dowstream receivers, so that the receivers do not exploit the incoherent data in the vicinity of the switching.
6. Switching device according to claim 5, characterized in that said characteristic sequence breaks the code used for encoding the data of the first or second digital signal.
7. Device according to either of the claims 4 and 5, characterized in that it also has a transmission means (10) of a characteristic digital signal, the multiplexer incorporating a third input receiving said characteristic digital signal and the control means (8) controlling the transmission of said characteristic digital signal as the characteristic sequence during switching.
8. Switching device according to claim 7, characterized in that the transmission means (10) is a clock generator.
9. Switching device according to either of the claims 4 and 5, characterized in that said predetermined sequence consists of a corresponding permanent state.
10. Switching device according to claim 9, characterized in that said control means (8) is connected to a detection input (CS) of the multiplexer (2), said permanent state being obtained by the inhibition of said multiplexer.
EP88400857A 1987-04-10 1988-04-08 Method for switching asyschronous digital signals, and device for carrying out this method Expired - Lifetime EP0288353B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR8705135 1987-04-10
FR8705135A FR2613893B1 (en) 1987-04-10 1987-04-10 METHOD FOR SWITCHING ASYNCHRONOUS DIGITAL SIGNALS, AND DEVICE FOR CARRYING OUT SAID METHOD

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EP0288353A1 EP0288353A1 (en) 1988-10-26
EP0288353B1 true EP0288353B1 (en) 1992-02-19

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Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5182467A (en) * 1991-08-22 1993-01-26 Triquint Semiconductor, Inc. High performance multiplexer for improving bit error rate
US5157348A (en) * 1991-10-15 1992-10-20 The United States Of America As Represented By The Secretary Of The Navy Smart programmable gain amplifier
US5299196A (en) * 1992-11-12 1994-03-29 International Business Machines Corporation Distributed address decoding for bus structures
JP2906361B2 (en) * 1993-09-01 1999-06-21 富士通株式会社 Multiplex control method
US5615126A (en) * 1994-08-24 1997-03-25 Lsi Logic Corporation High-speed internal interconnection technique for integrated circuits that reduces the number of signal lines through multiplexing
GB2499699A (en) 2011-12-14 2013-08-28 Wolfson Ltd Digital data transmission involving the position of and duration of data pulses within transfer periods

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3598922A (en) * 1967-08-02 1971-08-10 Honeywell Inc Multiplexer control apparatus
US3832690A (en) * 1972-02-22 1974-08-27 Coaxial Scient Corp Communications system encoder-decoder for data transmission and retrieval
FR2313827A1 (en) * 1975-06-02 1976-12-31 Materiel Telephonique Binary elements train transmission system - has simple means of synchronising receiver timer, this timer having multiphase circuit
US4017687A (en) * 1975-11-28 1977-04-12 The United States Of America As Represented By The Secretary Of The Navy Device for minimizing interchannel crosstalk in high rate commutator multiplexers
US4325147A (en) * 1980-06-16 1982-04-13 Minnesota Mining & Manufacturing Co. Asynchronous multiplex system
US4471481A (en) * 1981-02-11 1984-09-11 The Boeing Company Autonomous terminal data communications system
GB2140248B (en) * 1983-04-22 1985-11-20 Soundout Lab Electrical signal mixing apparatus
JPS60199247A (en) * 1984-03-23 1985-10-08 Nitsuko Ltd Synchronizing system of frame
US4773068A (en) * 1984-04-03 1988-09-20 Tie/Communications, Inc. Dual channel transmission method and apparatus with inherent channel identification and extraction
US4680750A (en) * 1984-10-01 1987-07-14 Lynch Communication Systems, Inc. Universal high-speed span line switch
US4675905A (en) * 1985-04-12 1987-06-23 Ampex Corporation Multiple input silent audio switch
DD250648A3 (en) * 1985-07-17 1987-10-21 Deutsche Post Rfz CIRCUIT ARRANGEMENT FOR TROUBLE-FREE SWITCHING OF DIGITAL SOUND SIGNALS

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US4939729A (en) 1990-07-03
FR2613893A1 (en) 1988-10-14
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EP0288353A1 (en) 1988-10-26
DE3868428D1 (en) 1992-03-26

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