EP0186866A2 - Majoritätsschaltung - Google Patents

Majoritätsschaltung Download PDF

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Publication number
EP0186866A2
EP0186866A2 EP85116266A EP85116266A EP0186866A2 EP 0186866 A2 EP0186866 A2 EP 0186866A2 EP 85116266 A EP85116266 A EP 85116266A EP 85116266 A EP85116266 A EP 85116266A EP 0186866 A2 EP0186866 A2 EP 0186866A2
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EP
European Patent Office
Prior art keywords
majority
circuit
output
input
level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP85116266A
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English (en)
French (fr)
Other versions
EP0186866B1 (de
EP0186866A3 (en
Inventor
Seigo C/O Patent Division Suzuki
Yukihiko Yabe
Masumi C/O Patent Division Kawakami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
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Toshiba Corp
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Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of EP0186866A2 publication Critical patent/EP0186866A2/de
Publication of EP0186866A3 publication Critical patent/EP0186866A3/en
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Publication of EP0186866B1 publication Critical patent/EP0186866B1/de
Expired legal-status Critical Current

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H03K19/23—Majority or minority circuits, i.e. giving output having the state of the majority or the minority of the inputs

Definitions

  • the present invention relates to a majority circuit to determine a majority of the level of a digital signal of a plurality of serial bits.
  • majority circuits to determine a majority of the level (“1" level or "0" level) of a digital signal of a plurality of serial bits are widely used.
  • Fig. 1 shows an example of conventional majority circuits.
  • the majority circuit receives a serial digital signal Di n of three bits and determines a majority logic of the signal.
  • the majority circuit comprises one-bit shift registers 1 to 3 which are cascade connected and a gate circuit 4.
  • Gate circuit 4 comprises NAND gates 5 to 8.
  • Three-bit input serial data D in is inputted shift register 1 of the first stage.
  • Each of shift registers 1 to 3 shifts the input data by one bit synchronously with a clock signal.
  • Output signals of shift registers 1 to 3 are inputted to NAND gates 5 to 7 in gate circuit 4.
  • Output signals of NAND gates 5 to 7 are inputted to NAND gate 8 and an output signal of NAND gate 8 becomes a majority output D ou t.
  • the one-bit shift registers equal to the number of input serial bits are cascade connected to constitute a counter circuit, the input serial bits are converted to parallel bits, and the parallel bit data is inputted to gate circuit 4, thereby obtaining a majority output.
  • Fig. 1 requires the 1-bit shift registers equal to the number of input bits. Therefore, as the number "n" of input bits increases, the number of shift registers required also increases. Further, the number of NAND gates constituting gate circuit 4 also increases.
  • a majority circuit for seven input bits constituted using the circuit arrangement shown in Fig. 1 has a circuit arrangement as shown in Fig. 2.
  • seven shift registers 11 to 17 are needed as shift registers constituting a counter circuit
  • thirty-five 4-input NAND gates 19 and one 35-input NAND gate 20 are needed as gate logic elements constituting a gate circuit.
  • the number of logic elements required remarkably increases with an increase in number of input bits.
  • the wirings among those elements also become complicated in association with the increase in number of elements. Consequently, there is a problem such that the size of the required chip enlarges.
  • the present invention is made in consideration of the above-mentioned circumstances and it is an object of the invention to provide a majority circuit in which a circuit arrangement is simple and the chip size is reduced due to such a simple arrangement.
  • a majority circuit comprising an input terminal to which an odd number of serial data of n bits are inputted, a counter circuit of a (n+1)/2 notation of a plurality of cascade connected binary counters for counting the serial data inputted to said input terminal, and an output terminal at which an output of said binary counter of the last stage of said counter circuit is taken out as a majority output of said serial data.
  • the majority circuit shown in Fig. 3 comprises a quaternary counter circuit comprising three binary counters 31 to 33 which are cascade connected.
  • An input of binary counter 31 of the first stage is connected to an input terminal 35 of the majority circuit.
  • Input data Di n is inputted to input terminal 35.
  • An output terminal of binary counter 33 of the last stage is connected to an output terminal 34 of the majority circuit.
  • Majority output D out is taken out from the output terminal 34.
  • Reset terminals R of binary counters 31 to 33 are connected to a reset terminal 36, respectively.
  • a reset signal RS is inputted to the reset terminal 36.
  • reset signal RS of a "1" level is first inputted to input terminal 36, so that binary counters 31 to 33 are respectively reset and outputs of binary counters 31 to 33 become a "0" level (i.e., 0, 0, 0), respectively.
  • serial data Di n whose majority is to be determined is inputted.
  • Fig. 4 it is now assumed that three bits of the fourth, sixth, and seventh bits of input serial data Di n are at a "0" level and other four bits are at a "1" level. The majority logic of the serial data Di n is at a "1" level.
  • Majority output D out of the majority circuit of Fig. 3 is the output of binary counter 33, so that majority output D ou t of serial data D in becomes a "1" level.
  • serial data Di n shown in Fig. 5 was inputted will then be considered.
  • reset signal RS of a "1" level is inputted to input terminal 36.
  • binary counters 31 to 33 are respectively reset and the outputs of binary counters 31 to 33 are set to a "0" level, respectively.
  • serial data Di n of Fig. 5 whose majority is to be determined is inputted.
  • three bits of the second, fourth, and sixth bits of serial data Di n are at a "1" level and other four bits are at a "0" level.
  • the majority logic of the serial data Di n becomes a "0" level.
  • Fig. 6 shows a majority circuit for the input serial data of fifteen bits.
  • binary counter 37 is added to the circuit of Fig. 3.
  • the majority circuit shown in Fig. 6 comprises a modulo (or notation) 7 counter circuit four binary counters 31 to 33 and 37 which are cascade connected.
  • An input of binary counter 31 of the first stage is connected to an input terminal 35 of the majority circuit.
  • Input data D in is inputted to input terminal 35.
  • An output terminal of binary counter 37 of the last stage is connected to an output terminal 34 of the majority circuit.
  • Majority output D out is taken out from the output terminal 34.
  • Reset terminals R of binary counters 31 to 33 and 37 are connected to a reset terminal 36, respectively.
  • a reset signal RS is inputted to the reset terminal 36.
  • reset signal RS of a "1" level is first inputted to input terminal 36, so that binary counters 31 to 33 and 37 are respectively reset and outputs of binary counters 31 to 33 and 37 become a "0" level (i.e., 0, 0, 0, 0), respectively.
  • serial data 'Di n whose majority is to be determined is inputted. It is now assumed that seven those of the fifteen bits of input serial data Di n are at a "0" level and other four bits are at a "1" level. The majority logic of the serial data D in is at a "1" level.
  • Majority output D out of the majority circuit of Fig. 6 is the output of binary counter 37, so that majority output D out of serial data D in becomes a "1" level.
  • Fig. 7 shows a practical arrangement of binary counter 31 in the majority circuits of Figs. 3 and 6.
  • the arrangements of the other binary counters are also substantially the same as that of binary counter 31.
  • An output signal S4 of clocked inverter 44 and reset signal RS are inputted to a two-input NOR gate 45.
  • An input terminal of a clocked inverter 46 is connected to an output terminal of NOR gate 45 and an output terminal of inverter 46 is connected to an output terminal of clocked inverter 44.
  • Clocked inverter 46 is controlled by a clock signal and operates for the period of time when clock signal (Fig. 8(a)) is at a "1" level.
  • An output signal S5 of NOR gate 45 is inputted to a clocked inverter 47.
  • Clocked inverter 47 is also controlled by clock signal and operates for the period of time when clock signal ⁇ is at a "1" level.
  • An output signal S6 of clocked inverter 47 and reset signal RS are inputted to a two-input NOR gate 48.
  • An input terminal of a clocked inverter 49 is connected to an output terminal of NOR gate 48 and an output terminal of inverter 49 is connected to an output terminal of clocked inverter 47.
  • Clocked inverter 49 is controlled by clock signal and operates for the period of time when clock signal ⁇ is at a "1" level.
  • An output signal S7 of NOR gate 48 is inputted to the other input terminals of AND gate 41 and NOR gate 42.
  • Output signal S7 of NOR gate 48 constitutes majority output OUT1 in the case where binary counter 31 is considered to be the counter of the last stage.
  • Clocked inverter 44, NOR gate 45, and clocked inverter 46 constitute a half-bit shift circuit 51 to shift output signal S3 of NOR gate 43 by a half bit of clock signal ⁇ .
  • Clocked inverter 47, NOR gate 48, and clocked inverter 49 constitute a half-bit shift circuit 52 to shift output signal S5 of half-bit shift circuit 51 by half bit of clock signal T.
  • Half-bit shift circuits 51 and 52 constitute a one-bit shift circuit.
  • reset signal RS is first set at a "1" level, so that the output signals of NOR gates 45 and 48, namely, output signals S5 and S7 of half-bit shift circuits 51 and 52 become a "0" level.
  • output signals OUT1 (Fig. 8(e)) and OUT2 (Fig. 8 (d)) are set at a "0" level irrespective of input signal D in (Fig. 8(c)).
  • reset signal RS is set at a "0" level.
  • output signal OUT2 becomes a signal as shown in Fig. 8D which changes in response to the leading edge of clock signal ⁇ .
  • the majority circuits shown in Figs. 3 and 6 intend to determine the majority logics of the serial data of seven bits and fifteen bits, respectively.
  • the majority circuits shown in Figs. 3 and 6 fundamentally intend to determine the majority logics for the serial data of (2 k- ,) bits, for example, three, seven, fifteen, ... bits, but cannot determine the majority logic of a serial data of bits of the number other than (2 k- ,), e.g., the serial data of five bits.
  • Fig. 9 is a diagram according to another embodiment of the present invention to obtain a majority output of the serial data of five bits. A different point of the embodiment of Fig. 9 from the embodiment of Fig.
  • binary counter 31 with reset terminals R is replaced by a binary counter 38 with a set terminal S. Further, an inverter 39 is provided between reset terminal 36 and set terminal S of binary counter 38. Reset signal RS is inputted to set terminal S of binary counter 38 through inverter 39.
  • Fig. 10 shows a detailed circuit arrangement of binary counter 38 in the majority circuit of Fig. 9.
  • Binary counter 38 of Fig. 10 uses NAND gates 65 and 68 in place of NOR gates 45 and 48 in the binary counter shown in Fig. 7.
  • An output signal S4 of clocked inverter 44 and reset signal RS are inputted to a two-input NAND gate 65.
  • An input terminal of a clocked inverter 46 is connected to an output terminal of NAND gate 65 and an output terminal of inverter 46 is connected to an output terminal of clocked inverter 44.
  • Clocked inverter 46 is controlled by a clock signal and operates for the period of time when clock signal (Fig. 8(a)) is at a "1" level.
  • An output signal S5 of NAND gate 65 is inputted to a clocked inverter 47.
  • Clocked inverter 47 is also controlled by clock signal and operates for the period of time when clock signal is at a "1" level.
  • An output signal S 6 of clocked inverter 47 and reset signal RS are inputted to a two-input NAND gate 68.
  • An input terminal of a clocked inverter 49 is connected to an output terminal of NAND gate 68 and an output terminal of inverter 49 is connected to an output terminal of clocked inverter 47.
  • Clocked inverter 49 is controlled by clock signal ⁇ and operates for the period of time when clock signal ⁇ is at a "1" level.
  • An output signal S7 of NAND gate 68 is inputted to the other input terminals of AND gate 41 and NOR gate 42.
  • Output signal S7 of NAND gate 68 constitutes majority output OUT I in the case where binary counter 38 is considered to be the counter 33 of the last stage.
  • Clocked inverter 44, NAND gate 65, and clocked inverter 46 constitute a half-bit shift circuit 51 to shift output signal S3 of NOR gate 43 by a half bit of clock signal ⁇ .
  • Clocked inverter 47, NAND gate 68, and clocked inverter 49 constitute a half-bit shift circuit 52 to shift output signal S5 of half-bit shift circuit 51 by half bit of clock signal ⁇ .
  • Half-bit shift circuits 51 and 52 constitute a one-bit shift circuit.
  • the embodiment of Fig. 9 is used for a 5-bit input.
  • the majority circuit which can determine a majority output of other input data of bits of an odd number other than (2 k -1).
  • the majority circuit for a 13-bit input can be provided by replacing binary counter 31 of the first stage in the majority circuit of Fig. 6 by a binary counter with the set function.
  • Fig. 11 shows a majority circuit of a still another embodiment according to the invention.
  • the majority circuit of Fig. 11 is intended for seven input serial bits.
  • the majority circuit comprises three binary counters 61, 62 and 63 cascade connected.
  • Binary counters 61 to 63 have reset terminal R.
  • Reset signal RS is inputted to reset terminals RS of binary counters 61 to 63.
  • Input serial seven bits are inputted to binary counters 61 to 63.
  • input serial bits are used as clock signals ⁇ , ⁇ .
  • Input terminal IN of binary counter 61 at the first stage is connected to a predetermined carry signal.
  • Input terminals IN of binary counters 62, 63 are connected to output signals (carry signal) OUT1 of binary counters 61 and 62, respectively.
  • Fig. 12 shows a detailed circuit of binary counter 61.
  • the circuit of Fig. 12 is different from the circuit of Fig. 7 is that clocked inverters 44 and 49 are controlled, not by clock pulse T, but by phase inverted input serial bits signal D in .
  • clock inverter 46 and 47 are controlled, not by clock pulse ⁇ , but by input serial bits signal D in .
  • Clocked inverters 44 and 49 operate when phase inverted bits signal D in is at a "1" level.
  • Clocked inverters 46 and 47 operate when bits signal Di n is at a "1" level.
  • Others are substantially the same as those in the circuit as shown in Fig. 7.
  • Figs. 13(a) to 13(f) show time charts of signals at the respective portions of the circuit of Fig. 11 appearing when input signal Di n have four "1" level bits, as shown in Fig. 13(a).
  • Reference letters A, B, C, D and E are commonly used in Fig. 11 and Figs. 13(b) to 13(f).
  • majority output E has "1" level, when the fourth bit of "1" level is inputted.
  • Figs. 14(a) to 14(f) show time charts of signals at the respective portions of the circuit of Fig. 11 appearing when input signal D in have three "1" level bits, as shown in Fig. 14(a).
  • Reference letters A, B, C, D and E are commonly used in Fig. 11 and Figs. 14(b) to 14(f).
  • majority output E has "1" level.
  • k binary counters 2 k- 1 are cascade connected to form a modulo (n+1)/2 counter circuit and an output signal of the counter of the last stage is taken out as majority signal D out .

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
EP85116266A 1984-12-26 1985-12-19 Majoritätsschaltung Expired EP0186866B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP59273422A JPS61154221A (ja) 1984-12-26 1984-12-26 多数決回路
JP273422/84 1984-12-26

Publications (3)

Publication Number Publication Date
EP0186866A2 true EP0186866A2 (de) 1986-07-09
EP0186866A3 EP0186866A3 (en) 1988-01-27
EP0186866B1 EP0186866B1 (de) 1991-11-21

Family

ID=17527674

Family Applications (1)

Application Number Title Priority Date Filing Date
EP85116266A Expired EP0186866B1 (de) 1984-12-26 1985-12-19 Majoritätsschaltung

Country Status (4)

Country Link
US (1) US4692640A (de)
EP (1) EP0186866B1 (de)
JP (1) JPS61154221A (de)
DE (1) DE3584720D1 (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102004036546A1 (de) * 2004-07-28 2006-03-23 Infineon Technologies Ag Integrierter Halbleiterspeicher

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5299356A (en) * 1993-04-12 1994-04-05 Maxwell Iii Ralph Diet eating utensil
JPH10214314A (ja) * 1997-01-30 1998-08-11 Toshiba Corp Ｉｃカード用携帯端末装置およびその制御方法
FR2797120B1 (fr) * 1999-07-30 2001-09-14 St Microelectronics Sa Minuterie numerique a declenchement rapide
US7236005B1 (en) * 2005-02-09 2007-06-26 Intel Corporation Majority voter circuit design
US7129742B1 (en) 2005-02-23 2006-10-31 The United States Of America As Represented By The National Security Agency Majority logic circuit
US8867695B2 (en) * 2013-01-25 2014-10-21 Apple Inc. Clock signal rate management circuit

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3225332A (en) * 1961-02-03 1965-12-21 Cutler Hammer Inc Data accumulation systems
JPS55115732A (en) * 1979-02-28 1980-09-05 Nec Corp Logic circuit of decision by majority
EP0107236A1 (de) * 1982-10-11 1984-05-02 Koninklijke Philips Electronics N.V. Mehrfachredundantes Taktsystem eine Anzahl von gegenseitig synchronisierenden Takten enthaltend, und Taktschaltung zum Gebrauch in einem solchen Taktsystem
US4484330A (en) * 1982-03-08 1984-11-20 At&T Bell Laboratories Majority vote circuit

Family Cites Families (5)

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Publication number Priority date Publication date Assignee Title
US4027175A (en) * 1973-09-20 1977-05-31 National Research Development Corporation Threshold logic gates
US4091293A (en) * 1975-12-30 1978-05-23 Fujitsu Limited Majority decision logic circuit
US4158767A (en) * 1978-04-24 1979-06-19 Avco Corporation Programmable binary counter
US4375683A (en) * 1980-11-12 1983-03-01 August Systems Fault tolerant computational system and voter circuit
US4394769A (en) * 1981-06-15 1983-07-19 Hughes Aircraft Company Dual modulus counter having non-inverting feedback

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3225332A (en) * 1961-02-03 1965-12-21 Cutler Hammer Inc Data accumulation systems
JPS55115732A (en) * 1979-02-28 1980-09-05 Nec Corp Logic circuit of decision by majority
US4484330A (en) * 1982-03-08 1984-11-20 At&T Bell Laboratories Majority vote circuit
EP0107236A1 (de) * 1982-10-11 1984-05-02 Koninklijke Philips Electronics N.V. Mehrfachredundantes Taktsystem eine Anzahl von gegenseitig synchronisierenden Takten enthaltend, und Taktschaltung zum Gebrauch in einem solchen Taktsystem

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN, vol. 4, no. 170 (E-35)[652], 22nd November 1980; & JP-A-55 115 732 (NIPPON DENKI K.K.) 05-09-1980 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102004036546A1 (de) * 2004-07-28 2006-03-23 Infineon Technologies Ag Integrierter Halbleiterspeicher

Also Published As

Publication number Publication date
JPS61154221A (ja) 1986-07-12
EP0186866B1 (de) 1991-11-21
DE3584720D1 (de) 1992-01-02
US4692640A (en) 1987-09-08
JPH0247135B2 (de) 1990-10-18
EP0186866A3 (en) 1988-01-27

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