EP0181007A3 - Bus broadcast method and apparatus - Google Patents

Bus broadcast method and apparatus Download PDF

Info

Publication number
EP0181007A3
EP0181007A3 EP85114271A EP85114271A EP0181007A3 EP 0181007 A3 EP0181007 A3 EP 0181007A3 EP 85114271 A EP85114271 A EP 85114271A EP 85114271 A EP85114271 A EP 85114271A EP 0181007 A3 EP0181007 A3 EP 0181007A3
Authority
EP
European Patent Office
Prior art keywords
receiver
broadcast
circuitry
data
bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP85114271A
Other languages
German (de)
French (fr)
Other versions
EP0181007A2 (en
Inventor
Jeffrey S. Gilbert
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Spacelabs Medical Inc
Original Assignee
Spacelabs Medical Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Spacelabs Medical Inc filed Critical Spacelabs Medical Inc
Publication of EP0181007A2 publication Critical patent/EP0181007A2/en
Publication of EP0181007A3 publication Critical patent/EP0181007A3/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/161—Computing infrastructure, e.g. computer clusters, blade chassis or hardware partitioning

Abstract

A broadcast channel capability is added to a multip­ rocessing combined bus implementation. A transmitter channel portion includes means for continually locking out other combined bus coupled modules from control of the combined bus until the data broadcast is complete. Circuitry is also provided for generating a delayed local broadcast acknowledge since the receiver modules will not generate a normal acknowledge signal due to unique decoding of the receiver circuitry. Receiver circuitry includes data latches into which data words transmitted during the broadcast are sequentially launched. The data latches are coupled to the receiver's CPU data bus. Circuitry is provided for signalling the receiver's CPU when the transfer is complete.
EP85114271A 1984-11-09 1985-11-08 Bus broadcast method and apparatus Withdrawn EP0181007A3 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US67019784A 1984-11-09 1984-11-09
US670197 1984-11-09

Publications (2)

Publication Number Publication Date
EP0181007A2 EP0181007A2 (en) 1986-05-14
EP0181007A3 true EP0181007A3 (en) 1988-05-18

Family

ID=24689410

Family Applications (1)

Application Number Title Priority Date Filing Date
EP85114271A Withdrawn EP0181007A3 (en) 1984-11-09 1985-11-08 Bus broadcast method and apparatus

Country Status (5)

Country Link
EP (1) EP0181007A3 (en)
JP (1) JPS61121150A (en)
CN (1) CN85108393A (en)
AU (1) AU4907285A (en)
ZA (1) ZA858310B (en)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3706734C1 (en) * 1987-03-02 1988-03-17 Force Computers Gmbh Process for the transmission of data and computers
US4837735A (en) * 1987-06-09 1989-06-06 Martin Marietta Energy Systems, Inc. Parallel machine architecture for production rule systems
JPH02503121A (en) * 1987-10-06 1990-09-27 ベル、コミュニケーションズ、リサーチ、インコーポレーテッド Selective receiver for each processor in a multiple processor system
GB8814629D0 (en) * 1987-11-12 1988-07-27 Ibm Direct control facility for multiprocessor network
IT1223142B (en) * 1987-11-17 1990-09-12 Honeywell Bull Spa MULTIPROCESSOR PROCESSING SYSTEM WITH MULTIPLATION OF GLOBAL DATA
US4998245A (en) * 1987-12-17 1991-03-05 Matsushita Electric Industrial Co., Ltd. Information transmission system having collective data transmission and collection devices
GB9012970D0 (en) * 1989-09-22 1990-08-01 Ibm Apparatus and method for asynchronously delivering control elements with pipe interface
CA2021826A1 (en) * 1989-10-23 1991-04-24 Darryl Edmond Judice Delay logic for preventing cpu lockout from bus ownership
IT1239596B (en) * 1990-02-16 1993-11-10 Sincon Spa Sistemi Imformativi CONNECTION NETWORK FOR DATA MANAGEMENT IN PARALLEL PROCESSING.
EP0537899B1 (en) * 1991-09-27 1999-12-15 Sun Microsystems, Inc. Bus arbitration architecture incorporating deadlock detection and masking

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5831637A (en) * 1981-08-20 1983-02-24 Nec Corp Multiplex processor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5831637A (en) * 1981-08-20 1983-02-24 Nec Corp Multiplex processor

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
E.D.N. ELECTRICAL DESIGN NEWS, vol. 29, no. 16, August 1984, pages 199-206, Boston, Massachusetts, US; R. KALISH et al.: "Consider using the S-100 bus to host your 16-bit muP" *
PATENT ABSTRACTS OF JAPAN, vol. 7, no. 111 (E-175)[1256], 14th May 1983; & JP-A-58 31 637 (NIPPON DENKI K.K.) 24-02-1983 *
WESCON/79 CONFERENCE RECORD, San Francisco, CA, 18th-20th September 1979, paper 28/1, pages 1-6, Electronic Conventions, Inc. North Hollywood, US; LES SOLTESZ: "Multiprocessing with single board computers - hardware considerations" *

Also Published As

Publication number Publication date
CN85108393A (en) 1986-08-27
AU4907285A (en) 1986-05-15
ZA858310B (en) 1986-06-25
EP0181007A2 (en) 1986-05-14
JPS61121150A (en) 1986-06-09

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Inventor name: GILBERT, JEFFREY S.