EP0162943B1 - Integrated circuit for decoding traffic radio announcement identification signals - Google Patents

Description

The invention relates to an integrated circuit for decoding traffic announcement signals whose frequency, the announcement frequency, is the information for a traffic announcement and which are contained in the form of a carrier signal amplitude-modulated therewith in a broadcast signal received and already demodulated with a conventional radio receiver, cf. the preamble of claim 1.

In the magazine "Funkschau", 1974, pages 535 to 538, the system for transmitting traffic announcements to radio listeners, which was introduced in Germany at the time and is now used in other countries, is described, with what is known as an announcement identifier being transmitted during a traffic announcement. In addition to this, area identification signals are also sent. The characteristic signals are quite low-frequency and are modulated onto the carrier signal, which has a frequency of 57 kHz in the known system, by means of amplitude modulation and are derived from the carrier signal by integer frequency division.

As can be seen from the magazine "Rundfunktchnic Mitteilungen", 1974, pages 193 to 202, in which this traffic radio system is also described in detail, the system parameters were selected in such a way that the receiver-side decoder circuits required for traffic radio with the usual receiver circuits processing analog signals are compatible and in particular no mutual interference occurs. The previously common decoder circuits are therefore also analog circuits.

In contrast, it is an object of the invention characterized in the claim to provide an integrated circuit for decoding traffic announcement signals, which works according to the principles of digital technology and is thus largely constructed from digital subcircuits. The response time of the circuit should be less than one second, e.g. 800 ms, and the announcement detection should be insensitive to noise.

In the own older European application EP-A-0119280, published on September 26, 1984, an integrated circuit for decoding traffic area code signals is described, which is based on a task modified for this purpose and comparable to the invention. The invention makes use of a few subcircuits of the older arrangement in order to achieve the object set for it, but the overall arrangement according to the invention is obviously different from that of the older application, which is evident from the different purpose. Such an integrable circuit arrangement is also described in DE-A 1-3 233 829, in which - in contrast to the solution according to the invention - the switching information contained in the amplitude modulation is obtained by comparing a digitally generated synthetic signal with the input signal.

• Fig. 1 zeigt in Form eines Blockschaltbilds den Aufbau eines Ausführungsbeispiels der Erfindung,
• Fig. 2 zeigt schematisch die Resonanzkurven der bei der Erfindung verwendeten Resonanzfilter, und
• Fig. 3 zeigt schematisch die Lage der Resonanzkurven nach Fig. 2 für den Fall, dass zwei Durchsage-Kennsignale zu verarbeiten sind.

The invention and its advantages will now be explained in more detail with reference to the figures of the drawing.

• 1 shows in the form of a block diagram the structure of an embodiment of the invention,
• Fig. 2 shows schematically the resonance curves of the resonance filters used in the invention, and
• FIG. 3 schematically shows the position of the resonance curves according to FIG. 2 in the event that two announcement identification signals are to be processed.

1 shows the block diagram of an integrated circuit for decoding traffic announcement identification signals according to the invention. For further demodulation and analog-digital conversion, the demodulated radio signal ds, which is obtained by means of a conventional radio receiver, is fed to the mixer stage ms, whose mixed signal frequency fm is greater than the sum of the announcement frequency fa and its carrier frequency. In relation to the system described in the two journals mentioned at the beginning, this means that the mixed signal frequency should be greater than 57.125 kHz. By means of the mixer stage ms, the announcement identification signal modulated onto the carrier signal is converted into a low-frequency position.

The output of the mixer stage ms is via the analog low-pass filter af at the input of the analog-digital converter aw, to which the clock signal ft is fed. The upper cut-off frequency of the low-pass filter af is at most equal to half the frequency of the scanning signal from the analog-digital converter aw, and its output is at the input of the digital absolute value generator br. This forms the amount of the input signal defined in the mathematical sense, i.e. its output signal is always positive and corresponds to the respective pure numerical value for both positive and negative input signals; both the number - -7 and the number + thus become + 7.

At the output of the absolute value generator br, the digital signal x is generated in the baseband position, and this is for the announcement frequency fa or the frequency fb, fc deviating therefrom by at most + 1% or -1% with the first, second or third signal path a, b, c connected. These consist in the signal flow direction of the digital resonance filter ra, rb, rc for the corresponding frequency fa, fb, fc as their resonance frequency, the digital absolute value generator ba, bb, bc and the digital low pass pa, pb, pc. Its respective upper cut-off frequency is less than twice the announcement frequency fa, and the three resonance filters ra, rb, rc have the same bandwidth and the same resonance magnification, as illustrated in FIG. 2.

On the other hand, at the output of the magnitude generator br is the series connection of the first and the second further digital low-pass filter p1, p2, whose respective upper cut-off frequency is equal to that of the digital low-pass filters pa, pb, pc or the frequency corresponding to the settling time constant of the resonance filters ra, rb, rc is. This is followed by the constant multiplier m1 and m2 in a parallel branch.

The first signal path a leads to the respective minuend input m of the first, second, third and fourth comparators k1, k2, k3, k4, of which the Subtrahend input s of the first and second comparators k1, k2 at the output of the first and second constant multipliers m1, m2 and subtrahend input s of the third and fourth comparators k3, k4 at the output of the second and third signal paths b, c lies. The minuend-larger subtrahend output m> s of the first comparator k1 is located at the S input of the RS memory flip-flop ff, from whose Q output the binary announcement identification signal dk is to be taken, and the respective minuend-smaller subtrahend output m < s of the second, third and fourth comparators k2, k3, k4 is located above the OR gate og at the R input of the RS flip-flop ff.

The constant d1, d2 of the respective constant multiplier m 1, m2 is in each case less than one and equal to the nominal degree of modulation of the announcement characteristic signal or equal to a predeterminable fraction of the nominal degree of modulation.

FIG. 3 shows that the arrangement according to the invention can also be used with a plurality of broadcasting frequencies, as is the case, for example, for a standard customary in the USA. In this case, the 'three signal paths a, b, c, the comparators k1 ... k4 assigned to them and the RS memory flip-flop ff are to be provided twice, each with a corresponding frequency rating.

The common circuit part is then also dimensioned with regard to the highest occurring announcement frequency. For such an arrangement, the course of the resonance curves of the then six resonance filters is shown in FIG. 3, the resonance frequency of which is fa1, fb1, fc1; fa2, fb2, fc2 are designated.

The carrier amplitude, to which the announcement signal is modulated, is measured by means of the magnitude generator br, which performs a full-wave rectification, comparable to a rectifier bridge for analog signals. At the same time, the announcement frequency is demodulated. The three signal paths a, b, c serve as a selective level meter, the signal path a measuring the announcement frequency and the two signal paths b, c detecting closely adjacent interference signals. Only when there is an input signal on the three signal paths with a frequency between the intersections x, y of the resonance curve of the resonance filter ra with the respective resonance curve of the other two resonance filters is the output signal on signal path a greater than that on the other two signal paths b, c. By comparison using the comparators k3, k4 it is then determined and recorded whether the frequency of the input signal is in the range between x and y.

The RS memory flip-flop ff is set by means of the comparator k1 if the output signal on the signal path a is greater than the output signal of the magnitude generator br, which is filtered by the low-pass filters p 1, p2 and multiplied by the factor d 1. The flip-flop ff is reset by means of the comparators k2 ... k4 and the OR gate og in each case when one of the output signals of the signal paths b, c is greater than that of the signal path a or this output signal is smaller than that by means of the low-pass filters p1 , p2 filtered and multiplied by the factor d2 output signal of the magnitude br. A circuit hysteresis can therefore be set with the factor d2.

The invention can be implemented particularly advantageously in the form of integrated semiconductor circuits. Since it works exclusively, at least as far as the subcircuits behind the analog-digital converter aw are concerned, according to digital circuit principles, the semiconductor circuit families customary for digital signal processing can be used, of which in particular the so-called MOS-integrated circuits can be used, i.e. integrated insulating layer field effect transistor circuits. Furthermore, there is the advantage that the inventive design with regard to the resonance frequencies of the resonance filters that are adjacent in the one percent range achieves very good interference suppression and reliable announcement frequency detection. Such a narrow resonance frequency measurement with analog resonance filters would only be achievable with considerable effort.

Claims (2)

1. Integrated circuit for decoding traffic information message tone signals whose frequency, the message tone frequency (fa), is the information marking a traffic information message, and which are contained, in the form of a carrier amplitude- modulated therewith, in a received broadcast signal (ds) demodulated with a conventional radio receiver, characterized by the following features:

- from the demodulated broadcast signal (ds), a digital signal (x) in the baseband is derived by further demodulation and analog-to-digital conversion;

- the digital signal (x) is applied to a first signal path (a) for each message tone frequency (fa; fa1, fa2) and to second and third signal paths (b, c) for frequencies (fb, fc; fb1, fb2; fc1, fc2) differing from said message tone frequency by a maximum of + 1 % and - %, respectively, each of said signal paths consisting of a tandem arrangement of a digital filter (ra, rb, rc) tuned to the respective frequency (fa, fb, fc; fa1, fb1, fc1; fa2, fb2, fc2) and having the same bandwidth and the same resonant rise, a digital absolute-value stage (ba, bb, bc), and a digital low-pass filter (pa, pb, pc) having an upper cutoff frequency lower than twice the message tone frequency (fa);

- the digital signal (x) is fed to a series combination of a first additional digital low-pass filter (p 1 ), having an upper cutoff frequency equal to that of the digital low-pass filters (pa, pb, pc), and a second additional digital low-pass filter (p2), having an upper cutoff frequency equal to the frequency corresponding to the transient-time constant of the tuned filters (ra, rb, rc);

- the first signal path (a) leads to the minuend inputs (m) of first, second, third, and fourth digital comparators (k 1, k2, k3, k4) of which the first and second comparators (k1, k2) have their subtrahend inputs (s) connected to the output of the second additional low-pass filter (p2) via a first constant multiplier (m1) and to the output of a second constant multiplier (m2), respectively, while the subtrahend inputs (s) of the third and fourth comparators (k3, k4) are connected to the outputs of the second signal path (b) and the third signal path (c), respectively;

- the minuend-greater-than-subtrahend output (m > s) of the first comparator (k 1) is coupled to the S input of an RS flip-flop (ff) providing the binary message tone signal (dk) at its Q output;

- the minuend-smaller-than-subtrahend outputs (m < s) of the second, third, and fourth comparators (k2, k3, k4) are coupled through an OR gate (og) to the R input of the RS flip-flop (ff), and

- the constants (d 1, d2) are smaller than one, and that of the first constant multiplier (m 1 ) is equal to the nominal modulation factor of the message tone signal, while that of the second constant multiplier (m2) is equal to a presettable fraction of the nominal modulation factor.

2. An integrated circuit as claimed in claim 1, characterized by the following features for further demodulation and analog-to-digital conversion:

- the demodulated broadcast signal (ds) is fed to a mixer (ms) to which a local-oscillator frequency (fm) higher than the sum of the message tone frequency (fa) and the carrier frequency of the message tone signal is applied, and

- the output of the mixer (ms) is coupled to the input of an analog-to-digital converter (aw) through an analog low-pass filter (af) having a maximum upper cutoff frequency equal to half the frequency of the sampling signal (ft) of the analog-to-digital converter (aw), whose output is connected to the input of an additional digital absolute-value stage (br).

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