EP0144432A4 - Memory readout control system. - Google Patents
Memory readout control system.Info
- Publication number
- EP0144432A4 EP0144432A4 EP19840901404 EP84901404A EP0144432A4 EP 0144432 A4 EP0144432 A4 EP 0144432A4 EP 19840901404 EP19840901404 EP 19840901404 EP 84901404 A EP84901404 A EP 84901404A EP 0144432 A4 EP0144432 A4 EP 0144432A4
- Authority
- EP
- European Patent Office
- Prior art keywords
- data
- speed memory
- storage region
- control system
- readout control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/18—Numerical control [NC], i.e. automatically operating machines, in particular machine tools, e.g. in a manufacturing environment, so as to execute positioning, movement or co-ordinated operations by means of programme data in numerical form
- G05B19/408—Numerical control [NC], i.e. automatically operating machines, in particular machine tools, e.g. in a manufacturing environment, so as to execute positioning, movement or co-ordinated operations by means of programme data in numerical form characterised by data handling or data format, e.g. reading, buffering or conversion of data
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
- G06F5/065—Partitioned buffers, e.g. allowing multiple independent queues, bidirectional FIFO's
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/30—Nc systems
- G05B2219/35—Nc in input of data, input till input file format
- G05B2219/35373—Data storage, buffer
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/30—Nc systems
- G05B2219/36—Nc in input of data, input key till input tape
- G05B2219/36107—Bubble memory
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Human Computer Interaction (AREA)
- Manufacturing & Machinery (AREA)
- Automation & Control Theory (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Numerical Control (AREA)
- Memory System (AREA)
Abstract
A high-speed memory (4) is constructed so that it is provided with at least a first data-storage region (4a) which is accessed by a processor (1) and a second data-storage region (4b) into which data in a low-speed memory (5) is transferred and stored. The processor (1) reads data out of the first data-storage region (4a) of the high-speed memory (4), then transfers the data in the second data-storage region (4b) of the high-speed memory (4) into the first data-storage region (4a), and also accesses the low-speed memory (5) to transfer data therein into the second data-storage region (4b) of the high-speed memory, so that the processor can continuously read out data regardless of any access to the low-speed memory.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56472/83 | 1983-03-31 | ||
JP58056472A JPS59180877A (en) | 1983-03-31 | 1983-03-31 | Control system of memory read-out |
Publications (2)
Publication Number | Publication Date |
---|---|
EP0144432A1 EP0144432A1 (en) | 1985-06-19 |
EP0144432A4 true EP0144432A4 (en) | 1988-05-26 |
Family
ID=13028042
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP19840901404 Withdrawn EP0144432A4 (en) | 1983-03-31 | 1984-03-30 | Memory readout control system. |
Country Status (3)
Country | Link |
---|---|
EP (1) | EP0144432A4 (en) |
JP (1) | JPS59180877A (en) |
WO (1) | WO1984003990A1 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4774654A (en) * | 1984-12-24 | 1988-09-27 | International Business Machines Corporation | Apparatus and method for prefetching subblocks from a low speed memory to a high speed memory of a memory hierarchy depending upon state of replacing bit in the low speed memory |
DE68925515T2 (en) * | 1988-11-11 | 1996-05-30 | Victor Company Of Japan | Data processing equipment |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0030981A1 (en) * | 1979-06-30 | 1981-07-01 | Fanuc Ltd. | Numerical control device |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5313325A (en) * | 1976-07-21 | 1978-02-06 | Mitsubishi Electric Corp | Connection method between information processing unit and peripheral device |
JPS5750380A (en) * | 1980-09-09 | 1982-03-24 | Mitsubishi Electric Corp | Writing method of buffer storage device |
-
1983
- 1983-03-31 JP JP58056472A patent/JPS59180877A/en active Pending
-
1984
- 1984-03-30 EP EP19840901404 patent/EP0144432A4/en not_active Withdrawn
- 1984-03-30 WO PCT/JP1984/000154 patent/WO1984003990A1/en not_active Application Discontinuation
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0030981A1 (en) * | 1979-06-30 | 1981-07-01 | Fanuc Ltd. | Numerical control device |
Non-Patent Citations (3)
Title |
---|
ELECTRONICS INTERNATIONAL, vol. 56, no. 16, 11th August 1983, pages 121-125, New York, US; W. BOENING et al.: "Multichannel DMA controller transfers 8 megabytes a second" * |
PATENT ABSTRACTS OF JAPAN, vol. 2, no. 49 (E-78)[837], 6. April 1978; & JP-A-53 13 325 (MITSUBISHI DENKI K.K.) 02-06-1978 * |
See also references of WO8403990A1 * |
Also Published As
Publication number | Publication date |
---|---|
EP0144432A1 (en) | 1985-06-19 |
JPS59180877A (en) | 1984-10-15 |
WO1984003990A1 (en) | 1984-10-11 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
17P | Request for examination filed |
Effective date: 19841219 |
|
AK | Designated contracting states |
Designated state(s): DE FR GB |
|
A4 | Supplementary search report drawn up and despatched |
Effective date: 19880526 |
|
17Q | First examination report despatched |
Effective date: 19900315 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN |
|
18D | Application deemed to be withdrawn |
Effective date: 19921001 |
|
RIN1 | Information on inventor provided before grant (corrected) |
Inventor name: SAKAKIBARA, SHINSUKE Inventor name: TACHIBANA, MITSUO |