EP0102750B1

EP0102750B1 - Character font display systems

Info

Publication number: EP0102750B1
Application number: EP19830304381
Authority: EP
Inventors: Marion A.Iv Keyes
Original assignee: Babcock and Wilcox Co
Current assignee: Babcock and Wilcox Co
Priority date: 1982-08-06
Filing date: 1983-07-28
Publication date: 1989-12-06
Also published as: CA1224289A; EP0102750A3; JPH0489996U; IN159329B; EP0102750A2; AU555262B2; DE3380944D1; JPS5958475A; AU1624183A

Description

This invention relates to systems for providing character fonts to display devices.
A typical raster scan type color cathode ray tube display generally comprises characters displayed in fixed rows and columns on a cathode ray tube. The display is refreshed internally by storing character codes (ASCII), along with color blink information, in a random access memory (RAM). The display refreshed by sequentially reading these codes, which are used as address information, to access a read only memory (ROM) in which the character fonts are stored. These character fonts are typically formed by dots within a matrix. Generally, a fixed repertoir of characters is displayable, typically 64 alphanumerics and 64 special symbols. Inasmuch as the repertoire of characters is fixed, the flexibility of the foregoing systems is very limited since characters cannot be changed in or added to the read only memory (ROM) by the operator.
Because of the foregoing, it has become desirable to develop a system wherein additional characters are available and these characters can be programmed by the operator.
US Patent No. US-A-3 729 730 discloses a display system having a single processor memory divided into two areas for control of the display. One area constitutes a character buffer for representing the code of the character to be formed in each position of the display, and the other area constitutes a dot pattern storage area which includes the dot patterns for all of the characters. During each display cycle, a first address corresponding to the position of a character to be displayed is transmitted to the memory, and a code representing the character to be displayed is returned to the display system and is combined with addition positional information to form a second address for transmission to the memory. The data word received back from the memory determines the locations of dots to be displayed in one line segment.
According to the invention there is provided a system for providing character fonts to a display device, the system comprising first memory means having character fonts contained therein and being characterised by microprocessing means having a program memory associated therewith, said memory means having character fonts contained therein, means controllable by the program memory for selecting between the first memory means and the second memory means to cause the appropriate character fonts contained therein to be transferred to the display device, and an isolation and control circuit connected to the selecting means, the second memory means, the microprocessing means and the display device, the circuit being responsive to the microprocessing means to permit entry of and modification of the character fonts contained in the second memory means and being responsive to the selecting means to cause the appopriate character fonts contained in the second memory means to be transferred to the display device, the circuit being controllable in response to program command signals from the microprocessing means.
A preferred embodiment of the present invention describes hereinbelow solves or at least alleviates the aforementioned problems associated with the prior art by providing a random access memory (RAM), in addition to the read only memory (ROM), for the storage of the character fonts. The RAM is accessible and programmable by a microprocessor (central processing unit) for the entry of character fonts therein. In operation, the microprocessor can access either the read only memory (ROM) or the random access memory (RAM), via a display memory, which contains character codes that are used as address information. Depending upon whether the read only memory (ROM) or the random access memory (RAM) is selected, the contents of the proper memory location associated with the character code is transferred to a video generator which, in turn, is connected to a sweep deflection driver and color drivers of a cathode ray tube display. In this manner, the fixed characters from the read only memory and the programmable characters from the random access memory can be displayed on the cathode ray tube.
The invention will now be further described, by way of illustrative and non-limiting example, with reference to the accompanying drawings, in which:

Figure 1 is an electrical schematic of a system embodying this invention; and
Figure 2 is an electrical schematic of isolation and control circuitry of the system of Figure 1 illustrating its interconnection to a read only memory (ROM) and a random access memory (RAM) used for character generation.

Figure 1 is an electrical schematic of a system 10 embodying this invention for providing character fonts to a display device in the form of a color cathode ray tube. The system 10, which provides a color graphic cathode ray tube display using writeable character fonts, includes a microprocessor 12 having a program memory 14 associated therewith, a character generator in the form of a read only memory (ROM) 16, a programmable character generator in the form of a random access memory (RAM) 18, a display memory 20 and a video generator 22.
The microprocessor 12 (central processing unit) controls the flow of information throughout the system 10 under the direction of the program memory 14. The program memory 14 typically is contained in the microprocessor 12 but may be separate therefrom if the microprocessor 12 does not contain sufficient memory capacity. A data entry keyboard 24 and a communications input 26, for the entry of data from another computer, etc. are provided and can access the microprocessor 12 in order to enter and/or modify data within the program memory 14 or the programmable character generator (RAM) 18. The microprocessor 12 can access the display memory 20 or the read-write isolation and control circuitry, shown generally as numeral 28, through which it has access to the programmable character generator (RAM) 18. The program memory 14 is programmed to select the proper character generator and does so through the display memory 20 which has character codes (ASCII), used as address information, stored therein. The display memory 20, through a line buffer 30, accesses either the programmable character generator (RAM) 18, via the isolation and control circuit 28, or the character generator (ROM) 16. Depending upon which character generator is selected, the contents of the proper memory location associated with the character code (ASCII) is transferred to a tri-state buffer 32. In the case of the character generator (ROM) 16, this transfer is directly from this generator 16 to the buffer 32, whereas if the programmable character generator (RAM) is utilized, the transfer of the contents of the proper memory location in the character generator 18 to the buffer 32 occurs via the isolation and control circuitry 28. In either case the output of the buffer 32 is connected to the input to a video shift register 34 whose output is connected to the input to the video generator 22. The output of the video generator 22 is connected to a sweep deflection driver 36 which controls the horizontal and vertical sweeps on a cathode ray tube 38 and is also connected to color drivers 40 which control the red, blue and green colors on the cathode ray tube 38. In this manner, writeable character fonts, formed by dots within a dot matrix, are produced and the resulting characters are displayed in fixed rows and columns, typically 80 columns by 48 rows, on the cathode ray tube 38.
Referring now to Figure 2, the read-write isolation and control circuitry 28, along with its interconnection with other circuit components, is detailed. Figure 2 illustrates an eight bit address and an eight bit isolation system. Such isolation is required to permit the microprocessor 12 to program the character generator 18 and to then permit the character generator 18 to subsequently provide data to the video generator 22. This isolation and control circuitry 28 comprises AND gates A₁ to A₈, AND gates A₉ to A₁₆, AND gates D, to D₈, AND gates Dg to D₁₆, inverters B, and B₄, and amplifiers B₂ and B₃. The address bus from the microprocessor 12 is connected to one input to each of the AND gates A, to A₈, while the other input to each of these gates A₁ to A₈ is connected to the output of the amplifier B₂ whose input is connected to the program command bus of the microprocessor 12. The address bus from the display memory 20 is connected to one input to each of the AND gates A₉ to A₁₆, while the other input to each of these gates Ag to A₁₆ is connected to the output of the inverter B, whose input is also connected to the program command bus of the microprocessor 12. The outputs of the gates A₁ to A₈ and gates A₉ to A,₆ are respectively connected together and the resulting connections form an input to the programmable character generator (RAM) 18. The data bus from the microprocessor 12 is connected to one input to each of the AND gates D, to D₈, while the other input to each of these gates D, to D₈ is connected to the output of the amplifier B₃ whose input is connected to the program command bus of the microprocessor 12. The outputs of these gates D, to D₈ are respectively connected to the inputs to AND gates D₉ to D₁₆ and form another input to the programmable character generator (RAM) 18. The other input to each of these AND gates D₉ to D₁₆ is connected to the output of the inverter B₄ whose input is connected to the program command bus of the microprocessor 12. The outputs of the gates D₉ to D₁₆ are connected to the input to the tri-state buffer 28.
In operation, the microprocessor 12 programs the display memory 20 with character codes (ASCII) corresponding to the addresses of the characters required. When the character generator (ROM) 16 receives a particular address from the display memory 20, it outputs the digital equivalent of the character required through the tri-state buffer 32 to the video shift register 34 which, in turn, transmits these data to the video generator 22. The video generator 22, through the sweep deflection driver 36, controls the horizontal and vertical sweep of the cathode ray tube 28, and also controls the color drivers 40 which produce the various color dots which form the desired characters on the cathode ray tube.
Through the use of the isolation and control circuitry 28, the microprocessor 12 can program the character generator (RAM) 18 which can then act as a special character generator. In this case, the display memory 20, through the line buffer 30, can select either the programmable character generator (RAM) 18 or the character generator (ROM) 16 and transfer the data contained therein to the tri-state buffer 32 and then to the video shift register 34 for transmission of same to the video generator 22.
Referring again to Figure 2, in order to program the programmable character generator (RAM) 18, a program command signal in the form of a digital (1) is received on the program command bus from the microprocessor 12. This digital (1) is inverted by the inverter B₁to a digital (0) which is applied to an input to each of the AND gates As to A₁₆ disabling all of these gates and preventing the address bus from the display memory 20 from accessing the programmable character generator (RAM) 18. Similarly, this digital (1) signal passes through amplifier B₂ and is applied to an input to each of the AND gates A₁ to A₈ enabling same permitting the address bus from the microprocessor 12 to access the programmable character generator (RAM) 18. While this is occurring, this digital (1) is applied to an input to each of the AND gates D₁ to D_e enabling same permitting the data bus from the microprocessor 12 to gain access to the programmable character generator (RAM) 18. This same digital (1) signal is inverted by inverter B₄ to a digital (0) which is applied to an input to each of the AND gates Dg through D₁₆ disabling same preventing the data bus from the microprocessor 12 from transmitting data directly to the tri-state buffer 32. In this manner, the microprocessor 12 can address the programmable character generator (RAM) 18.
As previously stated, during normal operation of the system, the display memory 20 transmits a particular address along its address bus to the character generator 16. The character generator 16, in turn, transmits the digital equivalent of the characters required to the tri-state buffer 32 which, in turn, transmits these data to the video shift register 34. If, however, a character from the programmable character generator (RAM) 18 is required, a program command signal in the form of a digital (0) is transmitted by the microprocessor 12 on the program command bus. This digital (0) signal is transformed into a digital (1) by the inverter B, causing the AND gates As to A₁₆ to be enabled allowing the address bus for the display memory 20 to access the programmable character generator (RAM) 18. The foregoing digital (0) also disables AND gates A, to A₈ and D, to D₈ preventing the address bus and the data bus from the microprocessor 12 from accessing the programmable character generator (RAM) 18. While this is occurring, this digital (0) signal is inverted by the inverter B₄to a digital (1) resulting in the enabling of AND gates Dg to D,_6' The display memory 20 can then access the programmable character generator (RAM) 18 directly which, in turn, transmits the digital equivalent of the character required to the tri-state buffer 32 via the AND gates Dg to D₁₆. The tri-state buffer 32 then transmits these data to the video shift register 34. In this manner, the character generator memory capacity has been effectively expanded by the capacity of the programmable character generator (RAM) 18.

Claims

1. A system for providing character fonts to a display device, the system (10) comprising first memory means (16) having character fonts contained therein and being characterised by microprocessing means (12) having a program memory (14) associated therewith, second memory means (18) having character fonts contained therein, means controllable by the program memory (14) for selecting between the first memory means (16) and the second memory means (18) to cause the appropriate character fonts contained therein to be transferred to the display device (38), and an isolation and control circuit (28) connected to the selecting means, the second memory means (18), the microprocessing means (12) and the display device (38), the circuit (28) being responsive to the microprocessing means (12) to permit entry of and modification of the character fonts contained in the second memory means (18) and being responsive to the selecting means to cause the appropriate character fonts contained in the second memory means (18) to be transferred to the display device (38), the circuit (28) being controllable in response to program command signals from the microprocessing means (12).

2. A system according to claim 1, including accessing means (24, 26) for accessing the microprocessing means (12) to permit the entry of and modification of information within the system.

3. A system according to claim 2, wherein the accessing means comprises a communication input means (26).

4. A system according to claim 1, claim 2 or claim 3, wherein the selecting means includes a display memory (20) containing address information as to the character fonts respectively stored in the first memory means (16) and the second memory means (18), the display memory (20) being accessible by the microprocessing means (12) and being operable to select between the first memory means (16) and the second memory means (18) in response to an address supplied by the program memory (14).

5. A system according to claim 4, wherein the isolation and control circuit (28) comprises:

a first amplifier (B-2) having its input connected to a program command bus of the microprocessing means (12) for receiving program command signals from the microprocessing means (12);

a first assembly of AND gates (A-1 to A-8) each having a first input connected to an address bus from the microprocessing means (12), a second input connected to the first amplifier (B-2), and an output connected to the second memory means (18), the first assembly of AND gates (A-1 to A-8) being operable to permit the address bus from the microprocessing means (12) to access the second memory means (18) in response to a first program command signal from the microprocessing means (12) and being operable to prevent the address bus from the microprocessing means (12) from accessing the second memory means (18) in response to a second program command signal from the microprocessing means (12);

a second amplifier (B-3) having its input connected to the program command bus of the microprocessing means (12) for receiving program command signals from the microprocessing means (12);

a second assembly of AND gates (D-1 to D-8) each having a first input connected to a data bus from the microprocessing means (12), a second input connected to the second amplifier (B-3), and an output connected to the second memory means (18), the second assembly of AND gates (D-1 to D-8) being operable to permit the data bus from the microprocessing means (12) to access the second memory means (18) in response to the first programm command signal from the microprocessing means (12) and being operable to prevent the data bus from the microprocessing means (12) from accessing the second memory means (18) in response to the second program command signal from the microprocessing means (12);

a first inverter (B-1) having its input connected to the program command bus of the microprocessing means (12) for receiving program command signals from the microprocessing means (12);

a third assembly of AND gates (A-9 to A-16) each having a first input connected to an address bus from the display memory (20), a second input connected to the first inverter (B-1), and an output connected to the second memory means (18), the third assembly of AND gates (A-9 to A-16) being operable to prevent the address bus from the display memory (20) from accessing the second memory means (18) in response to the first program command signal from the microprocessing means (12) and being operable to permit the address bus from the display memory (20) to access the second memory means (18) in response to the second program command signal from the microprocessing means (12);

a second inverter (B-4) having its input connected to the program command bus of the microprocessing means (12) for receiving program command signals from the microprocessing means (12); and

a fourth assembly of AND gates (D-9 to D-16) each having a first input connected to the data bus from the microprocessing means, a second input connected to the second inverter (B-4), and an output connected to the display device (38), the fourth assembly of AND gates (D-9 to D-16) being operable to prevent the data bus from the microprocessing means (12) from accessing the display device (38) in response to the first program command signal from the microprocessing means (12) and being operable to permit the data bus from the second memory means (18) to access the display device (38) in response to the second program command signal from the microprocessing means (12);

wherein the isolation and control circuit (28) is operable to permit the microprocessing means (12) to access the second memory means (18) to permit the entry of and modification of the character fonts contained therein in response to the first program commanded signal from the microprocessing means (12), and is operable to permit the dsplay memory (20) to access the second memory means (18) causing the appropriate character fonts contained therein to be transferred to the display device (38) in response to the second program command signal from the microprocessing means (12).

6. A system according to claim 5, wherein the first program command signal from the microprocessing means (12) is a digital "1".

7. A system according to claim 5, wherein the second program command signal from the microprocessing means (12) is a digital "0".

8. A system according to any one of the preceding claims, wherein the first memory means (16) is a read only memory means.

9. A system according to any one of the preceding claims, wherein the second memory means (18) is a random access memory means.