EP0038002B1 - System for displaying characters on a screen - Google Patents

Description

The invention relates to an arrangement for displaying characters on a screen of a display unit according to the preamble of claim 1.

From DE-PS 25 40 734 an arrangement for displaying characters on a screen of a display unit is known, in which the characters to be displayed are encoded by code characters stored in a data memory. An image control unit calls the code characters from the data memory in a periodic sequence, corresponding to 50 or 60 image changes per second. The image control unit contains a character generator in which data words associated with the forms of the characters that can be displayed on the screen are stored. Depending on the characters to be displayed on the screen, the corresponding data words are read from the character generator and fed to the display unit as line signals. If the display unit is designed as a cathode ray tube, the line signals represent video signals with which the electron beam is blanked.

In an arrangement for displaying characters known from DE-PS 24 46 048, the image repetition memory is designed as a shift register. The code characters assigned to the characters to be displayed circulate continuously in the shift register in accordance with the frame rate. Using a multiplexer, the code characters each representing a line are read out of the shift register. The code characters are also fed to a character generator which outputs data words assigned to the shapes of the characters. In this known arrangement, the video signals for the display unit designed as a cathode ray tube are generated using the data words.

In these known arrangements, a line grid is specified for the representation of the characters, which is formed in each case from several lines and which cannot be changed. Furthermore, the characters can only be displayed at specified character spaces.

From a publication "Distributed Architecture For A Fast High Resolution Raster Scan Display" by H. Roethlisberger in "Microprocessors And Their Applications", Fifth Euromicro Symposium On Microprocessing And Microprogramming, August 28-30, 1979, Amsterdam, 1979, pages 59 To 62 it is known to arrange an image repetition memory in the connection path between the image generator and the display unit. The image repetition memory is designed as a pixel memory in which a memory element is assigned to each pixel on the screen. When using such an image repetition memory in the connection path between the image generator and the display unit, it is possible to display the characters at any point on the screen independently of a line grid. A character generator is provided in the image generator, with the aid of which data words assigned to the code characters are generated. The character generator is connected to a microcomputer via a data bus and connected to the pixel memory via a further data bus.

Using the arrangement known from this publication, it is not readily possible to display multiple characters, such as the character "0", if this is not stored in the character generator, and it is also not readily possible to change or delete the data words stored in the pixel memory.

The invention is therefore based on the object of specifying an arrangement which enables the data words of characters stored in the pixel memory to be changed or deleted in a simple manner and, when used, in particular enables simple display of multiple characters.

According to the invention the object is achieved in the arrangement of the type mentioned by the features specified in the characterizing part of claim 1.

For this purpose, the pixel memory is preferably operated in a "read-modify-write" operating mode. In this operating mode, the stored information is first read out in each storage cycle and it is possible to change it before the information is stored again. The change is made using the link unit.

For a representation of double or multiple characters, it is advantageous if the linking unit links the data words and the data words read out in accordance with an OR function. Correspondingly, for deleting data words, it is expedient if the linking unit links the data words and the read data words in accordance with an antivalence function.

It would be conceivable to design the memory in the pixel memory as a shift register. Saving and restoring the data words is particularly easy if the memory is designed as a dynamic MOS memory with random access. With dynamic MOS memories of this type, the stored information must be refreshed at the latest after a predetermined period of time. In the arrangement, no special measures are required for the refresh if the data words stored in the memory are refreshed by the periodic readout when the characters are displayed on the screen.

An interruption of the presentation at It is not necessary to store data words in the memory if the data words are stored in the pixel memory during the line rewind and / or during the rewind.

If the data words are stored in bytes in the pixel memory, it is expedient that the pixel memory contains a parallel-to-serial converter, the parallel inputs of which are connected to the outputs of the memory and the output of which is connected to the display unit.

To control the cooperation of the pixel memory with the image generator and the display unit, it is advantageous if the pixel memory contains a time control unit which generates control signals for storing the data words in the memory, periodically reading out the data words from the memory and synchronizing the display unit.

• Figur 1 ein Blockschaltbild eines mit der Anordnung versehenen Telekommunikationsgeräts,
• Figur 2 ein Blockschaltbild eines Bildgenerators und eines Bildpunktspeichers,
• Figur 3 ein Blockschaltbild einer im Bildpuktspeicher vorgesehenen Speichereinheit.

In the following an embodiment of the arrangement according to the invention is described with reference to drawings. Show it:

• FIG. 1 shows a block diagram of a telecommunications device provided with the arrangement,
• FIG. 2 shows a block diagram of an image generator and an image point memory,
• FIG. 3 shows a block diagram of a memory unit provided in the image memory.

The telecommunications device shown in Figure 1 is controlled by a microprocessor MP. An interruption control IS and, on the other hand, a programmable control unit for direct memory access DMA (direct memory access) are connected to the microprocessor MP. A primary memory PS, a secondary memory SS, a keyboard TA, a printer DR, a communication part KT and an arrangement for displaying characters on the screen BS of a display unit AZ are connected via a data bus DB and possibly an address bus. The primary memory PS is designed as a semiconductor memory and it serves as a program memory and working memory. The secondary memory SS can be designed as a floppy disk memory and / or as a magnetic bubble memory. The keyboard TA contains keys for entering alphanumeric characters and function keys for performing various functions.

The printer DR is designed in a known manner and contains a type or a mosaic printing unit. The communication part KT is connected to a long-distance line FL and contains transmission units for sending characters or stored characters entered by means of the keyboard TA and for receiving characters.

The arrangement for displaying characters on the screen BS of a display unit AZ contains, in addition to the display unit AZ, an image generator BG and a pixel memory BP. When characters are displayed on the screen BS, code characters assigned to these characters are transmitted from the primary memory PS or from the secondary memory SS via the data bus DB to the image generator BG. The image generator BG contains a character generator ZG, which contains data words assigned to the shape of the characters in a manner known per se. Depending on the code characters, the corresponding data words are read from the character generator ZG and transferred to the pixel memory BP. A memory element of a memory SP provided in the pixel memory BP is assigned to each pixel on the screen BS. The data words are stored in these storage elements. The image point memory BP serves as an image repetition memory and from it the data words corresponding to an image change frequency of approximately 50 or 60 image changes per second are read out and transmitted to the display unit AZ. The screen BS of the display unit AZ can be designed as a screen of a cathode ray tube. In this case, a video signal is generated from the data words, with which the electron beam is palpated. If the screen BS is formed from individual picture elements, the data words are supplied to these picture elements.

The characters on the screen BS are displayed line by line and the characters to be displayed are composed of pixels which are arranged on these lines. For example, a character space is formed from 6x12 pixels and the characters are displayed within the character space in a basic grid of 5x7 pixels.

The memory capacity of the memory SP provided in the pixel memory BP is 512x256 bits, so that the characters can be displayed in 21 lines with 85 characters each on the screen BS.

Further details are described below together with the representations in FIGS. 2 and 3.

The image generator BG shown in FIG. 2 contains a control unit ST, which is also designed, for example, as a microprocessor system. The control unit ST is connected on the input side to the data bus DB. When a character is displayed on the screen BS, the code character CZ assigned to this character is transmitted to the image generator BG via the data bus DB. The control unit ST switches the code character CZ through to the character generator ZG, in which data words DW associated with the shape of the character are stored. The character is formed in raster lines, with each raster line corresponding to a data word DW. In addition, address signals which are assigned to the coordinates of the character on the screen BS are transmitted via the data bus DB. These coordinates are buffered in two registers XAR and YAR.

The pixel memory BP contains a time control unit ZS, which transfers the data words DW into the memory SP provided in a memory unit SPE, reads out the data words DW from the memory SP for generating the video signal VS and generating synchronizing signals SV and SH for a vertical one and horizontal synchronization of the display unit AZ controls.

The data words can be transferred to the storage unit SPE line by line or character by character. In the first case, the data words DW assigned to a line of the characters shown in one line are transmitted. In the second case, the data words DW assigned to a character are transmitted one after the other in time.

The transmission is expediently carried out after the display of a line or a complete image on the screen BS. This is determined by a signal S1 emitted by the time control unit ZS.

A processing unit ALU is connected upstream of the memory SP to manipulate the data words stored in the memory SP. This processing unit is designed, for example, as a commercially available arithmetic and logical control unit. It links the signals at its inputs according to arithmetic or logical functions. The type of linkage is determined by control signals S2 which are output by the control unit ST.

Since the memory SP is organized in bytes, the data words DW1 in the memory unit SPE are fed to a parallel-to-serial converter, which generates the video signal VS after a parallel-to-serial conversion of the data words DW1 and outputs it to the display unit AZ.

In the pixel memory BP shown in FIG. 3, the memory unit SPE contains a dynamic MOS memory with random access as the memory SP. The memory SP has a storage capacity of 18 KB for displaying 512x256 pixels on the display unit AZ. The memory SP is organized in bytes, so that its address space comprises 18K. The low-order address bits are represented by the address signals A2. The address signals A1 and A2 are fed to a multiplexer MX1. When data words DW are stored in the memory SP, the multiplexer MZ1 switches through the address signals A1 and A2 to a multiplexer MX2. The switching is carried out by a signal SZ output by the time control unit ZS during the line return and / or the image return of the electron beam. With a signal S3, an MX2 first switches through the least significant bits as the row address and then the more significant bits as the column address of the memory SP. At the same time, the time control unit ZS sends signals ZA and SA to the memory SP, with which it is communicated that the address present in each case is a row or a column address. At the same time, a write signal SB is emitted. The data word output by the image generator BG is then stored at the point in the memory SP identified by the address signals A1 and A2.

To display the characters on the screen BS, the memory SP is read out line by line. The time control unit ZS contains a counter which generates address signals AD, which call the memory elements of the rows of the memory SP in succession in a cyclical order and those of the individual columns within the rows. When reading out, the signal SZ switches the signals AD through to the output of the multiplexer MX1. In a similar way to when storing, the time control unit ZS generates the signals S3, ZA and SA, so that the memory SP is read out line by line. The stored data words are read out in parallel byte by byte and fed as signals DW1 to a parallel-series converter PSU. The parallel-to-series converter PSU generates, under control by a signal S4 from the data words DW1, the video signal VS, which is used for scanning the electron beam in the cathode ray tube of the display unit AZ. The time control unit ZS simultaneously outputs the synchronization signals SV and SH to the display unit AZ.

When displaying characters, the forms of which are stored in the character generator ZG, the data words DW are switched through unchanged via the link unit ALU to the memory SP, controlled by the signal S2.

When displaying multiple characters that can be composed of characters stored in the character generator ZG, the data words DW of a first character are first stored in the memory. After reading out the stored data words DW1, these are linked with the data words DW of the further character in the link unit ALU in accordance with an OR link and stored in the corresponding location in the memory SP at which the data words DW1 were previously stored. In this way, the pixel sets of the two characters are combined so that the union of the pixels is displayed on the screen BS. For this purpose, the memory SP is preferably operated in the "read-modify-write" operating mode, in which the stored information is first read out and then written to the same memory location after a change, if necessary. The OR operation is also set using a signal S2.

To delete a data word stored in the memory SP, this data word is read out according to an antivalence function with that of the data word Character generator ZG linked data word DW linked; By linking the two identical data words, a data word formed from all binary values 0 is stored in the memory SP. The antivalence function is also set by a signal S2. It is also possible to display the characters on the screen inversely, so that the colors of the background or of the characters are interchanged if the data words DW or DW1 are linked to a data word formed from pure binary values 1 in accordance with an antivalence function.

The memory SP can be understood as an image of the screen BS. A memory element in the memory SP is assigned to each possible pixel on the screen BS. If the electron beam is to be palpated at the location assigned to a possible pixel, a binary character with a first binary value, for example binary value 1, is stored in the corresponding memory element. In a corresponding manner, binary characters with the binary value 0 are stored at the points at which the electron beam is not palpated. Each line of the memory SP corresponds to a line on the screen BS.

By using the memory SP, the characters can be displayed at any coordinates on the screen BS. These coordinates are identified by the address signals A1 and A2.

Claims (7)

1. An arrangement for displaying characters on a screen (BS) of a display unit (AZ), wherein the characters are displayed on the screen (BS) in lines, wherein a picture generator (BG) employing a character generator (ZG) produces data words (DW) which are assigned to the shapes of the characters, and wherein a picture dot store (BP) provided with a store (SP) is arranged in the connecting path between the picture generator (BG) and the display unit (AZ), wherein the data words (DW) are stored in the store (SP) and periodically read out and wherein the picture dot store (BP) transmits video signals (VS) assigned to the characters, which are to be displayed, to the display unit (AZ), characterised in that the store (SP) in the picture dot store (BP) is preceded by a linking unit (ALU) which is designed as an arithmetic and logic control unit and by means of which prior to the storage in storage elements of the store (SP) the data words (DW) can be linked to data words (DW), which have previously been read out from the same storage elements of the store (SP), in dependence upon supplied control signals (S2).

2. An arrangement as claimed in claim 1, characterised in that the linking unit (ALU) links the data words (DW) and the read-out data words (DW1) in accordance with an OR-function.

3. An arrangement as claimed in claim 1 or 2, characterised in that the linking unit (ALU) links the data words (DW) and the read-out data words (DW1) in accordance with an antivalence function.

4. An arrangement as claimed in one of claims 1 to 3, wherein the store (SP) is designed as a dynamic MOS-store with selective access, characterised in that the regeneration of the data words (SW) stored in the store (SP) is effected by the periodic read-out during the representation of the characters on the screen (BS).

5. An arrangement as claimed in one of claims 1 to 4, characterised in that the storage of the data words (DW) into the picture dot store (BP) is effected during the line flyback and/or during the picture flyback on the screen (BS).

6. A system as claimed in one of claims 1 to 5, characterised in that the picture dot store (BP) comprises a parallel-series converter (PSU), whose parallel inputs are connected to the outputs of the store (SP) and whose output is connected to the display unit (AZ).

7. A system as claimed in one of claims 1 to 6, characterised in that the picture dot store (BP) comprises a timing control unit (ZS) which produces control signals for storing (signal 1) the data words (DW) into the store (SP), the periodic read-out of the data words (DW) from the store (SP) and the synchronisation (synchronising signals SV, SH) of the display unit (AZ).

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