EP0020185A1 - Method and apparatus for the serial-parallel addition of a great number of words - Google Patents

Abstract

The words to be added together are stored in shift registers (1i to 1p) whose serial outputs are connected to corresponding inputs of a transcoder (2) providing the binary value of the number "1" for each binary weight of the words to add. This value is sent to an adder-divider (4) which adds it to the number of "1" holding the next lower weight, divides this sum by 2, sends the fractional part to an output register (5) of the half sum and in a deduction register the whole part. Application: digital filters in MIC telephony.

Description

The present invention relates to a method for rapidly processing binary words to perform simultaneous addition, and to a rapid adder device for implementing this method.

The digital adders currently used to add several binary numbers, each having a large number of binary elements, comprise a cascade of adding cells each carrying out two Boolean functions with three variables, the carry propagating from cell to cell, which requires a relatively long computation time. To reduce the delay due to the propagation of the restraint, additional circuits are used which provide early restraint. However, the size of these latter adders becomes prohibitive when the format of the binary words to be added increases.

In many applications of adders, for example in digital filters, Fourier transformers, digital correlators in real time, it is necessary to carry out a large number of additions in a short time, for example about 65 million additions per second on words of 16 binary elements (bits) in certain transverse digital filters. In such cases, even fast-hold fast adders are no longer suitable.

The subject of the present invention is a method of processing binary words allowing the simultaneous addition of a large number of words composed of a large number of binary elements in the shortest possible time with the means currently available. , and also relates to an adder device for implementing this method.

The processing method in accordance with the present invention consists, starting from words each stored in a shift register and extracted at the serial output of these registers, sequentially extracting all the binary elements of the same weight starting with those of most significant weight weak and progressing in order towards those of highest weight, to be determined at each times the number of "1" among all the binary elements of the same weight, to add, for each considered weight of binary elements, the number of "1" of retention relating to the binary elements of immediately lower weight, to calculate the half sum of these two numbers, to send a "1" in a shift register when this half-sum is not an integer, and a "0" otherwise, to memorize a number equal to the whole part of this half-sum, and extracting the latter number as a number of "1" holdbacks for use when calculating the immediately following half-sum.

The device for implementing the method of the present invention comprises a transcoder device, the different inputs of which are connected to the serial outputs of the different shift registers in which the words to be added together are stored, this transcoder device being produced so as to present on its outputs the value, in pure binary, of the number of "1" present on its inputs, the outputs of this transcoder device being connected via a flip-flop register to corresponding binary weight inputs of a circuit parallel binary adder-divider itself connected to a storage register for the sum of the holdbacks, the least significant output of this adder-divider circuit being connected to the serial input of an output shift register.

According to a particular embodiment of the device of the invention, intended for the addition of a large number of words, for example greater than 16, the transcoder device has a pyramid structure with several processing stages, the stage of input, at the base of the pyramid, comprising in parallel several elementary transcoder circuits each supplying on its different outputs the value, in pure binary, of the number of "1" for each binary weight of all the words arriving on all its inputs, the outputs of at least two different transcoder circuits being grouped, each time, at the input of an adder circuit presenting on its outputs the sum of the input values, several stages of such adder circuits being arranged in cascade, each of these stages comprising a number of adding circuits lower than that of the preceding stage, for example half, the last stage, at the top of the pyramid, comprising only one combinatory circuit. Preferably, the different successive stages constituting the transcoder device are interconnected by means of flip-flop registers, with parallel inputs and outputs, all of the registers being connected to a common generator of clock signals.

• - la figure 1 est un schéma général d'un additionneur rapide conforme à la présente invention, et
• - la figure 2 est le schéma détaillé du dispositif transcodeur de la figure 1.

The present invention will be better understood with the aid of the detailed description of an embodiment taken as a nonlimiting example and illustrated by the appended drawing, in which:

• FIG. 1 is a general diagram of a fast adder according to the present invention, and
• - Figure 2 is the detailed diagram of the transcoder device of Figure 1.

The fast adder represented diagrammatically on the figurel is intended for the simultaneous addition of 127 words for example, each comprising a large number of binary elements, for example 32. However, it is understood that the number of words that the it can be added together may be different, and that the words may contain a different number of binary elements, the modifications to be made to the device of the invention being obvious to those skilled in the art on reading the presence description.

The adder of FIG. 1 comprises, on the input side, p shift registers, respectively referenced 1 to 1 _P , p being the number of words to be added together, 127 in the present case, these registers for example each comprising 32 cells if the maximum number n of binary elements of the words to be added is 32. The words to be added together can be introduced into these shift registers either in serial mode or in parallel mode depending on the configuration of the circuits connected upstream of the adder.

The serial output of each register 1 ₁ to 1 ₁₂₇ is connected to a corresponding input of a transcoder 2 described in more detail below. In the case of the addition of 127 words, the transcoder 2 has seven outputs of respective binary weights 2 to 2. The different outputs of transcoder 2 are connected, through the intermediary diary of a register 3, to a series of corresponding inputs of the same weight of a binary adder-divider circuit 4 which can for example be produced in a manner known per se using two integrated circuits 74283 from Texas Instruments. Register 3 is with parallel inputs and outputs and is, for example, typically made up of eight D-type flip-flop cells, one of these cells being unused.

The weakest point output of the adder-divider circuit 4 is connected to the serial input of a shift register 5 comprising a number of cells sufficient to contain all the binary elements of the result. For the aforementioned example of the addition of 127 words of 32 binary elements each, it is easily demonstrated that the result comprises a maximum of 39 binary elements. Register 5 will then be a standard 40 cell register.

The other outputs of the adder-divider circuit 4 are respectively connected to another series of its corresponding weight inputs via a register 6 with parallel inputs and outputs, of the same constitution as register 3.

We can have the result of the addition either on the serial output S of register 5, as and when the calculation operations described below, or on the parallel outputs S ₁ to S of register 5 at the end calculation operations.

The circulation of information in the shift registers 1 ₁ to 1p and 5, as well as the transit in the registers 3 and 6 are controlled by a clock signal arriving at terminal 7 which is connected to the input CK of signals d clock of all these registers.

FIG. 2 shows the detailed diagram of the transcoder device 2 in the case where 127 words of 32 binary elements each have to be added together.

The transcoder 2 comprises, on the input side, a first stage with eight elementary transcoder circuits respectively referenced 8 to 15. These transcoder circuits, for example FPLA (programmable logic networks) of the 82S100 type from Signetics with sixteen inputs, being programmed to supply each on its five outputs the value, in pure binary, of the total number of "1" present on all its inputs. The inputs of these transcoder circuits are respective ment referenced E ₁ to E ₁₂₇ , the last input of circuit 15 not being used.

The outputs of each time two transcoder circuits are grouped and connected, by means of flip-flop registers of type D, 16 to 19, to corresponding inputs of four adder circuits of a second processing stage, respectively referenced 20 to 23. Each of these four adder circuits provides the sum of its two input values from two corresponding transcoder circuits on its outputs. The outputs of the adder circuits 20 to 23 are also grouped for each time two adders and connected, via two registers 24 and 25, to corresponding inputs of two other adders 26, 27 forming the third processing stage, and finally the outputs of the adders 26 and 27 are connected via two registers 28, 29 to corresponding inputs of an adder 30 forming the last processing stage of the transcoder device and supplying the value on its seven outputs 31 to 37, pure binary, of the total of "1" of the same rank which were present simultaneously on the 127 inputs E to ^E ₁₂₇ ,

The clock signal inputs of all the registers are connected to a terminal 38 which is itself connected to terminal 7.

It will be noted that the conformation of the transcoder device of FIG. 2 is due to the use of elementary trancoder circuits 8 to 15 with sixteen inputs each, the most efficient currently available, and that, of course, if transcoder circuits were available at 128 inputs, the device in FIG. 2 would be reduced to a single such circuit. However, the pyramidal structure in stages in accordance with the invention can still be used when it is desired to add together a number of words greater than the number of inputs of the available transcoder circuits. It will also be noted that the outputs of the transcoder circuits and of the adder circuits can be grouped in a non-symmetrical manner, provided that the weights of the different outputs and inputs of the transcoder or adder circuits are respected.

The different registers of the transcoder device 2 are not absolutely necessary, but it is preferable to use them. to properly synchronize the operation of the different stages of this transcoder device.

The adder described above operates as follows: the words to be added together are stored in the input registers 1 ₁ to 1p (p = 127 in the above example), the least significant binary element (2 ⁰ ) of each of these words being available at the input of the transcoder device 2. On the outputs of each of the circuits 8 to 15 are available the value in pure binary of the total of the "1" of weight 2 ⁰ present at the entrance. At the first rising edge of the clock signal arriving at terminal 38, these values are transferred to the adders 20 to 23 to be added there in pairs. On the second rising edge of the clock signal, the four partial sums supplied by the adders 20 to 23 arrive at the adders 26 and 27, the two partial sums of which reach the last adder 30 at the third rising edge of the clock signal, the adder 30 immediately providing to the input of register 3 the value in pure binary, the total of "1" of weight 2 ⁰ words present in the input registers 1 ₁ to ¹ _127.

Said first edge of the clock signal not only transfers into the adders 20 to 23 the results supplied by the transcoder circuits 8 to 15 for all the binary elements of weight ²⁰ of the words to be added, but also presents the inputs E to E ₁₂₇ binary elements of weight 2 ¹ which follow the same treatment as binary elements of weight 2 ⁰ , and so on up to binary elements of weight 2 ³¹

The fourth rising edge of the clock signal transfers into the adder-divider 4 the first useful content of register 3, that is to say the value of the total of "1s" of weight ²⁰ of the words to be added. The adder-divider 4 adds this value to the output value of register 6, which is zero because at the start of the addition of the words there is no reserve, register 6 having been previously reset so as to appropriate, then proceeds to a shift of one step to the right (towards the least significant binary elements) of this value, that is to say that it realizes the division by 2, then it sends in the register 5 the least significant binary element after shift, namely the fraction part nary (2) of the result of the division and sends to register 6 the other shifted bits. This means that the adder 4 performs the half-sum of the value of the total of "1" of the binary weight considered and of the value of the total of "1" of carry, sends the fractional part of this half-sum in the register 5 and send the entire part to register 6 of deductions.

On the fifth rising edge of the clock signal, the value of the total of the elements of binary weight 2 ¹ of the words to be added reaches the adder-divider 4 from the adder 3, and simultaneously, the register 6 sends it the value of the total deductions for binary items of weight 2 ⁰ . The adder-divider 4 performs the sum of these two values, then divides it by two, sends the fractional part of the result in register 5 and the whole part in register 6. This processing continues thus until the thirtieth -th fifth rising edge of the clock signal which commands the addition of the value of the total of "1" of weight 2 ³¹ to the total of the deductions relating to "1" of weight 2 ³⁰ , then the division by two of this sum, sending the least significant binary element to register 5 and sending the total of the deductions to register 6. Then, no more "1" can arrive from register 3 in the adder-divider 4, if we assume that no other word is no longer loaded in the input registers 1 ₁ to 1127. Therefore, at from the thirty-sixth rising edge of the clock signal, only the retained flows circulate between the register 6 and the adder-divider 4. It can easily be demonstrated that the maximum value of the total of the "1" of retention arriving from the register 6 to the adder-divider 4 at the thirty-sixth rising edge is 126. Consequently, all the carry 1s will be exhausted at the latest after the forty-second rising edge of the clock signal. If we take for example a clock signal at 16 MHz, that is to say with a period equal to 62.5 nanoseconds, the addition of the 127 words of 32 binary elements each will be completed in 2.6 µs, approximately , which is entirely compatible for example with the maximum permitted processing times for digital filters used in MIC telephony, and significantly less than the processing time for conventional adders of the same capacity.

) en supposant que l'on utilise des circuits transcodeurs élémentaires à 16 entrées.In general, we can easily demonstrate that if we proceed with the addition of p words each comprising n binary elements the addition will be completed at the latest _in : n + r + s periods of the clock signal, with: 2 ^r ≤ p <2 and s = Log ₂ (

) assuming that elementary transcoder circuits with 16 inputs are used.

We will now verify using a simplified example of binary addition that the operation of the adder of the invention is correct. We will limit ourselves to the addition of four words a, b, c and d of five binary elements ("bits") each, namely: 11110, 01010, 01111, 01111, which makes in decimal: 30, 10, 15 and 15 respectively. We will place these four words in the middle part of a table, the upper part of which is reserved for deductions and the lower line for results. The addition will be made in a known manner analogous to that used to make written additions in the decimal system.

To carry out the addition, one writes, one below the other the four words a to d, the bits of the same weight being in the same column, and they are added mentally column by column starting with the weight the lowest and by carrying a carry-over in the higher weight column each time two "1s" are added. For the weight column 2 ⁰ , there are two "1" and there is of course no deduction from a pre column cedent. We therefore write on a result line a "0" and we carry a single deduction in the weight column 2 ¹ .

In the weight column 2 ¹ , there are four "1" from the four words and a retaining "I", which makes a total of five "1". We must therefore carry two "1" retainers in the weight column 2 ² and write a "1" for the result in column 2 ¹ . One proceeds thus on for all the other columns, and one finds as result: 1000110, that is to say 70 in decimal notation, which is indeed the sum of 30, 10, 15 and 15.

By analyzing this way of adding, we notice that in each column the binary element of the result is a "0" when the number of "1" of the words and of the retentions is even and a "1" when this number is odd, and that on the other hand the number of "1" withholding is equal to half the number of "1" in the previous column when this number is even, is half the number immediately below when the number of "1" is odd, which means that the number of "1" retainers is equal to the integer part of half the number of "1" words and retainers in the previous column, and that the binary element of the result is equal to the fractional part of this half. We can easily verify that this rule is valid in all cases. Consequently, the process for processing binary words described above makes it possible to effectively obtain the sum of these words, and the device for implementing this product works correctly.

Claims (5)

1. Method for processing binary words, making it possible to simultaneously add a large number of such words, these words being each stored in a shift register and extracted at the serial output of these registers, characterized by the fact that we sequentially extract all the binary elements of the same weight starting with those of the lowest weight and progressing in order towards those of the highest weight, that we determine each time the number of "1 "among all the binary elements of the same weight, that we add, for each considered weight of binary elements, the number of" 1 "of retention relative to the binary elements of immediately lower weight, which we calculate the half sum of these two numbers, that we send a "1" in a shift register when this half-sum is not an integer, and a "0" otherwise, that we store a number equal to the integer part of this half-sum and that we extract this last number in t ant that number of "1" deductions for use when calculating the immediately following half-sum. 2. Method according to claim 1, using transcoder circuits with sixteen inputs for the addition of p words each comprising n binary elements, characterized in that the addition of these p words requires at most n + r + s periods of clock signal, with 2 ^r <p <2 ^{r + 1} and s = Log2 (

). 3. Adding device for implementing the method according to claim 1 or 2, characterized in that it comprises a transcoder device (2) whose different inputs are connected to the serial outputs of the different shift registers (1 ₁ . .. 1 _p ) in which the words to be added together are memorized, this transcoder device being produced so as to present on its outputs the value, in pure binary, of the number of "1" present on its inputs, the outputs of this device transcoder being connected by means of a flip-flop register (3) to corresponding binary weight inputs of a parallel binary adder-divider circuit (4) itself connected to a storage register for the sum of the deductions (6), the least significant output of this adder-divider circuit being connected to the serial input of an output shift register (5). 4. Adding device according to claim 3, characterized in that the transcoder device has a pyramidal structure with several processing stages, the input stage, at the base of the pyramid, comprising in parallel several elementary transcoder circuits (8 ... 15) each supplying on its different outputs the value, in pure binary, of the number of "1", for each binary weight of all the words arriving on all its inputs, the outputs of at least two different transcoder circuits being grouped each time at the input of an adder circuit (20-23), several stages of such adder circuits being arranged in cascade, the last stage, at the top of the pyramid, comprising only one adder circuit (30 ). 5. An adder device according to claim 4, characterized in that the different successive stages constituting the transcoder device are connected by means of flip-flop registers, with parallel inputs and outputs, all of the registers being connected to a common generator. clock signals.

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