DK175639B1 - Subscriber equipment for wireless digital telephony - has control and MODEM processors directly coupled in assembly containing CODEC and universal transmitter receiver - Google Patents

Abstract

A base-band processor provides control of conversion of PCM signals at one bit rate to other bit rates. It converts received digital signals to voice signals and vice versa. It also provides echo cancellation where it uses dynamic memory to store received signals. PROM's store the echo cancellation program information as well as that for utilisation of the processor as a control processor. As a control processor it signals to the frequency synthesiser the frequency of operation for communication to the base station. The processor is directly coupled to a modem processor which is able to access the base band processor memory. This processor sends its signal at a predetermined sampling rate which are converted to analogue signals. The analogue signals are subjected to a cancellation process to reduce distortion. These signals are converted to an IF for addition to the synthesiser frequency to result in an HF signal for transmission.

Description

in DK 175639 B1

The invention relates to a subscriber system unit for a digital wireless telephone system, wherein the subscriber unit is arranged to communicate wirelessly with a base station. The subscriber unit has a baseband processor 5 that performs a number of functions including transcoding incoming and outgoing signals from one type of bit streams to another and providing echo cancellation. It also acts as a control microprocessor for e.g. informing a synthesizer with respect to the 10 desired frequency of operation to be used. It is additionally coupled to storage means for receiving and storing the various functions thereby performed or received.

The baseband processor is coupled to a modem processor to which it is coupled with a direct access means which prevents simultaneous access of both of these processors, but the two processors are interconnected and the modem processor acting as the master of the system has access to the baseband processor 20 memory through the direct access means. However, exclusion means are provided whereby the control of the baseband processor by the modem processor is prevented in certain circumstances.

The modem processor sends its signals at predetermined sampling frequency through a frequency-translated complex signal that is converted to an analog signal. This analog signal is subject to interlocking by a blanking process. The intercepted signal is then converted and filtered to generate an IF signal which is then amplified. The frequency of the amplified IF signal is added to a frequency generated by the aforementioned synthesizer and the resulting RF signal is amplified and fed to an antenna.

The subscriber unit uses constantly repeated frames in which it transmits in one part of each frame and receives in another part of it, where these parts are designated

I DK 175639 B1 I

I I

In as "slits". On the basis of certain signals that

is taken from the base station, generates baseband process I

soren start signals that determine whether the subscriber unit H

You will be in transmit mode or receive mode. IN

5 I Intervals between the activation of the system I

You use a setting mode in which a known I

The signal from the modem processor is compared to a back I

In guided signal to produce correction condition I

In which compensation for unwanted variants is obtained

In 10 tions of the IF signal due to variations in temp

In rature, component values, etc. The correction constants I

stored for use in correcting actual reception I

In ne signals. H

During demodulation, the demodulated digits are kept

In 15 speech signals to the modem processor in the form of time multi- I

You plexed I and Q samples and demultiplex. Oh demulti- I

plexed I and Q samples are passed to one. compensatory and I

In frequency correction circuits to minimize errors,

In which results in the generation of frequency correction I

In 20 tions signals used to correct any H

errors in system timing and in synthesizer output sig- I

I nal

The invention is explained in more detail below

Referring to the drawing, in which:

In FIG. 1 shows a diagram of a subscriber unit I

In accordance with the invention, I

In FIG. 2 is a block diagram of the modulator portion of the one in I

FIG. 1, the modem processor shown in FIG

In FIG. 3 is a block diagram of the DPSK turnover unit I

In FIG. 2, I

In FIG. 4 shows the structure and function of the device shown in FIG. 2

In the FIR filter shown, I

In FIG. 5 is a block diagram of the embodiment of FIG. 1

In interpolator, I

In FIG. 6 is a block diagram of the embodiment of FIG. 1

In synthesizer, I

In FIG. 7 is a modified embodiment of the embodiment of FIG. 1 vi- I

3 DK 175639 B1 unit entrance part, fig. Fig. 8 is a block diagram of the demodulator portion of the modem processor shown in Fig. 1; 9 is a block diagram of the embodiment of FIG. 8 shows the coarse frequency control module; FIG. 10 is a block diagram of the AFC and symbol timing module shown in FIG. 8th

WORD LIST

10

Glossary of acronyms and words used in the description.

ACRONYM Definition.

15 A / D Analog / Digital Converter ADJ Adjustment Input 20 AFC Automatic Frequency Control AGC Automatic Amplifier Control BLANKING Controls that hold the signal 25 at a predetermined amplitude level during the activation of the controls CODEC Combined Codes and Decoders 30 CPE Customer Acquired D / Phone Equipment A Digital / Analog Converter DPSK Differential phase shift modulation in 35

DK 175639 B1 I

DS Data Selection H

EEPROM Electrically Erasable Programmable H

reading storage H

EPROM Erasable Programmable Reading Bearing H

FIFO First-in / First-Out Memory H

10 FIR Determined impulse response H

GLITCH Unwanted Transient Signal I

HOLD Idle mode H

In Phase I

IF Medium Frequency H

20 kbps Kilobits per second H

nS Nanosecond H

PAL Programmable logic unit H

PCM Pulse code modulation PROM Programmable reading memory

30 PSK Phase Shift Modulation I

Q Square I

RAM Direct Access Storage I

35

REDP Residual induced linear prediction I

5 DK 175639 B1 RF Radio Frequency R / W 'Read / Turn 5 S / H Sample and hold SLIC Subscriber loop interface circuit 10 STROBE Sampling signal UART Universal asynchronous receiver / transmitter VCXO Voltage controlled crystal oscillator 15 XF External flag output used for signaling

The invention relates to communication systems for wireless transmission of multiple information signals using digital time sharing circuits between a base station and one or more subscriber stations, and in particular relates to the construction and function of such a subscriber station.

25 Referring now in more detail to the drawings, wherein like reference numerals refer to like parts, FIG. 1 shows a connector 10 for connecting the customer-acquired equipment, CPE.

A line pair 12 leads from connector 10 to a SLIC 14 and can also be connected to a ring circuit 16 through a relay 18. The SLIC 14 is a standard chip for performing various functions such as battery voltage, surge protection, ringing, signaling detection, e.g. from a turntable, microtele phone status, line testing and so on. It also contains the hybrid circuit that separates a number of speech messages.

DK 175639 B1 I

clay 1 incoming and outgoing signals. The SLIC 14 is

coupled to a large CODEC 20 that has incoming and outgoing I

walking lines to and from a baseband processor 22, wherein

it translates in the inbound direction analog speech signa- H

5 clay for digital signals, i.e. 64 kbps μ-law PCM, I

while in the outgoing direction it converts digital H

signals for analog speech signals. It can sometimes

be desirable to bypass CODEC one so that you

The SLIC 14 is connected directly to the baseband processor 22. H

10 There is an alternative approach to the baseband processor I

through a connection 24 and a UART 26 providing I

brings a direct digital connection to baseband I

the processor, thereby bypassing the SLIC and CODEC. This one

direct access connection serves two purposes: (1) Only that I

15 allowing the digital signals to pass, when desired, I

thereby diverting all analog connections, and (2) adding

allow direct access to the processors and storage with I

for easy maintenance and testing. IN

The baseband processor 22 has several functions, of I

20 which is to convert the 64 kbps PCM signal to 1

14.57 .... kbps using a transcoding function, I

such as e.g. provided by residual excited linear

prediction, RELP. It also provides echo removal I

and additionally acts as a control microprocessor, e.g. IN

25 by informing the synthesizer used in system H

met with respect to the desired frequency of work. Basis-

the tape processor 22 is coupled to a self-contained memory

melschip 28, as well as for a series of EEPROM 30 which is H

an electrically erasable, non-volatile warehouse where you selected

30 bits can be electrically erased without the other bits being

is stored in the delete. This EEPROM 30 is used for H

storing both the subscriber identification number and the network

the work identification number, {the base station it uses- I

is given in conjunction with.) In addition, the baseband processor fl

35 22 coupled to a full-speed RAM 32 in which it is

stores the signals received in it. The RAM 32 I

7 DK 175639 B1 also contains a "custodian" and is also used as a stock with direct access for RELP conversion, echo removal and other functions. The baseband processor 22 is also coupled to a half-speed EPROM 34 and full-speed PROM 36, which stores the RELP and echo removal functions, as well as various other functions, such as the control function. The baseband processor 22 is additionally coupled over a direct memory Ises approach 38, DMA, to a modem processor 40.

The DMA 38 prevents the occurrence of simultaneous access to RAM 32 by both the baseband and modem processor.

The DMA interface is used to transmit speech and control signals between the base and modem processors. The modem processor 40 acts as a master and controls the baseband processor 22 over hold lines not shown. Modem processor 40 can access baseband processor 22, stop its processing, and cause control lines, address and data buses to assume a three-state output high-20 mode. This allows modem processor 40 to access the baseband processor DMA memory through the DMA interface and to read or write in it.

This is done by modem processor 40 applying its XF bit, which is fed to the baseband processor 25 holding input. When the baseband processor receives this command, it will terminate the execution of the running instruction, halt its processing, cause its control data and address buses to adopt a three-state output high impedance to the tooth, and then send a hold-back signal to the modem processor. Immediately after the modem processor issues the hold command, it will continue with other tasks while waiting for the baseband processor to send the hold confirmation signal. Once the modem processor receives the hold confirmation signal, it takes control of the baseband processor's control, data and address buses and then reads or writes in the DMA RAM 32.

I DK 175639 B1 I

IN

In the modem processor has completed its approach to DMA I

The RAM removes the holding input of the baseband processor

clean, which then resumes treatment where it left off.

The baseband processor also has the ability to exclude I

H 5 modem processor by setting its own XF bit high.

I This bit is blocked with the hold signal from the modem processor

You can clean and can override the hold line at any point before

In the baseband processor goes into hold mode. Modem Process- I

In the sore, 10 of the address bus uses bits and all data H

In the 10 bits of the bus. It also uses 3 guide lines: STROBE, I

In R / W and DS. IN

In either the baseband processor 22 or the modem processor,

the signal 40 acting in both directions may receive signals I

I from RAM 32 in accordance with Ise with the signals described above. The two processors are connected

In each other by means of a portion of the RAM 32 which is real

In served for use as a custodian. Modem Processors I

40 is also coupled to a full-speed PROM 44 which I

contains the program for this processor. IN

In the modem processor 40, in its modulation array transmits I

In picking position its signals via a FIFO 46 to an in- I

In terpolator 48, where these signals have a junction frequency H

In friend's 320 kHz. Interpolator 48 increases this in practice

In aggregate frequency by a factor of 5 to convert it to I

25 1600 kilosamples / second (1.6 megasamples / second). In- I

In the terpolator approximates in cooperation with the crystal filter, H

In what will be described later and which seems like an integral

In grator, effectively a 5-pole FIR filter. This application I

In providing digital and analog hardware for realization

In 30 of an FIR filter differs from the classic hero I

In digital realization of a hardware FIR. Interpolator I

At the output, a PAL 50 is passed

In the PAL is designed as a kind of mixer, to which a 400 kHz square wave, as shown by

I 35 50 coming from a timing generator 51, as well as 1600 I

In the kilosample / second signal. 1600 kilosample / second- I

The signal represents a 1600-chlose symbol / second PSK signal with a zero carrier and a desired 20 kHz bandwidth. In reality, the PAL can be considered a frequency translator. The PAL circuit, when configured to perform a complementary function of a 2, controlled by a 400 kHz square wave, 1 practices a time-multiplied quadrature mix and sets 1 in practice the 20 kHz broadband signal up to 400 kHz.

The output of PAL 50 is a time-multiplexed, frequency-translated complex signal that is applied to the D / A converter 52 which converts the digital signal to an analog signal. The output of D / A converter 52 is fed to a mixer 54 to which a deglitching / blanking pulse 56 is also fed from a blanking generation module 58. Glitch energy is the largest contribution to noise in a sampled data system. Glitch energy occurs during the transition from one input word to another. In a large D / A converter, each incoming bit, depending on its state, can cause a change in the output analog level.

Such changes resulting from the various bits generally do not occur simultaneously and therefore cause glitches. Classic solutions to this problem are the use of a sample and hold function after the D / A or the use of a de-glitching D / A. However, both of these alternatives are unreasonably expensive. "Blanking" leads the output signal from the mixer to an intermediate reference level during the transition periods, typically approx.

35 nS before and 130 nS after the digital switching times, thereby suppressing large glitch peaks occurring 30 on the D / A output. Although blanking creates harmonics outside of the interesting center frequency, the use of relatively narrow IF filtering essentially eliminates these harmonics. This blanking method also reduces the sampling frequency content of the output signal 35. The output signal indicated at 60 from mixer 54 is fed to a mixer 62 in a converter which as a whole

I DK 175639 B1 I

I I

The heat is designated 64. The mixer 62 has a 20 MHz-I

In Entrance indicated at 65 and shared by an H

In 20 MHz line 66. The output of mixer 62 is I

the sum of 20 MHz from the Input 65 and the 400 KHz input I

In 5 nal received from mixer 54, with a resultant I

In output signal of 20.4 MHz. This output signal is fed

I to a crystal filter 6Θ that only lets this sum that you

You constitute the IF signal, pass to an amplifier 70. I

I A synthesizer is shown at 72. In this synthesis I

In Fig. 72 there is a synthesizer module which provides I

an output signal L01. In the synthesizer module, one extracts

second circuit also a second output signal L02, wherein I

In the L02 output signal, the L01 output signal follows an I

At a frequency of 5 MHz below the frequency of L01. Synthesize- H

For reference, the reference uses the 80 MHz VCXO for reference. Initial screen I

The needle L01 is passed through the line 74 to a mixer 76 which

You also receive the IF output of amplifier 70. I

Since the IF signal has a size of 20.4 MHz, I

the synthesizer is served if, e.g. a fre- I

In the 20 frequency range of 455.5 MHz at the output of mixer 76, I

generate a frequency of 435.1 MHz added to them

20.4 MHz gives the desired frequency of 455.5 MHz. This I

output signal is then amplified by an amplifier 80 with I

variable gain. The baseband processor 22 transmits I

25 on the basis of decoding certain signals from base I

the station receives a gain control signal on line 81

Easily a D / A converter 82 to amplifier 80 of variants

bell reinforcement. Variable I amplifier 80

amplification has a limited bandwidth and lets it

30 for undesired differential frequencies that also produce I

brought by mixer 76, pass. The output of I

amplifier 80 is routed along line 83 to a power amplifier

strengths 84 which effect the final reinforcement before I

The RF signal is passed through a relay 86 to an antenna 88. I

The device uses a system by which a frame I

is repeated every 45 milliseconds. In this system, I

11 DK 175639 B1 which receives the unit during a portion of the second half of each frame and receives during a portion of the first half of each frame. There may be a design in which both parts of the halves have the same length, although they must not necessarily be equal. Another embodiment may be hexadecimal, with four parts of the same length available to the subscriber under a whole frame. Each of the four parts can be referred to as a slot. Each slot contains, as part of its initial data, a unique word used by the device to create timing for receiving the remaining data into the slot. Prior to the first of the four slots, there is an AM hole used to determine a slot which is arbitrarily referred to as the first 15 slot. The AM hole and the unambiguous word are parts of the incoming signal from the base station. The duration of the AM hole is used to determine whether a particular RF channel is a control channel or a voice channel.

A data signal is derived from the average size 20 of the signal represented by 116. A threshold proportional to said average size is compared to non-leveled sizes. If the threshold is not exceeded by the non-leveled size for a predetermined period of time, it is assumed that a large 25 AM hole is detected. Modem processor 40 stores the time at which the AM hole was determined to occur in RAM 32.

The baseband processor produces on the basis of (a) modulation mode, quartets or hexadecimal, (b) the time at which the AM hole appeared, as stored in large RAM 32, and (c) the time at which a unique word was received, as separately determined by the baseband processor, start signals indicating when the unit should be in a transmit state or a receive state. Such starting signals are coupled over line 90 to a frame timing module 91.

I DK 175639 B1 I

I I

In the Frame Timing Module 91, the start signals are converted

In to 2 pulse serls. One impulse series is coupled over H

line 92 for activating the power amplifier 84 and H

I for activating relay 86, so as to disable I

In the 5-way amplifier 84 to the antenna 88. In the time that you

In pulse on line 92, the unit is arranged to be H

In re in transmit mode. When relay 86 is not activated on I

In this way, it is arranged to couple the antenna 88 to I

In the preamp 94's input. H

I 10 The second series of pulses from the frame timing module H

In 91, the line 93 is connected to an amplifier 94 in order to

In activating this amplifier. The unit is intended to H

You are in the receiving state during this series of impulses. For- H

In the amplifier 94, received signals lead to a mixer H

I 15 96, which also receives the output signal L02 from synthesis I

In zone 72 through line 98. The output of mixer H

In pure 96, a crystal filter 100 whose output I

In signal is applied to an IF amplifier 102.

Modem processor 40 leads via line 89 to the first H

In said data signal derived from average magnitude I

Late of the signal, represented by 116, to a D / A about-I

You set 104 which produces an analog AGC voltage I

In signal passed through a line 106 to an amplifier I

H 102 and thereby to this amplifier indicates where I

In 25 much reinforcement required to compensate the sole

In that the IF signal always has the same amplitude. This one

The amplifier also receives the output signal from the crystal I

In the filter 100. The output of the amplifier 102 is fed

Into a mixer 108 to which an input is also introduced

H 30 signal 20 kHz signal from line 109 for generation I

of a resulting 400 KHz signal. This 400 KHz signal I

is then fed to an A / D module consisting of a sample I

and holding circuit 110, an A / D converter 112 and FIFO 114. I

The output of the A / D turnover module is 64

In 35 chlorosample / secxind and this output is passed through I

the line 116 to the modem processor 40. The modem processor 40 I

B1 demodulates this signal and passes the demodulated data to the repository portion of RAM 32, which is accessed for the baseband processor 22 in which the RELP conversion takes place. The resulting output has 24 kbps PCM on a continuous serial basis. This output signal is fed to the CODEC which converts it to an analog signal which is then fed to the SLIC which in turn transmits it to the telephone; or alternatively, the 16 kbpc from the repository can be decoded to a digital signal which is fed to UART1 en 26.

Used in the setting state, at line 118 a return is provided between two relays 120 and 122. This return, which is at the IF side rather than at the RF side, reduces the number of required 15 elements. The setting state is that in which a known signal of the modem processor is output through the remainder of the transmit element set to IF amplifier 70. Because relays 120 and 122 are activated, the output of amplifier 70 is coupled to the input of crystal filter 20 100.

In addition, an output indicated by line 90 from the baseband processor 22 is connected to frame timing 91 and causes a pulse on line 93 to completely deactivate amplifier 94 during the exercise state. Further, during tuning mode, frame timing 91 produces a second pulse on line 92 rendering amplifier 84 completely inoperative. The known signal produced by the modulator is compared to the present signal which is fed back to the modulator. An utility is then set up to compensate for variations due to various factors such as variations in temperature, component values and so on. The correction constants are stored in RAM 32. The modem applies the received signals to these stored corrections. The setting state occurs in the spaces between system activation.

I DK 175639 B1 I

I I

In Synthesizer module 72, an 80 MHz contains

dilator, VCXO derived from the received signal. 80 MHz-I

The signal produced by the oscillator passes through I

In a line 124 to a 4-part circuit 126 whose output I

5 pass signal goes to mixers 62 and 108. This output I

In signal, the two processors are also provided

In bringing clock pulses, square waves. Furthermore, you run

In it through a line 124 to a 5-part circuit 130 and I

Then to the timing module 51. The modem processor determines H

In 10 any difference in frequency between the center frequency and one

In the submultiple of the beat frequency. IN

Any resulting difference is caused by modem pro- I

the processor over a line 132 to a D / A converter 134. Out- I

The pass signal from D / A converter 134 is passed over a line

I 15 nie 136 and an ADJ input 138 to the VCXO which later I

must be described in such a way as to alter its I

In frequency in the direction required to minimize it

In prior resulting difference. A locking tab- I

In a tector signal, a line 140 is passed to the baseband

In the processor 22 to indicate when a loss I occurs

I of the sync in the synthesizer.

Modem processor 40 comprises, as shown in Figure I

In 2, a large DPSK converter 150 to which data is fed

through a line 162. The data is then fed at 16 kHz of acid

At 25 bol / second frequency for a large FIR filter 154. Out- I

In the start signal from the FIR filter 154 indicated by

In 156, asynchronous data comprising 10 complex samples / I

In symbol, time multiplexed IQ pairs. This output signal I

is fed to the FIFO 46 described above, where

H 30 there is a turnover from asynchronous to synchronous place. Out-

The signal from the FIFO 46 is in the form of 160,000 I

pairs of data words / second to the above-described inter-

polator 48, it multiplexes the IQ pairs and remultiplex I

sees the IQ samples at a frequency of 1.6 MHz. IN

H 35 In a hexadecimal modulation scheme, it is divided by

close Input sequence up into 4-bit symbols. In hexadecimal I

15 DK 175639 B1 PSK determines the 4-bit symbols phase of the carrier during the given symbol period. The conversion of the binary input signal to the PSK waveform is performed by the modulator.

Figure 3 shows how a sequence of sampler S shown at 160 is transformed into a sequence of sampler in phase I and quadrature Q in modem processor DPSK converter 150 of modem processor 40. The symbols are first inverted Gray-coded as shown at 162. This is done to minimize the number of bit errors that occur as a result of the most likely incorrect symbol determination in the demodulator.

The output of the inverted Gray encoder 162 is applied to a phase quantizer 164 which determines the absolute phase value 0 entered by the current symbol.

This phase value is then passed to the differential encoder 166 which calculates the absolute phase value dj *. 6J 'represents the modulo 16 sum of the current differential phase 0 and the previous phase 0 / - f.

20 0 / '= (0 / + 0 - /') MOD 16

The modulo 16 addition is similar to the modulo 360 addition that is performed when angles are added together.

The differential phase Θj 'is introduced into cosine and sine lookup tables to calculate the power symbol I-Q-25 components.

The I and Q samples are fed to the six-coil filter 154 with a specific impulse response, FIR, which is further shown in Figure 4. The function of the FIR filter is to create an oversampled PSK waveform from the I and Q samples. The Q-sam-30 piers are fed to a bank of 10 six-coil FIR filters labeled "h ^, j" (j = 1-10). Similarly, I samples are fed to a bank of 10 filters labeled "hgj". These 20-filter outputs signal the time multiplex as shown on a single parallel bus running at a sampling frequency that is 10 times the sampling frequency of the I, Q pairs at the input of the filter.

DK 175639 B1 I

Interpolator 48, shown in more detail in Figure 5, H

includes an input 180 and a relay 182 coupled H

to the PAL 50 at a line 183 where the relay 182 may be H

alternate between Entrance 180 and Line 184. Optional H

5, a multiplier 185, H may be inserted in line 183

which can be used for multiplying input slots -

clay from line 183, as well as an optional Entrance H

signal 187 that can be applied from the modem processor or H

or from any desired help repository. Relay 182 H

10 is connected to PAL · 1 and 50 by line 183, and

line 184 leads from I - 'memory 186 having an input H

188 from the Q repository 190. A 1.6 MHz input signal provides H

be provided to both the I / Q and Q / I storage, as indicated by H

192 and 194. The interpolator demultiplexer H

15 the multiplexed I, Q samples at a frequency of 160 kHz

and resamples and remultiplexes thereon at a frequency H

at 800 kHz. IN

Synthesizer 72, which is functionally described- H

know above, is shown in Figure 6, where an H is shown

20 VCXO module 200 receiving a signal from ADJ input

138. This input controls the exact frequency I

of the VCXO module. The output of the VCXO module is over a line H

202 connected to a synthesizer 204. This synthesizer H

204 is capable of synthesizing frequencies between H

25 438.625 and 439.65 MHz 1 due synchronization with signa- H

above the line 202. The special frequency is selected H

by means of an input signal over line 128, such as H

is also shown in Figure 1. I

The output signal of synthesizer 204 is passed over an H

30 line 206 and a filter 208 to become LO1. Ut- I

the signal from the synthesizer 204 is also passed over one

line 210 to a synchronous translator 212. Output signal- I

lightly from the VCXO 200 is passed through a line 214 to an I

module 216, dividing by 16 if 5 MHz output sig- I

35 nal is passed through a line 218 to the synchronous upper

switching module 212. The output of line 214 is connected I

also to a reference output 221. H

17 DK 175639 B1

The module 212 subtracts the 5 MHz input signal on line 218 from the frequency on line 210 and provides a differential frequency passed over a filter 220 to become L02. In this way, the frequency acting as L02 varies between 433,625 and 434.65 MHz, with the frequency of 1.02 always being 5 MHz below the frequency of L01.

In addition, the output of the synthesizer 204 over the line 222 and the output of the 10 synchronous translator 212 are combined over the line 224 of the synchronization detector 226 in such a way that if either the frequency of the line 206 is not synchronous with the frequency of the line 202 or the frequency of the synchronous translator 212 is not synchronous with the combination of the frequency on line 206 and the output frequency of module 216 divided by 16, a synchronization loss signal, locking loss, is transmitted on line 140, also shown in Figure 1.

The particular combination of a synthesizer 204 plus the module 216 divided by 16 and the synchronous translator 212 provides the same function as the two separate synthesizers used previously, but with fewer parts, greater stability, easier tolerances, and so on.

Figure 7 shows a preferred circuit for testing the subscriber interface. For this purpose, the modem processor 22 shown in Figure 1 generates a 1 kHz sine wave which is fed to the codec 20 shown in Figure 1 which converts it to an analog sine wave which is passed through the SLIC 14 to the line pair 12. A relay K not shown in Figure 1 is introduced immediately adjacent to the subscriber 10 so that it can disconnect the connector from the circuit. Any reflected signal from the unfinished line pair 12 at open relay K 35 is passed through the hybrid function to the SLIC and converted into a digital signal by the codec 20. This digital

I DK 175639 B1 I

I 18 I

In signal, to the baseband processor 22, which together H

You are similar to the reflected signal with the original sig- H

nal and determines whether any unwanted Impedances or H

In compounds, e.g. earth, is present on the line pair H

B 5 12.

Figure 8 shows the demodulator portion of the modem processor.

pure 40 and shows the 400 kHz output signal from the H

In mixer 108 shown in Figure 1, high precision I is introduced

In the sample and holding circuit 110, which has an opening failure

For 10 times 25 nanoseconds or less, and if out- H

Input signal is fed to the A / D converter 112. Output signal I

Lightly from A / D converter 112 is passed through line 118 to I

In the modem processor, all as shown in Figure 1. Input sig- I

In the needle at line 116, time multiplexed I and H comprise

In 15 Q samples that may have some cross product distortion, H

In the form of two complex sample pairs / symbol. They mentioned H

In time-multiplexed I and Q samples, demulti- H is fed

In the plexer 298, where they demultiplexed. The demultiplex- H

In Seated I and Q samples, an equalizer module 300, H is fed

In 20 whose purpose is to minimize (a) the failure energy of the counter- H

In taken data stream, (b) the modified fault energy of da- H

the key current is delayed by 0.05 T, where T is 1 / 16,000 of I

For one second, (c) modified fault energy of the data stream I

In the advance of 0.05 T, (d) the energy of the data stream from I

In the adjacent upper channel, the desired receive frequency plus I

At 25 kHz, and (e) the energy from the data stream for it to- H

In offensive lower channel, desired reception frequency -25 kHz. H

In the Equalizer is a complex 28-pole FIR filter, H

wherein the filter weights are determined by minimizing the H

30 the above five purposes. For this purpose, five H are generated

In setting signals of the modulator. These are: (a) an I

signal at the desired frequency at which the receiver and I

the transmitter clock generators are synchronized, (b) the same I

signal as at (a) but where the receiver clock generator I

In 35, 0.05 T is passed in front of the transmitter clock generator, (c) the same I

In signal such as (b) except that it is delayed by I

(T) the same signal as (a), but where the carrier frequency is increased by 25 kHz, and (e) the same signal as (d) except that the carrier frequency is reduced by 25 kHz. In cases (d) and (e), the modem processor 5 changes the transmitter FIR filter coefficients by 25 kHz to generate the set signal with a 25 kHz deviation.

By comparing the actual Input signals with the set of desired output signals during the presentation of each of the five Setting signals, a set of weighting coefficients is achieved which, when realized in the equalizer, fulfill the aforementioned purposes. These weighting coefficients are stored in RAM 32. The offset I and Q samples are fed to a module 302 which produces an output signal that is the arctangent of the ratio of the offset Q and I samples. This output signal shown at 304 represents the phase of the received signal.

The equalized I and Q samples are also simultaneously fed to a coarse frequency module 306, shown in more detail in Figure 9. The I and Q samples are joined together to produce a lower sideband 308, as shown in Figure 9 and at the same time the difference between the I and Q samples is formed to produce an upper sideband 310. A size calculation is then performed on both the upper and 25 lower sidebands, as indicated at 312 and 314. The difference operation between the sizes takes place at 316.

This difference, stated at 318, represents a frequency error.

As shown in Figure 8, the output signal 304 is fed from the arctangent module 302 to the AFC and a symbol time tracking module 32 shown in greater detail in Figure 10. The phase correction value indicated at 322 in Figure 10 is subtracted from the detected phase, resulting in the corrected phase indicated by line 324. The corrected phase 324 is fed to a symbol detector 326 which detects the current symbol expressed by the phase value and

I DK 175639 B1 I

I 20 I

quantifies the phase to the nearest 22.5 degrees of increase

You see. The quantized phase given at 328, I

You subtract the corrected phase 324 by 330. This

In error signal 332, a loop filter of the second order is applied

5 as a whole indicated by 334 which calculates the phase corp.

In the reaction value given by line 336 and · I

In the frequency correction signal shown at 338. It- I

In th frequency correction signal is passed to the VCXO through I

In the line 132 shown in Figure 1.

I The error signal 332 is passed through line 340 to an I

In symbol time trace module 342, which also receives output sig- I

In the needle from the symbol detection module 326 through the line I

344. The symbol time trace module 342 contains an algorithm I

I, which traces the phase over a number of predetermined acids

In 15 bolts, locks on the initial phase of the first symbol and the I

In the phase of the last symbol and then the slope. The

You try to determine the zero I based on the phase / time function

In reviews that actually occur and compare

H with where they should have occurred and one is calculated

20 time adjustment that corrects for the difference. Symbol- I

The clock is adjusted at the beginning of the next slot. Syrn-

In the ball time trace module 342, an output signal 346 which i

is fed to the timing module 51. shown in Figure 1

The frequency correction signal 338 from the AFC and I

The symbol timing module 320 is fed to a weighting module I

H 348, as shown in Figure 8, where it is weighted. Output Signal I

In light 350 from module 348, a summing module I is passed

In 352, where signal 350 is added to module 306's I

output signal 318 to provide an output I

Signal 354 which is fed to the D / A converter 134. Output I

In the signal from the D / A converter shown in Figure 1 is led to I

In the synthesizer at 138. I

Although the invention, as described above,

for various distinct elements, it is mu-

35 to allow the function of many of these elements, I

such as e.g. The full speed PROM, FIFO 46, I

The interpolator 48 and PAL 50 are contained in a modem processor of sufficient capacity. This may also be the case for elements such as frame timing 91, blanking generator 58, timing means 51, 5 division by 4, division by 5 and some or all of the synthesizer 72. Furthermore, the baseband processor and modem processor may also be combined into a single unit which contains the codec and the UART.

10 15 20 25 30 35

Claims (4)

A symbol time tracking and automatic frequency control system, characterized by comprising an input of a signal representing a detected phase (304), in a means (323) for subtracting a phase correction value (322) from it. said signal representing a detected phase (304) providing a signal representing a corrected phase (324) in a means (326) for quantizing the phase of the signal representing a corrected phase (324), I for a predetermined increment, a means (330) for subtracting a signal, IB 15 representing the quantized phase (328), from the signal representing the corrected phase I ( 324), to provide a phase error signal (332), I and. In a means (334) for receiving the phase error signal I 20 (332) and therefrom calculating both the phase correction value (322) and a frequency correction signal (338). IN The system according to claim 1, further comprising a symbol timing module I (342) adapted to receive both the phase IB error signal (332) and the signal representing IB the quantized phase (328) for which provides an timing adjustment for adjusting an acidic IB clock. IN A method for symbol time tracking and automatic frequency control, characterized in that IB comprises IB receiving a signal representing a detected IB phase (304), subtracting a phase correction value (322) from said signal representing a detected phase (304) to provide a signal representing a corrected phase (324) to quantize the phase of the signal representing a corrected phase (324) to a predetermined increment subtracting a signal representing the quantized phase (328) from the signal representing a corrected phase (324) to provide a phase error signal (332) and to compute both the phase correction value (322) and a frequency correction signal ( 338) based on the phase error signal. 15 Frequency conversion device for converting a first, at an output frequency centered signal to a second, at a second frequency centered signal, characterized by comprising a means for receiving a first predetermined signal, a means for receiving a a first time multiplexed square signal, a first signal combiner performing a multiplication function by combining the first predetermined timing signal with the time multiplexed square signal, a digital / analog converter for converting the combined signal into a first analog signal, 30 second signal combining means for combining the first analogue signal emitted from the digital / analog converter with a second analog signal at a predetermined frequency to generate a third analog H signal, and H a means for integrating the third analog signal. H signal to generate the second, at another frequency H 5 centered signal. H