DE69131212D1 - Cache coherency in logical caches - Google Patents

Cache coherency in logical caches

Info

Publication number
DE69131212D1
DE69131212D1 DE69131212T DE69131212T DE69131212D1 DE 69131212 D1 DE69131212 D1 DE 69131212D1 DE 69131212 T DE69131212 T DE 69131212T DE 69131212 T DE69131212 T DE 69131212T DE 69131212 D1 DE69131212 D1 DE 69131212D1
Authority
DE
Germany
Prior art keywords
cache coherency
logical caches
caches
logical
coherency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69131212T
Other languages
German (de)
Other versions
DE69131212T2 (en
Inventor
Hidenobu Ohta
Taizo Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of DE69131212D1 publication Critical patent/DE69131212D1/en
Application granted granted Critical
Publication of DE69131212T2 publication Critical patent/DE69131212T2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
    • G06F12/1054—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache the data cache being concurrently physically addressed

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE69131212T 1990-01-22 1991-01-22 Cache coherency in logical caches Expired - Fee Related DE69131212T2 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2012220A JPH03216744A (en) 1990-01-22 1990-01-22 Built-in cache memory control system

Publications (2)

Publication Number Publication Date
DE69131212D1 true DE69131212D1 (en) 1999-06-17
DE69131212T2 DE69131212T2 (en) 1999-09-23

Family

ID=11799299

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69131212T Expired - Fee Related DE69131212T2 (en) 1990-01-22 1991-01-22 Cache coherency in logical caches

Country Status (5)

Country Link
US (1) US5517633A (en)
EP (1) EP0439325B1 (en)
JP (1) JPH03216744A (en)
CA (1) CA2034709C (en)
DE (1) DE69131212T2 (en)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5748627A (en) * 1994-06-10 1998-05-05 Harris Corporation Integrated network switch with flexible serial data packet transfer system
US5809548A (en) * 1996-08-30 1998-09-15 International Business Machines Corporation System and method for zeroing pages with cache line invalidate instructions in an LRU system having data cache with time tags
US5809528A (en) * 1996-12-24 1998-09-15 International Business Machines Corporation Method and circuit for a least recently used replacement mechanism and invalidated address handling in a fully associative many-way cache memory
US6434671B2 (en) * 1997-09-30 2002-08-13 Intel Corporation Software-controlled cache memory compartmentalization
US6226731B1 (en) * 1998-09-08 2001-05-01 International Business Machines Corporation Method and system for accessing a cache memory within a data-processing system utilizing a pre-calculated comparison array
CN1168025C (en) * 1999-03-10 2004-09-22 国际商业机器公司 Command cache for multiple thread processor
DE10158393A1 (en) 2001-11-28 2003-06-12 Infineon Technologies Ag Memory for the central unit of a computer system, computer system and method for synchronizing a memory with the main memory of a computer system
US6654865B2 (en) * 2002-01-31 2003-11-25 Ubicom, Inc. Netbufs: communication protocol packet buffering using paged memory management
US8270529B2 (en) * 2006-06-22 2012-09-18 Nordnav Technologies Ab Software-based spread spectrum signal processing
JP4821887B2 (en) 2009-06-08 2011-11-24 日本電気株式会社 Coherency control system, coherency control device, and coherency control method
US20110055482A1 (en) * 2009-08-28 2011-03-03 Broadcom Corporation Shared cache reservation
CN111290972B (en) * 2020-03-11 2022-07-15 深圳忆联信息系统有限公司 Method and device for improving data carrying efficiency and computer equipment

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4332010A (en) * 1980-03-17 1982-05-25 International Business Machines Corporation Cache synonym detection and handling mechanism
JPS5948879A (en) * 1982-09-10 1984-03-21 Hitachi Ltd Storage control system
JPS6093563A (en) * 1983-10-27 1985-05-25 Hitachi Ltd Buffer storage control system
US4985829A (en) * 1984-07-31 1991-01-15 Texas Instruments Incorporated Cache hierarchy design for use in a memory management unit
US4991081A (en) * 1984-10-31 1991-02-05 Texas Instruments Incorporated Cache memory addressable by both physical and virtual addresses
US4797814A (en) * 1986-05-01 1989-01-10 International Business Machines Corporation Variable address mode cache
JPH0661066B2 (en) * 1986-10-20 1994-08-10 株式会社日立製作所 Storage controller
US4926317A (en) * 1987-07-24 1990-05-15 Convex Computer Corporation Hierarchical memory system with logical cache, physical cache, and address translation unit for generating a sequence of physical addresses
JP2675836B2 (en) * 1987-10-02 1997-11-12 株式会社日立製作所 Data processing device
KR920001282B1 (en) * 1987-10-02 1992-02-10 가부시키가이샤 히타치세이사쿠쇼 Buffer memory control apparatus
US5119290A (en) * 1987-10-02 1992-06-02 Sun Microsystems, Inc. Alias address support
US5003459A (en) * 1988-04-01 1991-03-26 Digital Equipment Corporation Cache memory system
US5029070A (en) * 1988-08-25 1991-07-02 Edge Computer Corporation Coherent cache structures and methods
US5155824A (en) * 1989-05-15 1992-10-13 Motorola, Inc. System for transferring selected data words between main memory and cache with multiple data words and multiple dirty bits for each address
US5226133A (en) * 1989-12-01 1993-07-06 Silicon Graphics, Inc. Two-level translation look-aside buffer using partial addresses for enhanced speed
US5210845A (en) * 1990-11-28 1993-05-11 Intel Corporation Controller for two-way set associative cache

Also Published As

Publication number Publication date
CA2034709C (en) 1998-07-28
CA2034709A1 (en) 1991-07-23
EP0439325A2 (en) 1991-07-31
EP0439325B1 (en) 1999-05-12
US5517633A (en) 1996-05-14
JPH03216744A (en) 1991-09-24
DE69131212T2 (en) 1999-09-23
EP0439325A3 (en) 1992-07-08

Similar Documents

Publication Publication Date Title
DE69031086D1 (en) Cache memory control in multiprocessor networks
DE69530776D1 (en) TWO-WAY SET-ASSOCIATIVE CACHE STORAGE
DE69127936D1 (en) Bus protocol for processor with write-back cache
DE69130580D1 (en) Cache memory arrangement
DE68927172D1 (en) MULTIPROCESSOR SYSTEM WITH CACHE STORAGE
DE69132186T2 (en) Cache management arrangement
DE69131674T2 (en) Computer arrangement with selectable cache memory subsystem
DE69027253T2 (en) Multiprocessor cache system
DE69130583D1 (en) Cache control arrangement
DE69229667T2 (en) SIMULATED CACHE ASSOCIATIVITY
DE69432133T2 (en) Data processor with cache memory
EP0447161A3 (en) Hierarchical invalidation for distributed caches
DE69329080T2 (en) Cache memory
DE69132018T2 (en) Pre-cache cache calculator
DE69219433D1 (en) Write-through virtual cache Synonym addressing and cache invalidation
GB9715399D0 (en) Cache coherency using path directories
DE69131212D1 (en) Cache coherency in logical caches
DE69033629T2 (en) Microprocessor with cache memory
DE69030072D1 (en) Fast write-through cache
DE69611510D1 (en) Central processing unit with cache memory
DE68925336D1 (en) Data processing device with cache memory
DE69131338T2 (en) Cache memory arrangement
DE59208307D1 (en) Cache
DE69031365T2 (en) Multi-computer system with hierarchical cache memory
DE69030368T2 (en) Tandem cache memory

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee