DE602004018981D1 - Datenlayout-mechanismus zur verringerung von hardware-betriebsmittelkonflikten - Google Patents

Datenlayout-mechanismus zur verringerung von hardware-betriebsmittelkonflikten

Info

Publication number
DE602004018981D1
DE602004018981D1 DE602004018981T DE602004018981T DE602004018981D1 DE 602004018981 D1 DE602004018981 D1 DE 602004018981D1 DE 602004018981 T DE602004018981 T DE 602004018981T DE 602004018981 T DE602004018981 T DE 602004018981T DE 602004018981 D1 DE602004018981 D1 DE 602004018981D1
Authority
DE
Germany
Prior art keywords
conflicts
data layout
reduce hardware
layout mechanism
hardware factory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602004018981T
Other languages
English (en)
Inventor
Tatiana Shpeisman
Ali-Reza Adl-Tabatabai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of DE602004018981D1 publication Critical patent/DE602004018981D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/44—Encoding
    • G06F8/441—Register allocation; Assignment of physical memory space to logical memory space
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/44—Encoding
    • G06F8/443—Optimisation
    • G06F8/4441—Reducing the execution time required by the program code
    • G06F8/4442—Reducing the number of cache misses; Data prefetching

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Devices For Executing Special Programs (AREA)
  • Management, Administration, Business Operations System, And Electronic Commerce (AREA)
  • Communication Control (AREA)
DE602004018981T 2003-12-29 2004-12-21 Datenlayout-mechanismus zur verringerung von hardware-betriebsmittelkonflikten Active DE602004018981D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/748,384 US20050149916A1 (en) 2003-12-29 2003-12-29 Data layout mechanism to reduce hardware resource conflicts
PCT/US2004/043238 WO2005066764A2 (en) 2003-12-29 2004-12-21 Data layout mechanism to reduce hardware resource conflicts

Publications (1)

Publication Number Publication Date
DE602004018981D1 true DE602004018981D1 (de) 2009-02-26

Family

ID=34710909

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602004018981T Active DE602004018981D1 (de) 2003-12-29 2004-12-21 Datenlayout-mechanismus zur verringerung von hardware-betriebsmittelkonflikten

Country Status (7)

Country Link
US (1) US20050149916A1 (de)
EP (1) EP1700209B1 (de)
JP (1) JP4704357B2 (de)
CN (1) CN1902586A (de)
AT (1) ATE420400T1 (de)
DE (1) DE602004018981D1 (de)
WO (1) WO2005066764A2 (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050216900A1 (en) * 2004-03-29 2005-09-29 Xiaohua Shi Instruction scheduling
WO2007056893A1 (en) * 2005-11-18 2007-05-24 Intel Corporation Latency hiding of traces using block coloring
US7836435B2 (en) * 2006-03-31 2010-11-16 Intel Corporation Checking for memory access collisions in a multi-processor architecture
US8037466B2 (en) 2006-12-29 2011-10-11 Intel Corporation Method and apparatus for merging critical sections
US7805580B2 (en) * 2007-01-08 2010-09-28 International Business Machines Corporation Method and system for determining optimal data layout using blind justice
US8386391B1 (en) * 2007-05-01 2013-02-26 Hewlett-Packard Development Company, L.P. Resource-type weighting of use rights
US8561072B2 (en) * 2008-05-16 2013-10-15 Microsoft Corporation Scheduling collections in a scheduler
JP4892022B2 (ja) * 2009-03-03 2012-03-07 株式会社東芝 コンパイル装置およびコンパイルプログラム
JP4600700B2 (ja) * 2009-03-17 2010-12-15 日本電気株式会社 プログラムのメモリ空間への配置方法、装置、およびプログラム
CN103455443B (zh) * 2013-09-04 2017-01-18 华为技术有限公司 一种缓存管理方法和装置
WO2016144298A1 (en) * 2015-03-06 2016-09-15 Hewlett Packard Enterprise Development Lp Location update scheduling
CN105306525A (zh) * 2015-09-11 2016-02-03 浪潮集团有限公司 一种数据布局的方法、装置和系统
US10285190B2 (en) * 2016-12-20 2019-05-07 Raytheon Bbn Technologies Corp. Scheduling access to a shared medium
US20190187964A1 (en) * 2017-12-20 2019-06-20 Advanced Micro Devices, Inc. Method and Apparatus for Compiler Driven Bank Conflict Avoidance
US10783082B2 (en) * 2019-08-30 2020-09-22 Alibaba Group Holding Limited Deploying a smart contract

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5774730A (en) * 1995-07-31 1998-06-30 International Business Machines Corporation Method and apparatus for improving colorability of constrained nodes in an interference graph within a computer system
US5963972A (en) * 1997-02-24 1999-10-05 Digital Equipment Corporation Memory architecture dependent program mapping
US5933644A (en) * 1997-06-18 1999-08-03 Sun Microsystems, Inc. Method and apparatus for conflict-based block reordering
EP0974898A3 (de) * 1998-07-24 2008-12-24 Interuniversitair Microelektronica Centrum Vzw Verfahren zur Bestimmung einer speicherbandbreiteoptimierten Speicherorganisation von einer im wesentlichen digitalen Vorrichtung

Also Published As

Publication number Publication date
JP4704357B2 (ja) 2011-06-15
JP2007517324A (ja) 2007-06-28
EP1700209B1 (de) 2009-01-07
US20050149916A1 (en) 2005-07-07
EP1700209A2 (de) 2006-09-13
CN1902586A (zh) 2007-01-24
ATE420400T1 (de) 2009-01-15
WO2005066764A3 (en) 2006-01-26
WO2005066764A2 (en) 2005-07-21

Similar Documents

Publication Publication Date Title
DE602004018981D1 (de) Datenlayout-mechanismus zur verringerung von hardware-betriebsmittelkonflikten
ATE459227T1 (de) Verfahren, elektronische vorrichtungen und computerprogrammprodukte zur koordination von bluetooth- und wlan-kommunikation
ATE410571T1 (de) Verkleidungsplatte
AU2003223789A1 (en) Constraint-based production planning and scheduling
DE60312390D1 (de) Ereigniserinnerungsverfahren
ES2559763T3 (es) Anticuerpo humano específico de CD3 con propiedades inmunosupresoras
DE60207161T2 (de) Halbleiteranordnung mit Hardware-Anordnung zur Taktsteuerung
AU2003287070A8 (en) Systems and methods for planning, scheduling, and management
GB2432537A (en) A ciliated stent-like system
EP1248449A3 (de) System und Verfahren zur kompetenzbasierten Anrufverteilung in einer Anrufzentrale
WO2004107119A3 (en) System and method for preference scheduling of staffing resources
DK1562444T3 (da) Fremgangsmåde til formindskelse af acrylamidindholdet i varmebehandlede levnedsmidler
DE60213484D1 (de) Kommunikationssystem
ATE395662T1 (de) Grid-parallelausführung
WO2006094884A3 (en) User interface for appointment scheduling system showing appointment solutions within a day.
ATE521925T1 (de) Feldbusverteilereinheit
EP2290538A3 (de) Verfahren und Vorrichtung zur Verringerung des Energieverbrauchs in anwendungsspezifisch anleitungseingestellten Prozessoren
ATE446536T1 (de) Motorsteuerungsmodul und -verfahren zur verwendung in der motorsystemherstellung
ATE409917T1 (de) System und verfahren zum optimierten parsen von tag-basierten protokollströmen
ATE454770T1 (de) Nachrichtensequenzer für korrelierte unternehmensereignisse
DE60320570D1 (de) Vorrichtung zur steuerung von tastaturereignissen
BR0204085B1 (pt) fio elÁstico fluorescente e mÉtodo para produzir o mesmo.
GB0307805D0 (en) A method of enabling source code to be used to generate a first and a second software application,each compatible with a different operating system
DE60311187D1 (de) Datenausgabetreiber und Datenausgabeverfahren zur Minimierung von Abweichungen der Datenausgabezeit durch Datenmuster verursacht
GB0222917D0 (en) Management of business process application execution

Legal Events

Date Code Title Description
8364 No opposition during term of opposition