DE602004012492D1 - DMA control with bus busy time restriction as well as DMA parameter sets for several logical processors - Google Patents

DMA control with bus busy time restriction as well as DMA parameter sets for several logical processors

Info

Publication number
DE602004012492D1
DE602004012492D1 DE602004012492T DE602004012492T DE602004012492D1 DE 602004012492 D1 DE602004012492 D1 DE 602004012492D1 DE 602004012492 T DE602004012492 T DE 602004012492T DE 602004012492 T DE602004012492 T DE 602004012492T DE 602004012492 D1 DE602004012492 D1 DE 602004012492D1
Authority
DE
Germany
Prior art keywords
dma
well
parameter sets
time restriction
logical processors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE602004012492T
Other languages
German (de)
Other versions
DE602004012492T2 (en
Inventor
Akihiro Furuta
Nobuo Higaki
Tetsuya Tanaka
Tsuneyuki Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Publication of DE602004012492D1 publication Critical patent/DE602004012492D1/en
Application granted granted Critical
Publication of DE602004012492T2 publication Critical patent/DE602004012492T2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
DE602004012492T 2003-08-01 2004-07-29 DMA control with bus busy time restriction as well as DMA parameter sets for several logical processors Expired - Fee Related DE602004012492T2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2003285080 2003-08-01
JP2003285080A JP2005056067A (en) 2003-08-01 2003-08-01 Dma transfer controller

Publications (2)

Publication Number Publication Date
DE602004012492D1 true DE602004012492D1 (en) 2008-04-30
DE602004012492T2 DE602004012492T2 (en) 2009-04-09

Family

ID=33535731

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602004012492T Expired - Fee Related DE602004012492T2 (en) 2003-08-01 2004-07-29 DMA control with bus busy time restriction as well as DMA parameter sets for several logical processors

Country Status (5)

Country Link
US (1) US7305499B2 (en)
EP (1) EP1503292B1 (en)
JP (1) JP2005056067A (en)
CN (1) CN100388253C (en)
DE (1) DE602004012492T2 (en)

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US7734832B2 (en) * 2004-11-10 2010-06-08 Microsoft Corporation Method and system for structured programmed input/output transactions
US8079036B2 (en) * 2004-11-10 2011-12-13 Microsoft Corporation Method and system for structured DMA transactions
JP2006157580A (en) * 2004-11-30 2006-06-15 Ricoh Co Ltd Image processor, image forming apparatus, image processing method, computer program, and recording medium
JP2006178787A (en) * 2004-12-22 2006-07-06 Toshiba Corp Semiconductor device and data transfer method therefor
CN100369024C (en) * 2005-01-17 2008-02-13 北京中星微电子有限公司 Direct memory access control device and image processing system and transmission method
US7555577B2 (en) * 2005-05-13 2009-06-30 Texas Instruments Incorporated Data transfer apparatus with channel controller and transfer controller capable of slave and standalone operation
US7546391B2 (en) * 2005-05-13 2009-06-09 Texas Instruments Incorporated Direct memory access channel controller with quick channels, event queue and active channel memory protection
JP2006338353A (en) * 2005-06-02 2006-12-14 Sony Corp Information processor, information processing method and program
WO2007003986A1 (en) 2005-06-30 2007-01-11 Freescale Semiconductor, Inc. Device and method for controlling an execution of a dma task
EP1899828B1 (en) 2005-06-30 2009-11-25 Freescale Semiconductor, Inc. Device and method for arbitrating between direct memory access task requests
EP1899825B1 (en) 2005-06-30 2009-07-22 Freescale Semiconductor, Inc. Device and method for controlling multiple dma tasks
JP2008216472A (en) * 2007-03-01 2008-09-18 Matsushita Electric Ind Co Ltd Speech decoding device and speech decoding system
JP4972692B2 (en) * 2007-08-30 2012-07-11 パナソニック株式会社 DMA controller and data transfer method
US20090063725A1 (en) * 2007-08-31 2009-03-05 O2Micro Inc. Direct memory access system
US8266337B2 (en) * 2007-12-06 2012-09-11 International Business Machines Corporation Dynamic logical data channel assignment using channel bitmap
JP2011060066A (en) 2009-09-11 2011-03-24 Renesas Electronics Corp Data processing circuit
JP5834182B2 (en) * 2010-07-27 2015-12-16 パナソニックＩｐマネジメント株式会社 Data transfer control device and data transfer control method
JP5644531B2 (en) * 2011-01-19 2014-12-24 富士通セミコンダクター株式会社 Data transfer apparatus and data transfer method
US8447897B2 (en) * 2011-06-24 2013-05-21 Freescale Semiconductor, Inc. Bandwidth control for a direct memory access unit within a data processing system
JP5658827B2 (en) * 2011-06-24 2015-01-28 株式会社日立製作所 Storage system
JP5803689B2 (en) * 2012-01-17 2015-11-04 トヨタ自動車株式会社 Information processing apparatus and DMA controller operation check method
US9128925B2 (en) 2012-04-24 2015-09-08 Freescale Semiconductor, Inc. System and method for direct memory access buffer utilization by setting DMA controller with plurality of arbitration weights associated with different DMA engines
JP2014010759A (en) 2012-07-02 2014-01-20 Toshiba Corp Bridge device, method therefor, storage apparatus and program
JP6004057B2 (en) * 2015-07-09 2016-10-05 トヨタ自動車株式会社 Information processing apparatus and DMA controller operation check method
FR3057969B1 (en) 2016-10-25 2019-11-01 Thales DETERMINISTIC DRIVER SYSTEM FOR DETERMINING THE OPERATION OF MEANS FOR TRANSFERRING DATA BY DIRECT ACCESS TO MEMORY MEANS
CN114661644B (en) * 2022-02-17 2024-04-09 之江实验室 Pre-storage DMA device for auxiliary 3D architecture near-memory computing accelerator system

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JPH05250305A (en) * 1992-03-06 1993-09-28 Mitsubishi Electric Corp Data transfer control system
US5680556A (en) * 1993-11-12 1997-10-21 International Business Machines Corporation Computer system and method of operation thereof wherein a BIOS ROM can be selectively locatable on diffeent buses
JPH0830549A (en) 1994-07-18 1996-02-02 Fuji Xerox Co Ltd Bus control device
US5603050A (en) * 1995-03-03 1997-02-11 Compaq Computer Corporation Direct memory access controller having programmable timing
JPH09223102A (en) * 1995-12-14 1997-08-26 Ricoh Co Ltd Direct memory access controller
JP3712842B2 (en) * 1997-08-05 2005-11-02 株式会社リコー Data transfer control method, data transfer control device, and information recording medium
US6363445B1 (en) * 1998-10-15 2002-03-26 Micron Technology, Inc. Method of bus arbitration using requesting device bandwidth and priority ranking
JP2000132505A (en) 1998-10-27 2000-05-12 Matsushita Electric Ind Co Ltd Bus access method and device therefor, and device and system using the bus access method and device
JP3258300B2 (en) 1999-09-03 2002-02-18 松下電器産業株式会社 DMA transfer device and image decoding device
US6542940B1 (en) * 1999-10-25 2003-04-01 Motorola, Inc. Method and apparatus for controlling task execution in a direct memory access controller
JP2002041445A (en) 2000-05-19 2002-02-08 Matsushita Electric Ind Co Ltd Highly efficient dma controller
EP1193610B1 (en) * 2000-09-29 2006-11-15 Ricoh Company, Ltd. Data processing apparatus and DMA data transfer method
JP2002163239A (en) * 2000-11-22 2002-06-07 Toshiba Corp Multi-processor system and control method for it
KR100367084B1 (en) * 2000-12-22 2003-01-09 한국전자통신연구원 DMA controller for the high speed image processor at real time
KR100456696B1 (en) * 2002-05-21 2004-11-10 삼성전자주식회사 Bus arbiter for integrated circuit systems

Also Published As

Publication number Publication date
US7305499B2 (en) 2007-12-04
US20050050241A1 (en) 2005-03-03
EP1503292B1 (en) 2008-03-19
CN1591374A (en) 2005-03-09
EP1503292A3 (en) 2005-03-23
DE602004012492T2 (en) 2009-04-09
CN100388253C (en) 2008-05-14
JP2005056067A (en) 2005-03-03
EP1503292A2 (en) 2005-02-02

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Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: PANASONIC CORP., KADOMA, OSAKA, JP

8339 Ceased/non-payment of the annual fee