DE60136110D1 - Segmented circuit arrangement - Google Patents

Segmented circuit arrangement

Info

Publication number
DE60136110D1
DE60136110D1 DE60136110T DE60136110T DE60136110D1 DE 60136110 D1 DE60136110 D1 DE 60136110D1 DE 60136110 T DE60136110 T DE 60136110T DE 60136110 T DE60136110 T DE 60136110T DE 60136110 D1 DE60136110 D1 DE 60136110D1
Authority
DE
Germany
Prior art keywords
circuit arrangement
segmented circuit
segmented
arrangement
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60136110T
Other languages
German (de)
Inventor
Ian Juso Dedic
Sanjay Ashwin-Kumar Patel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from EP00309413A external-priority patent/EP1100203B1/en
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE60136110D1 publication Critical patent/DE60136110D1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

DE60136110T 2000-10-26 2001-09-11 Segmented circuit arrangement Expired - Lifetime DE60136110D1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP00309413A EP1100203B1 (en) 1999-11-10 2000-10-26 Noise shaping in segmented mixed-signal circuitry
GB0101307A GB0101307D0 (en) 2000-10-26 2001-01-18 Segmented circuitry

Publications (1)

Publication Number Publication Date
DE60136110D1 true DE60136110D1 (en) 2008-11-20

Family

ID=8173341

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60136110T Expired - Lifetime DE60136110D1 (en) 2000-10-26 2001-09-11 Segmented circuit arrangement

Country Status (3)

Country Link
CN (1) CN1909377B (en)
DE (1) DE60136110D1 (en)
GB (1) GB0101307D0 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104113343B (en) * 2014-02-28 2017-09-29 西安电子科技大学 One kind packet pseudorandom rotating thermometer decoding circuit
CN109586726B (en) * 2019-01-22 2024-03-08 江苏集萃微纳自动化系统与装备技术研究所有限公司 Segmented digital-to-analog converter

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4812818A (en) * 1987-02-24 1989-03-14 Brooktree Corporation Digital-to-analog converter
US5646619A (en) * 1995-04-26 1997-07-08 Lucent Technologies Inc. Self-calibrating high speed D/A converter
US5793231A (en) * 1997-04-18 1998-08-11 Northern Telecom Limited Current memory cell having bipolar transistor configured as a current source and using field effect transistor (FET) for current trimming
US5949362A (en) * 1997-08-22 1999-09-07 Harris Corporation Digital-to-analog converter including current cell matrix with enhanced linearity and associated methods

Also Published As

Publication number Publication date
GB0101307D0 (en) 2001-02-28
CN1909377B (en) 2011-10-05
CN1909377A (en) 2007-02-07

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Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU MICROELECTRONICS LTD., TOKYO, JP

8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU SEMICONDUCTOR LTD., YOKOHAMA, KANAGAWA, JP

8328 Change in the person/name/address of the agent

Representative=s name: SEEGER SEEGER LINDNER PARTNERSCHAFT PATENTANWAELTE