DE4417286A1 - ATM buffer circuit data read-out method - Google Patents

Abstract

The method involves the buffer level being evaluated from the half-full indicators (H). It uses the buffer level indication to control the introduction of empty filler data bytes between used byte blocks. The half-full indicator (H) for memory blocks 1 to n are acquired and evaluated. Further indicators for at least one cell filled, one quarter of cells and three quarters of cells filled are also used. According to the memory block 1 to n, a different number of empty bytes are assigned, where the number of empty bytes introduced between used blocks varies. The read-out from blocks with low data levels is at a low rate, while the read out from block with high data levels is at a high rate.

Description

The invention relates to a method and Circuit arrangement for reading cells from a Buffer memory in ATM facilities or terminal Adapters, which vary greatly from those of the ATM network Delay incoming cells and if possible even to the clock recovery circuits has to pass on.

A solution is known in which for clock recovery in the receiving part of a subscriber circuit for Digital signals with originally constant bit rate, especially high bit rate video signals, from a 1st Memory in the demultiplexer the 53 byte cells in a "cell resolver" (ZA) with a byte clock of 19 440 kHz be taken over. In the cell resolver ZA Cell sequence number checked for correctness and if necessary, excess cells are recognized and removed or inserted missing cells. The 47th Useful byte of a cell (without the cell header and without the first Byte of the information field, which is the signaling for the Start of a nesting block and the Cell sequence number contains) are from the cell resolver ZA with a byte clock of 4860 kHz, but with different time delay, read out: is the 1st memory is at least half full, so each 4 empty bytes sent after the 47 useful bytes before the the next 47 useful bytes leave the cell resolver ZA. If the memory is less than half full, so be 5 empty bytes are sent after the 47 useful bytes before the the next 47 useful bytes leave the cell resolver ZA.  

A change between two and three empty bytes is known in the case where the video bit rate is 64 to 60 is increased by a forward error correction. This Example does not take into account CCITT recommendation I.363, in which an increase in the ratio of 128 to 124 is fixed becomes.

When using this solution in compliance with the CCITT Recommendation I.363 then becomes the disadvantage of this solution obviously if due to major changes in the Cell run times in the transmission network of the 1st memory themselves for a long time in one of the two states "less than half full "or" at least half full ". In these In some cases, larger networks, d. that is, if the cells of a connection have many switches have to go through and therefore extremely different Run times are subject to, the first memory empty or overflows.

The invention has for its object a method and to develop a circuit arrangement which the Disadvantages of the above remove known solution without the capacity of the first memory is increased unnecessarily must become. It should be achieved that the level of the 1st store as close as possible to the "half full" - Brand is held. The frequency range for the Transfer of user data should be relatively large and Clock frequencies for the terminals to be adapted. Farther It must be taken into account that there are still free bytes in the 47 useful bytes Capacity for a forward correction of approximately 3.223% for Signals with an ATM adaptation layer of type 1 (according to CCITT recommendation I.363) must be available.

According to the invention, the object is achieved by a method solved, in addition to capturing the current  Fill level of a memory SP1 based on that in the memory SP1 integrated half-full display H other characteristic Memory states from 1 to n are recorded and evaluated. Each memory state of the first memory is 1 a different number of empty bytes is assigned to n. The following applies to the assignment, the lower the level of the first memory SP1, the greater the number of this Fill level assigned empty byte, which lies between the individual useful byte blocks of the cells can be inserted. In order to the cells are read from an additional one second memory SP2 when the first level is low Memory SP1 with a low readout speed and at a high level with a high one Readout speed.

The method according to the invention is implemented by means of a circuit arrangement which is composed of assemblies known per se, such as memories, control assemblies and assemblies for cell sequence testing and cell head removal. According to the invention, the first memory SP1 is connected to a module for the level indicator FA via the byte clock input BT, the cell start input for reading data from memory 1 ZSte and the cell start input for reading data from memory 1 ZSta. The module for the level indicator FA is connected to an additional second control module SB2 via the outputs for the level indicator 1- n. The output for the half-full display of the first memory H1 is connected to the first control module SB1. An additional second control module SB2 is connected via its output for the reading clock L to the input of a second memory SP2, which is connected with its further inputs to the block for cell sequence checking, cell sequence correction and cell head removal A. Furthermore, the second control module SB2 is connected to the clock divider Te via the byte clock input BT3, via an input for the differentiated half-full display H2d to the first control module SB1 and via an input for the delete pulse Lö on the one hand with the block for the cell sequence check, cell sequence correction and cell head distance A and on the other hand connected to an input of the second memory SP2. The second memory SP2 is connected to the first control module SB1 via its input for the half-full display H2.

The solution according to the invention is based on a Embodiment explained in more detail. It shows:

Fig. 1 by means of a block diagram the basic solution of the circuit arrangement according to the invention,

Fig. 2 shows the circuit structure for the embodiment shown in Fig. 1 control module SB1,

Fig. 3 shows the circuit configuration for the embodiment illustrated in Fig. 1 SB2 control assembly,

Fig. 5 is a table for the assignment of the number of empty bytes to the binary counter blocks and

Fig. 6 is a table for assigning the number of idle byte to the Binärzählerblöcken doubling the Bytetaktfrequenzen BT3 and BT2.

In Fig. 1 the basic construction of the circuit arrangement according to the invention. The first memory SP1 can, for example, consist of one or more FIFO (first-in first-out) memories connected in cascade. The block labeled A contains the circuit for the cell sequence check, a correction circuit for missing or surplus cells and a suppression circuit for the cell headers consisting of 5 bytes, as well as a suppression circuit for the 1st byte of the information field belonging to the ATM adaptation layer. In the specific embodiment, the second additional memory SP2 can hold approximately 10 cells and only contains correct cells with regard to the cell sequence. With regard to the data sequence, errors may also be contained, which may have arisen either in the transmission path or by inserting replacement cells of any content in block A. These inserted cells are marked at the output of block A with the signal "data correct" (DR3 = 0 potential). The assembly for the level indicator FA preferably consists of the combination of an up and down counter with a decoding circuit.

FIG. 2 shows a specific embodiment of the structure of the first control module SB1 shown in the block diagram in FIG. 1.

The first control assembly consists of two over the half full display of the first memory H2 connected Differentiators. The differentiators are a differentiator for the negative edges Dn and one Differentiators for the positive edges Dp with two bistable multivibrators S1; S2, are interconnected. The bistable multivibrators S1; S2 is a common one Gate circuit T1 subordinate to the input for the Cell request signal ZAnf of the first memory connected is. Between reset input R and output Q of the bistable multivibrators S2 is a delay element Verz arranged.

At the beginning of the reading process, the first memory SP1 and the second memory SP2 are deleted. The half-full signal of the first memory H1, which is obtained in the module for the level indicator FA, sets the bistable multivibrator S1 ( FIG. 2). At the output Q of S1, a cell request signal ZAnf is sent to the first memory SP1 via the gate T1. This signal is maintained until the second memory SP2 sends a half-full signal H2 (0 potential) to the differentiator Dn. In this way, several cells are successively transferred from the first memory SP1 via block A to the second memory SP2. Only an output pulse at the differentiator Dn then resets the bistable multivibrator S1 and thus ends the positive potential of the cell request signal ZAnf. However, this process only takes effect when the system is switched on (start phase). During operation, a cell request signal ZAnf is always generated when the half-full display of the second memory H2 is undershot, that is, when the half-full display of the second memory H2 changes from 0 to 1 potential. A pulse then arises at the output of the differentiator for the positive edges Dp, which sets the bistable multivibrator S2. At the output Q of the bistable multivibrator S2, a cell request signal ZAnf is given to the first memory SP1 via the gate circuit T1 until the bistable multivibrator S2 is reset via the delay element Verz. In this way there is a short pulse at the output of the gate circuit T1, which leads to the reading out of one cell from the first memory SP1 into the second memory SP2.

In Fig. 3, the details of the second control unit SB2 are shown. The second control module SB2 consists of a combination of binary counter blocks BZA-BZE with bistable multivibrators S3-S9 and gate circuits T2-T8. The binary counter block BZA is used to count the useful data of the individual successive cells. The respective fill level of the first memory is detected by the binary counter blocks BZB-BZE arranged downstream of the binary counter block BZA, the specific number of which corresponds to the number of memory states to be evaluated, with each binary counter block BZB-BZE being assigned a specific fill level range of the first memory SP1. The specific number of empty bytes to be inserted between the cells of the useful byte is generated in each case via the bistable multivibrator S6-S9 belonging to the activated binary counter block BZB-BZE and the associated gate circuit T4-T7 in connection with the gate circuit T8.

After switching on the bistable multivibrator S3 lies Q 0 potential at its output. At the exit Q of the bistable multivibrators S4 is also 0 potential at. Via the output Q of the bistable multivibrator S4 the second gate circuit T2 is prepared for opening (inverted input). The second gate circuit is T2 blocked. The binary counter block BZA does not count because CE 0 potential is present at its input.

When the half-full display of the second memory H2 responds, the potential at H2 goes to 0 potential. The differentiator for the negative edges Dn ( FIG. 2) generates a pulse for the differentiated half-full display H2d and thus sets the output of the bistable multivibrator S3 to 1 potential. The second gate circuit T2 supplies positive potential to the binary counter block BZA and to the output for valid data GD, which marks valid data with 1 potential and to the third gate circuit T3, whose output for the reading clock L is a continuous sequence of 47 reading clocks L to delivers second memory SP2. When the binary counter block A reaches the counter reading 47 , the bistable multivibrators S4 and S5 are set via its output Q. Thus, the gate circuits T4 to T7 for evaluating the level determined in the module for the level indicator FA are released via the output Q of the bistable multivibrator S5. At the same time, positive potential at output Q of bistable multivibrator S4 blocks gate circuit T2 and interrupts the counting process via the 0 potential at input CE of binary counter block BZA. Depending on the fill level of the 1st memory SP1 ( FIG. 1), one of the gate circuits T4 to T7 is opened and one of the bistable multivibrators S6 to S9 connected downstream of the gate circuits T4 to T7 is activated. The activated bistable multivibrator gives via its output Q a positive potential to the input of the downstream binary counter block BZB-BZE, so that it counts the number of clock gaps programmed into it. If, for example, the first memory has the status memory at least 1/4 full V, the gate circuit T5 is opened and the bistable multivibrator S7 is activated. The binary counter block BZC begins to count, ie it counts 5 byte clocks BT3 and then resets the bistable multivibrators S4 and S7 via its output Q. After resetting the bistable multivibrator S4, 1 potential appears at the output of the gate circuit T2 and the binary counter block BZA counts again to 47.

Possible assignments (α to σ) of the binary counter sizes of the binary counter blocks BZB to BZE to concrete values, which relate to an input bit rate of 34368 kbit / s to be transmitted in cell format with the ATM adaptation layer of type 1, are in column 2 of FIG. 4 specified, with the values of the empty bytes listed in column 1. For example, the following assignments apply to the case α: binary counter block BZB = 3 empty bytes, binary counter block BZC = 4 empty bytes, binary counter block D = 5 empty bytes and binary counter block BZE = 6 empty bytes. The assignments (α to σ) of the binary counter blocks BZB to BZE proposed in FIG. 4 always leave the two binary counter blocks BZC and BZD at the same values with regard to the empty byte number assigned to them. If the fill levels of the first memory SP1 are in the middle range, ie between 0.25 and 0.75, the binary counter BZC is always assigned 4 empty bytes and the binary counter block BZD is always assigned 5 empty bytes. This procedure is proposed because only relatively small changes in the read-in frequency into the “transmit memory” are associated with it in the desired working area of the first memory SP1 in the downstream clock recovery. (Column 4 of Fig. 4).

From α to σ, however, the effectiveness of the circuit is increased at low and high levels (low level <25%; high level <75%). The example of FIG. 4 is a video signal transmission at a clock frequency of 34368 kHz and a Auslesebytetakt of 4860 kHz (BT2 in Fig. 1) a number of ways evident (ie on the size of the transfer network) depending on the specific requirements are variably usable.

If the absence of more than 6 cells is found in the block for the cell sequence check A when checking the sequence number, the input for the erase pulse receives Lö 1 potential and resets the bistable multivibrator S3 ( FIG. 3), ie the output Q of the bistable multivibrators S3 receives 0 potential and blocks the gate circuit T2. This will interrupt the previous cycle. The next time the half-full display of the second memory H2 is reached, sets the bistable multivibrator S3 again and thereby starts the cycle again.

The data read out from the second memory SP2 are fed to a further memory designed as a FIFO outside the cell resolver ZA (not shown in FIG. 1), minus the four of 128 information fields of 47 bytes each required for the forward error correction. The data of this additional memory are read out with an almost continuous clock and sent to the terminal.

The fill level of the receiving memory can be kept even more effectively in the area of the half-full display if the byte clock for signal processing is doubled to a value of 9720 kHz (by changing the clock divider Te). A selection of possible assignments (α to σ) of the empty byte and the frequencies that can be achieved in this way are shown in FIG. 5. The exemplary embodiment described relates to an input bit rate of 34368 kbit / s to be transmitted in the ATM network, which is expanded on the transmission side to 35476.645 kbit / s by a forward error correction device in accordance with CCITT recommendation I.363. In principle, however, the method according to the invention can also be applied to any other bit rate.

Claims (5)

1. Method for reading out data from buffer memories in ATM devices, in which the current fill level of a memory is detected and evaluated as a half-full display, the readout speed being changed depending on the fill level of the memory by inserting empty bytes between the useful byte blocks , characterized in that, in addition to the half-full display of the memory (H), further memory states from 1 to n are detected and evaluated, that a different number of empty bytes is assigned to each memory state from 1 to n, the lower the fill level , the greater the number of empty bytes that are inserted between the individual useful byte blocks, and that the reading of the cells with a low fill level due to the greater number of empty bytes inserted between the useful byte blocks with a low readout speed and with high fill level due to the low number of between the Useful byte blocks inserted empty byte with a high readout speed. 2. The method according to claim 1, characterized in that in addition to the half-full display (H) Memory states filled with at least one cell (1Z), at least 1/4 full (V) and at least 3/4 full (D) can be detected.   3. Circuit arrangement for reading out data from buffer memories in ATM devices using a memory which is connected to a control module and a module for cell sequence checking, cell sequence correction and cell head removal, characterized in that a first memory (SP1) via its clock input (BT ) and its cell start inputs (ZSte; ZSta) is connected to a module for the level indicator (FA), that the module for the level indicator (FA) is connected to a second control module (SB2) via the outputs for the level indicator ( 1- n) that the output for the half-full display H is additionally connected to the first control module (SB1), that the second control module (SB2) is connected via its output for the reading pulse (L) to the input of a second memory (SP2) , which is connected with its other inputs to the block for cell sequence checking, cell sequence correction and cell head removal (A), that the second control module (SB2) via byte clock input (BT3) with the clock divider (Te), via an input for the differentiated half-full display (H2d) with the first control module (SB1) and via an input for the erase pulse (Lö) is connected on the one hand to the block for cell sequence checking, cell sequence correction and cell head removal (A) and on the other hand to an input of the second memory (SP2), and that the second memory (SP2) via its output for the half-full display (H2 ) is connected to the first control module (SB1). 4. Circuit arrangement according to claim 2, characterized characterized in that the assembly for the Level indicator (FA) from the combination of a preliminary and Down counter with a decoding circuit consists.   5. Circuit arrangement according to claim 2, characterized characterized in that the second control module (SB2) from a combination of binary counter blocks (BZA-BZE) with bistable multivibrators (S3-S9) and There are gates (T2-T8), the Binary counter block (BZA) for counting the user data of the serves individual successive cells, and that by the subordinate to the binary counter block (BZA) Binary counter blocks (BZB-BZE), their concrete number with the number of memory states to be evaluated matches, the respective level of the first Memory (SP1) is detected, each Binary counter block (BZB-BZE) each one concrete Level of the first memory (SP1) is assigned, and that over to the activated binary counter block (BZB-BZE) belonging bistable multivibrator (S6-S9) and the associated gate circuit (T4-T7) in connection with the gate circuit (T8) the generation of the concrete Number of cells between the useful bytes empty byte to be inserted.