DE4244920C2 - Clock rate matching for independent networks - Google Patents

Abstract

The clock rate matching appts for independent networks includes a memory (400), microprocessor (405) and a digital signal processor (406). A PCM signal is received by an analog/PCM block (124) and the clock (CLK1) extracted by a modem (126). The modem extracts the data and passes it to a memory (400) at the extracted clock speed. The data is clocked out of the buffer by a separate clock (CLK2). The difference in clock speeds is measured by the movement of the buffer pointers. In order to match the two clock rates, bits are added or deleted from the exit path of the memory.

Description

The present invention relates to a transmitting device device for a radiotelephone communication system that works with a public telephone network has an interface, the data is clocked at a rate different from that of the Radiotelephone communication system differs.

Current methods of adjusting data rates between networks with independent clock sources are so ge plans to work in an almost flawless environment One such procedure is the one in the CCITT blue paper Recommendations V.110 (1988) described the clock compensation can perform in fractions of a bit. Since the V.110 frame consists of a total of 80 bits, of which 48 Da tenbits, if the user clock rate is 4.8 Kb / s each of the 48 data bits used in the V.110 frame. However, if the user's data rate is 2.4 Kb / s or 1.2 Kb / s is only 1/2 or 1/4 of the 48 data bits of the V.110 frame used. In this case 1/2 or 3/4 of the data bits in the V.110 frame are not used and are finally coded redundantly. In addition to the data bits clock rate information in the V.110 frame along with independent network clock setting information. In error-free systems, this information is from a clock source transferred to another so that the independent Data source can determine the compensation amount that is not is maneuverable to transfer the data precisely.  

The method described above is well suited for digital, integrated service network (ISDN) environments in which typical bit error rates (BER) are in the order of 10 ^-9 . However, when it is used in a digital radio telephone environment, for example the Groupe Special Mobile or GSM digital radio telephone system environment, the method is typically BER in the order of 10 ^-3 to 10 ^-5 . The implementation of the clock rate adaptation, as described in the CCITT recommendations V.110, causes various problems when used in the GSM environment. First, the method as recommended by the CCITT uses fractions of bit times depending on the data rate to perform clock compensation, but this information is not provided by the GSM radio interface specification, which is essentially the V.110- Frame compressed and optimized for radio transmission. The lower broken data rates are lost when optimizing. Second, errors introduced in the GSM radio interface can cause the GSM data services to randomly add or remove bits from the user data stream in the V.110 route. If this occurs, not only will data errors be caused, but also the total number of data bits will be disturbed by interference with the clock compensation mechanism as described in the CCITT recommendations V.110. This problem alone can render some types of error correction protocols useless in the GSM environment.

Another shortcoming of the V.110 adjustment procedure the user data clock speeds is the requirement a sampling mechanism for monitoring the phase differences difference between the two bars in the independent bars. To achieve the required resolution, the Bars are over-sampled to the required phases measure difference. This requirement leads to an additional one liche and expensive overhead for the GSM data platform and leads to eight complex phase states that are necessary to implement the compensation mechanism.

From document EP 0 155 741 A2 a radio telephone communication system is known in connection with FIGS. 1 to 3 with associated description and claims 1 and 2, which forms an interface with a network, the data of which are clocked at a rate that differs from that of the radiotelephone communication system. The radio communication system has a transmitter and a receiver that transmit data rate compensation information in frames, the transmitter determining the required compensation based on the data rate difference and generating data rate compensation information based on the required compensation. The data rate compensation information is distributed in each frame, the data rate compensation information causing the receiver to compensate for the data rate difference by an integer number of bits. The receiver receives the data rate compensation information and determines the necessary compensation based on the data rate compensation information and compensates the data rate difference by an integer number of bits based on the required compensation.

A similar system is known from US 4 930 125.

It is the object of the present invention to transmit to specify the direction for a radio telephone communication system, which performs data rate compensation in a simple manner.

This object is achieved by the subject matter of patent claim 1 solved.

Preferred embodiments of the present invention are Ge subject of the subclaims.

In the following a preferred embodiment of the present ing invention with reference to the accompanying drawings nations explained in more detail. The drawings show in detail nen:  

Fig. 1 generally depicts a radio telephone system, which may include the present invention.

Fig. 2 shows the structure of a V.110 frame as defined by CCITT Recommendations V.110.

Figure 3 shows two consecutive V.110 frames that form a multi-frame in accordance with the present invention.

Fig. 4 generally shows an apparatus which performs the adaptation of independent clock rates in a transmitter according to the invention.

Fig. 5 generally shows an apparatus which performs the adjustment of independent clock rates in a receiver according to the invention.

Fig. 6 shows, generally in accordance with the present invention, in the form of a flow diagram, the steps the IWF performs to adjust independent clock rates and transmit data.

Fig. 7 generally shows, in accordance with the present invention, in the form of a flow diagram, the steps performed by the IWF to adjust independent clock rates and receive data.

Fig. 8 shows, generally in accordance with the present invention in flow chart form the steps that performs a communication system, to transmit data from one network having independent clock sources to another network with un-dependent clock sources.

Fig. 1 generally depicts a communication or sparked lephonsystem, which may include the present invention. A public switched telephone network (PSTN) / digital network with integrated services (ISDN) 100 is connected to a mobile network (MN) 106 . The PSTN / ISDN 100 generally includes a land-based telephone system and computers or other data transfer hardware that may require modems to transmit data. A modem data call in the radio telephone system of Fig. 1 is made as follows. A caller in the PSTN 100 starts a call to the mobile control center (MSC) 105 in the MN 106 . The call is sent to the MSC 105 in audio form, where it is then routed to a data interface or gateway (IWF) 125 . The IWF 125 converts the audio format of the data coming from the PSTN 100 into a digital format (similar to ISDN) in the MN 106 . The digital data is processed in a data transmission frame or V.110 frame format, which is a standard rate adjustment frame used in the MN 106 . The V.110 frame then goes into a base station system (BSS) 115 , where it is further processed into a standard radio interface format as specified in the GSM recommendation 4.21 , version 3.2.0 , March 1990. The data contained in the GSM radio interface frame is transmitted via an antenna 120 . A mobile unit 110 receives the radio interface frame that contains the data and processes the data back into the V.110 format (not shown).

In the system shown in FIG. 1, it is not necessary that the PSTN / ISDN 100 be synchronized with the MN 106 . When synchronized, the corresponding clock signals that drive the modem 126 in the IWF 125 are synchronized with the rate adjustment block 127 in the IWF. As a result, clock matching between modem 126 and rate matching block 127 is not required. However, if the two networks are not synchronized, the clock driving the modem 126 is not adapted to the clock used in the rate adjustment block 127 . For non-radio telephony applications, the CCITT recommendations for the V.110 framework provide a mechanism to compensate for the problem of unmatched clocks. The procedure, which depends on the data rates used, adds or deletes full bits, 1/2 bits and 1/4 bits of the V.110 frame as required to speed up or slow down the data rate.

Fig. 2 shows the structure of a V.110 frame as defined in the CCITT recommendation V.100. The V.110 frame has 10 octets, each octet having 8 bits. The octet 0 comprises 8 "0" bits and is used for synchronization purposes. The first bit of each subsequent octet is a "1" bit and is again used for synchronization purposes. The remaining bits in the V.110 frame include three types of bits. D bits carry the user data stream, S and X bits carry the modem status signals, and E bits carry the user data rate and clock compensation information. In the preferred exemplary embodiment, the E bits, in particular E4, E5, E6 and E7, are modified in the clock compensation method according to the invention. Fig. 3 illustrates generally a first V.110 frame 300 and a second V.110 frames 305 which are transferred to form a multi-frame 310, which is the implementation of the preferred embodiment. The use of four E-bits from each of the two V.110 frames forms an 8-bit code word that is coded forward error corrected (FEC). So 2 of the 8 E bits are used to represent the clock compensation states, while the remaining 6 E bits are used to correct the multiframe forward error.

Because the radio interface uses a smaller bandwidth than the V.110 frame, some of the bits in the V.110 frame must be removed and / or compressed. If the compensation mechanism listed in CCITT Recommendation V.110 were used, the added or deleted 1/2 or 1/4 bits would be lost in the removal or compression of hits in the base station system (BSS) 115 of the MN 106 go. In addition to the mapping problem between the radio interface and the V.110 frames, the high BER could cause data bits to be incorrectly added or deleted. This corruption changes the number of data bits transmitted, which consequently leads to serious data errors.

Fig. 4 generally shows the hardware that performs clock rate adaptation according to the present invention. A pulse code modulated (PCM) signal, typically used for audio communications in digital branches or links, is input to an analog / PCM block 124 . The PCM line contains elements of audio and clock, CLK1, PSTN 100 . The clock information designated CLK1 is extracted from the modem 126 . The user data goes from the analog / PCM block 124 , where it is reformatted to its raw data form, into the modem. The CLK1 signal is used to clock the raw data symbolized by the DAT line exiting the modem 126 . At this point, the DAT line contains data that is clocked at a first clock rate or CLK1. The modem 126 leaving data 126 are input into a data buffer 400, the passungsblock in the Ratenan 127 is located. The data is clocked in the buffer 400 at a second clock rate CLK2, which is derived from the MSC 105 . The data buffer 400 receives the data from the DAT line. At this point, the clock difference between CLK1 and CLK2 is determined. This determination is made by setting pointers in the data buffer 400 . For example, one pointer measures the rate at which data bits go into data buffer 400 , which would be the rate of CLK1, and a second pointer measures the data rate at which data exits buffer 400 , which would be the rate of CLK2, that clocks data from buffer 400 . If CLK1 is less than CLK2 by a lower threshold, a clock underspeed condition results. In this state incoming data coming into the buffer 400 on the DAT line slower in the data buffer 400 as they exit the data buffer 400th In order to match the two clock rates to one another, an entire bit is deleted in the data leaving the data buffer 400 if the clock underspeed falls below a lower limit. Similarly, if CLK1 is greater than CLK2 by a lower threshold, a clock overspeed condition arises. In this state, data coming into the buffer 400 on the DAT line come into the data buffer 400 faster than they leave the data buffer 400 . In this state, the rate of the data leaving the data memory 400 must increase, therefore an entire bit is added to the data leaving the data buffer 400 . This addition occurs when the difference in the two clock rates exceeds an upper threshold. If the difference between CLK1 and CLK2 is not above or below the upper or lower threshold, the data leaving the buffer 400 is not changed.

Four clock compensation states are in the preferred one Embodiment possible and in Table 1 only for Illu shown for purposes of stration; the state pattern depending The bit pattern can vary depending on the system design to change.  

Table 1

Table 1 generally shows the clock compensation states and their corresponding function and bit pattern and is again for illustrative purposes only. In the event that the two clocks are essentially equivalent, no change in the data bits leaving the buffer 400 is necessary, so state 1 , which does not represent a change, can correspond to a bit pattern of "00". In a clock underspeed state where there is a requirement to clear a bit, a second state or state 2 can be represented by a bit pattern "01". At a clock overspeed, 2 separate states are necessary because the clock overspeed state requires that a bit be inserted into the outgoing data bits; the bit used can be either a "0" or a "1". State 3 then corresponds to the insertion of a "0" bit and can be represented by a bit pattern "10", while state 4 corresponds to the insertion of a bit "1" and can be represented by a bit pattern "11". Hysteresis capability can be added by setting two thresholds for each pointer depending on the state of the compensation.

The correct clock compensation is determined by a digital signal processor (DSP) 406 and a microprocessor (µP) 405 , which in the preferred embodiment are a Motorola 56001 DSP and a Motorola 68020 µP. The µP monitors the pointers in buffer 400 and determines the appropriate state and bit pattern by comparing the rate at which data enters buffer 400 to the rate at which data leaves buffer 400 . Since the µP 405 receives data from the modem 126 , the µP 405 formats the data in a V.110 frame. As soon as the required compensation state is determined, the DSP 406 changes the number of data bits in the multiframe 310 accordingly. When the µP 405 determines that no change is necessary, a bit pattern "00" is used as a compensation state, and there is no change in the number of data bits D in the multiframe. If the µP 405 determines that there is a clock underspeed, ie state 2 , a bit pattern "01" is used in two of the eight E bits in the multiframe 310 . In this case, the port receiving the multiframe 310 will ignore the data bit immediately following the E bits of the second V.110 frame 305 . If the µP 405 determines that the number of data bits in the multiframe 310 must be increased by one bit, the µP 405 increases the number by adding a "0" or "1" bit in the total user data bits. This occurs between the last data bit preceding the E bits and the first data bit following the E bits in the second V.110 frame.

The IWF 12 has a duplex system so that it also receives the V.110 frames that have been sent and changed. Fig. 5 shows the receive and change process from the V.110 frame to the raw data as requested by the modem 126 as input. A data receiver 500 receives the multiple frame 310 , which in turn consists of a first V.110 frame 300 and a second V.110 frame 305 . The frames are entered into a DSP 506 and a µP 505 , which in turn are a Motorola 56001 DSP and a Motorola 68020 µP in the preferred embodiment. The µP 505 and DSP 506 are clocked by CLK2, which is derived from the MN ( 106 ) clock. Depending on the genes are received, compensating state 506 decodes the DSP the pre Windwärts error correction that was performed at the Kompensationszustandsbits, and sends the decoded state to uP 505, where the data bits of the multi-frame 310 entspre be amended accordingly. For example, if the compensation state is state 2 , the microprocessor ignores the data bit immediately following the E bits of the second V.110 frame 305 . If the decoded state is such that state 3 or 4 is present, the microprocessor adds one bit into the raw data leaving microprocessor 505 . The output of the microprocessor 505 is input into a data buffer 507 , which in turn has a clock input CLK2. By using the correct compensation, the µP 505 generates the new rate for the modem 126 , into which data is clocked at CLK1. The data is transferred to the Analog / PCM block 124 where it is converted to a PCM signal and transferred back to the MSC 105 . At this point, again referring to FIG. 1, the MSC 105 transmits the data to the PSTN / ISDN networks 100 in an audio modulation format using PCM elements.

Fig. 6 generally shows, in flow diagram form, the steps the IWF performs in accordance with the invention to adjust independent clock rates and transmit data. The process in the IWF begins at 600 by providing a clock with a second clock rate at 603 and assuming at least a predetermined number of network information bits and data bits at a first clock rate at 606 . The µP 405 then determines 609 the difference between the first clock rate and the second clock rate. The DSP 406 changes the predetermined number of data bits at 612 by an integer multiple of bits, and the data transmitter 420 sends at 615 at least one network information bit and changed data bits at the second clock rate.

Figure 7 generally shows, in flow chart form, the steps the IWF performs in accordance with the invention to adjust independent clock rates and receive data. The process in the IWF begins at 700 when a data receiver 500 receives at least 703 a frame at a second clock rate. The DSP 506 determines the clock compensation state at 706 , the µP 505 changes the number of data bits by at least one data bit at 709 and the clock setting block 501 sets the second clock rate at 712 so that it is adapted to the first clock rate of the determination network.

Fig. 8 shows, generally in flow chart form the steps that performs a communication system to transmit data from one network having independent clock sources in a network to be transmitted to more complete with independent clock sources in accordance with the invention. The process begins at 800 when the first data interface at 803 provides a second clock at a second clock rate. The first data interface then receives at 806 at least a predetermined number of network information bits and data bits at a first clock rate and determines at 809 the difference between the first and the second clock rate. The first data interface then changes the predetermined number of data bits by at least one data bit at 812 and sends at 815 at least one network information bit and at least the changed data bits at the second clock rate. The second data interface then receives at least one network information bit at 818 and at least the changed data bits at the second clock rate and determines the compensation state at 821 . The second data interface then changes the number of data bits by at least one data bit at 824 and sets the second clock rate at 827 in order to adapt it to the clock rate of the destination network.

This method of clocking independent clock sources across networks is not only used in IWF 125 , but can also be used in mobile units 110 , which may also require clocking to an independent source. In addition, the described methods can be used in a pure ISDN environment, where separate, asynchronous ISDN clock sources are used.

Since the preferred embodiment of the fiction device is a digital radio telephone system high BER rates during transmission over the radio interface do not pose unusual. By using two bits to Representation of the clock compensation state and the lead If six bits are used as forward error correction, the Emp sensitivity to the high BER rates in digital radio phone can be reduced. In the preferred embodiment For example, two V.110 frames for a total of eight E bits used. To the sensitivity to the high BER rates can do even more two consecutive V.110 frames are used, what to use more E bits in the forward error correction door leads. In addition, other methods of moving forward error correction can be used. For example, by Use of a V.110 frame with a total of four E bits, and by using two E bits for clock compensation tion and the remaining two E bits and additional ones S and X bits for forward error correction, the reduction sensitivity to high BER still he be enough. Similarly, anything from one of the E bits to to four of the E bits used for clock compensation in the V.110 Frames used are used as the clock compensation state  and the forward error correction can be done by Repeating a certain state over a given one Number of V.110 frames can be reached. In this Scenario, the initial V.110 framework would have a certain Condition, and the subsequent V.110 frame would be densel ben condition included, and when the system is satisfied and the "correct" state of compensation has been obtained, different V.110 frames will continue to be used which receive clock compensation states. Any Number of forward error correction schemes can be used become.

By using the device according to the invention and the method in a radio telephone system, such as a GSM, will address the problem of asynchronous / independent customization Clock sources solved. The process changes data bits in one V.110 frame by at least one complete data bit, which means that si It is made that the compression and optimization the radio interface does not lose the data bits which, if if they are broken, lost. The reliability the transmission is corrected by the forward error correction Compensation states increased, reducing sensitivity the procedure against errors due to high BERs is gert. In addition, the use of simple data buffers, typically in a data transfer environment Exercise used, used to be expensive and complicated graced phase difference detectors and those for their use required additional scanning techniques Zen.

Claims (8)

1. Transmitting device for a radiotelephone communication system ( 106 ), which forms an interface with a network ( 100 ), the data of which are clocked at a rate which differs from that of the radiotelephone communication system ( 106 ), the transmitting device transmitting data rate compensation information transmits in frames, determines and generates the data rate compensation information required for adapting the data rates of the network ( 100 ) and the radio telephone communication system ( 106 ) to one another on the basis of the data rate difference, distributes these data rates for transmission to at least two ISDN frames and for this Areas are used that are not required for the payload, the data rate compensation information causing a receiver to compensate for the data rate difference by an integer number of bits. 2. Transmitting device according to claim 1, wherein the transmitter is located either in a fixed radio telephone infrastructure device ( 125 ) or in a mobile radio telephone unit ( 110 ). 3. Transmitting device according to claim 1, wherein the receiver is located either in a fixed radio telephone infrastructure device ( 125 ) or in a mobile radio telephone unit ( 110 ). 4. Transmitting device according to claim 2 or 3, wherein the fixed radio telephone infrared structure device ( 125 ) further provides a transfer function (IWF) within the radio telephone communication system ( 106 ). 5. Transmitting device according to claim 1, wherein the at least two ISDN frames further contain at least two V.110 frames ( 310 ). 6. Transmitting device according to claim 5, wherein the data compensation information still has a 5-bit code word. 7. Transmitting device according to claim 6, wherein the areas used for the transmission of the data rate compensation information are formed by the E bits of at least two V.110 frames ( 310 ). 8. Transmitting device according to claim 7, wherein the 5-bit code word within the two consecutive V.110 frames at bit positions E4, E5 and E6 is placed.