DE4241702A1 - Analogue=to=digital converter for electric motor speed control - counts clock pulses produced during period of PWM signal obtd. from error comparison with triangular wave - Google Patents

Abstract

A speed error voltage (7) in analogue form is low-pass filtered (1) to remove noise and higher harmonics, and compared (2) with a triangular wave (8) of constant amplitude and frequency (800 Hz). A pulse-width modulated signal (9) is forwarded to a microprocessor (3) with a clock signal generator (31) which gives a digital output for control of the inverter (4) supplying current to the motor (5). An encoder (6) coupled to the motor gives feedback to the microprocessor so that the speed error is reduced to zero. ADVANTAGE - Does not use integrated circuit. Stable and precise digitisation is achieved independently of the triangular-wave frequency and temp. Resolution is improved by use of earlier measurements.

Description

The present invention relates to an analog / digital Converter circuit and in particular an analog / digital Converter circuit that is used for example in a motor control circuit is executed.

Some motor control circuits use a microprocessor and are software controlled. Fig. 46 shows a conventional motor control circuit which is software controlled as mentioned above. A speed command voltage, which is an analog signal, is passed through a low pass filter 101 to filter out interference voltages and other higher harmonics. The analog output signal from the filter 101 is converted into a digital form by an analog-to-digital converter IC (integrated circuit) 102 and supplied to a microprocessor 103 to control the output frequency of a frequency converter 104 , thereby controlling the speed of an electric motor 105 . The speed of the motor 105 is demodulated by an encoder 106 . The microprocessor 103 calculates the difference between the speed prescribed by the speed command signal and the actual speed of the motor 105 and controls the frequency converter 104 so that the difference is reduced to zero.

The motor control circuit described above is expensive because it is used an analog to digital converter IC. It is also required the analog to digital converter IC over a number of lines, e.g. B. 10 or 12 lines, depending on the number of Bits to connect to the microprocessor. The input / Output ports of the microprocessor are therefore through the Lines occupied which originate from the A / D converter IC. Thereby it is impossible to use the microprocessor effectively.

In view of the above prior art Disadvantages, it is the object of the present invention  to provide an analog / digital converter circuit, at the an analog to digital converter IC is unnecessary to the cost to lower the ports of a microprocessor effectively usable are, the conversion efficiency neither by tempera fluctuations in the door are still affected by aging digital output data of the inexpensive analog / digital Converter circuit will not be affected if the DC component of one for the analog / digital conversion used triangular wave depending on the tempe rature or if the offset voltage of the comparator changes the temperature changes, the resolution and insensitivity an alarm signal is improved compared to interference voltages Message is generated that the digital signal is abnormal len value when the level of a speed command signals exceeds the amplitude of a triangular wave and a pulse width modulated signal with its high or low level is also coupled, an alarm signal for Message is generated that the digital signal is abnormal paint value when the pulse width modulated signal from the start of operation with the high or low level is coupled, and with an improved engine control unit is provided that shuts off the engine to its to prevent uncontrolled and abnormal operation if the level of the speed command signal is the amplitude of a Triangular wave exceeds and a pulse width modulated Signal is coupled to its high or low level.

This object is achieved by an analog / Digital converter circuit with the features of the patent say 1 or 5 or 6 or 8 solved.

Various advantages of the invention include:

• 1. Elimination of the dependence on the frequency of the Triangular wave signal to ensure stable and accurate To achieve conversion into digital form;
• 2. Elimination of the dependence of the change on the Temperature by subtracting the data from the Pulse duration of a square wave from the data related the pulse duration of the pulse width modulated wave;
• 3. Application of the invention to a speed command signal for an engine including a device for Stop the motor when the speed command signal exceeds the amplitude of the triangular wave signal;
• 4. Use of previous measured values to improve the on solution of the converter;
• 5. Use an alarm with the converter to safely make sure that he is in perfect operating condition located; and
• 6. Eliminate the need for all of the above Points after an analog / digital converter IC.

The present invention is illustrated by the following Description and the accompanying drawings.

The drawings show:

Fig. 1 is a block diagram of a motor control circuit with the analog / digital converter circuit corresponding to Example 1 according to the invention;

Fig. 2 is a flowchart for explaining the function of Example 1;

Fig. 3 is a block diagram of a motor control circuit with the corresponding Example 2 analog / digital converter circuit according to the invention;

Fig. 4 is a block diagram of a motor control circuit with the analog / digital converter circuit corresponding to Example 3 according to the invention;

Fig. 5 is a flowchart for explaining the function of Example 3;

Fig. 6 is a flow chart for explaining the pulse width conversion operation of Example 3;

Fig. 7 is a block diagram of a motor control circuit with the appropriate Example 4 analog / digital converter circuit according to the invention;

Fig. 8 is a flowchart for explaining the operation of Example 3;

FIG. 9A and 9B flowchart for explaining the problems of pulse width conversion operation, when the present invention is not applied;

FIG. 10 is a block diagram of Example 5 of an analog / digital converter circuit according to the invention;

Fig. 11 is a flowchart for explaining the operation of Example 5;

Fig. 12 is a block diagram of a model of the comparator used in Example 5;

Fig. 13 is a waveform diagram with models of the triangular waves used in game 5 ;

FIG. 14 is a block diagram of a model in which the temperature dependence of Example 5 is taken into into account;

FIG. 15 is a block diagram of another model in which the temperature dependence of Example 5 is taken into taken into;

Fig. 16 is set in which the offset voltage difference between the two comparators to zero a block diagram of the model of Example 5;

Fig. 17 is a flowchart for explaining the model of Figure 16, in which the DC component of the triangular wave and the offset voltages of the comparators change with temperature.

Fig. 18 is a flowchart similar to that of Fig. 17, but showing a different case;

FIG. 19 is a block diagram of a model is assumed in that the offset voltage difference between the two comparators Example 5 is in accordance with temperature unaffected by the Tem;

Fig. 20 is a flowchart for explaining the operation of the model of FIG. 19;

FIG. 21 is a flowchart for explaining an interrupt operation of Example 6 of an analog / digital converter circuit according to the invention;

Fig. 22 is a waveform diagram for explaining the effects of resolution improvement under certain conditions in Example 6;

Fig. 23 is a waveform diagram for explaining the distorting effects of the resolution enhancement under other conditions in Example 6;

FIG. 24 is an equivalent circuit diagram of a gebil Deten by Example 6 low-pass filter;

FIG. 25a and 25b are flow charts for explaining an interrupt operation according to a modification of Example 6, an analog / digital converter circuit of the invention;

Fig. 26 is a flowchart showing an interrupt operation of another modification of Example 6, an analog / digital converter circuit according to the invention;

Fig. 27 is a waveform diagram for explaining the effects of resolution improvement in the example of Fig. 26 under certain conditions;

FIG. 28a, 28b and 28c block diagram for explaining ver VARIOUS further modifications of Example 6, an analog / digital converter circuit according to the invention;

Fig. 29 is a flowchart for explaining the operation of the example of Fig. 28 (a);

FIG. 30a and 30b are flow charts for explaining an inter-rupt-operation of the embodiment of Fig 28 (a).

Fig. 31 is a flowchart for explaining the operation of the example of Fig. 28 (b);

FIG. 32a and 32b are flow charts for explaining an inter-rupt operation of the embodiment of Fig 28 (b).

Fig. 33 is a flowchart for explaining the operation of the example of Fig. 28 (c);

FIG. 34 is a flowchart for explaining an interrupt operation of the example in FIG. 28 (c);

FIG. 35 is a block diagram of another modification of Example 6, an analog / digital converter circuit according to the invention;

Fig. 36 is a flowchart for explaining the operation of the example of FIG. 35;

FIG. 37a, 37b and 37c are flow charts for explaining an interrupt operation of the various functions Modifika of FIG. 35;

Fig. 38 is a block diagram of another modification of Example 6, an analog / digital converter circuit according to the invention;

Fig. 39 is a flowchart for explaining the operation of the example of FIG. 38;

FIG. 40 is a block diagram of a motor control circuit with the corresponding Example 7 A / D converter circuit according to the invention;

FIG. 41 is a flowchart for explaining an example of the operation of Example 7;

Fig. 42 is a flowchart for explaining another example of the operation of Example 7;

Fig. 43 is a flowchart for explaining the function of the functions added in Example 7;

FIG. 44 is a triangular wave generator circuit;

Fig. 45 is a flowchart for explaining the operation of the engine control unit shown in Fig. 44; and

Fig. 46 is a block diagram of a motor control circuit with a conventional analog / digital converter circuit.

example 1

An example of an analog-to-digital converter circuit according to the present invention will be described below with reference to FIGS. 1 and 2. The example shown is designed for use in a circuit for controlling the speed of an electric motor in the same way as the conventional circuit which is described with reference to FIG. 46.

Referring to Fig. 1, a speed command is voltage-7, is an analog signal when applied to a low pass filter 1. The output of the filter 1 and a triangular wave 8 are applied to a comparator 2 . The output of the comparator 2 is connected to a microprocessor 2 with a clock generator 31 . The microprocessor 3 generates a digital signal corresponding to the speed command voltage 7 , using the internal clock pulses and the clock generator 31 . The microprocessor controls an inverter or frequency converter 4 in such a way that the difference between the speed of a motor 5 , which is reported by the output signal of an encoder 6 , and the speed reported by the above-described digital signal is reduced to zero.

The operation of the example described above is also described below with reference to FIG. 2. The speed command voltage 7 contains interference voltages as well as other higher harmonics, as shown in Fig. 2 (a). This speed command voltage 7 is passed through the low-pass filter 1 to remove the higher harmonics from the output of the low-pass filter. This output is identified by reference numeral 71 in FIG. 2 (b).

The output 71 of the low-pass filter corresponding to the speed command voltage is compared by the comparator 2 with the triangular wave, which has a constant frequency and a constant amplitude. As shown in FIG. 2 (b), the position in which the output 71 of the low-pass filter, which corresponds to the speed command voltage 7 , intersects the triangular wave 8 changes according to the level of the output 71 . The output of the comparator 2 therefore takes the form of a pulse width modulated signal 9 which changes in accordance with the level of the low-pass filter output 71 according to FIG. 2 (c). In other words, the width or duration of the high level of the pulse width modulated signal 9 indicates the amplitude of the speed command voltage 7 . The triangular wave compared to the speed command voltage includes a sawtooth wave in all examples of the present invention, including the example being discussed.

As is known to those skilled in the art, the clock 31 of the microprocessor 3 has a counter which counts the internal clock pulses of a given frequency according to FIG. 2 (d). The clock 31 counts those of the clock pulses that appear within the high level period of the pulse-width modulated signal 9 , as shown in FIG. 2 (e). The total count value determined by the counter is therefore a digital value. The counter of the clock 31 is initialized such that its total count is stored in the counter buffer on the leading edge of the pulse width modulated signal 9 as shown in Fig. 2 (f) and the counter triggers an interrupt to clear the total count . The total count value obtained on the trailing edge of the pulse width modulated signal 9 is stored in the counter buffer as shown in FIG. 2 (g).

In this way, the speed command voltage 7, as shown in FIG. 2 (a) is an analog signal is converted into a digital form by a series of operations of Fig. 2 (b) to Fig. 2 (g) passes. The value of the counter buffer, which is a digital signal, serves as a prescribed speed for the speed control provided by the software. In particular, the microprocessor 3 calculates the difference between the speed of the motor 5 demodulated by the encoder 6 and the digitized speed command value and controls the frequency converter 4 such that the difference is reduced to zero.

In the following, the resolution of the above example is dealt with using numerical values. The frequency of the internal clock pulses of the microprocessor is 8 MHz. The value of the digital output varies from 9 to 9999. This means that the resolution is 13.3 bits (= log ₂ 10000) and thus exceeds the resolution of 12 bits of the analog / digital converter IC.

The response frequency is dealt with below. Since the Frequency of the triangular wave as described above 800 Hz carries, the digital output data are updated with 800 Hz lized. The sampling theorem makes it impossible to use analog ones Input frequencies of over 400 Hz as output data again admit. If the signal with a frequency twice as high how the signal frequency is sampled, so according to the Theorem almost completely replaces the original signal given. The one used in the engine speed control However, the cut-off frequency is approximately 100 Hz, so that at Controlling the engine speed no practical problems to step.

In example 1 described above, an analog / digital Converter circuit consisting of only one comparator and its peri Therapy components are manufactured without one  To use analog to digital converter IC; The A / D converter circuit can therefore be manufactured economically. If control by software using a microprocessor is between the comparator and the microprocessor only one conductor wire required. This allows the ports of the Microprocessor can be used effectively. When using the A / D converter circuit in an engine speed control circuit puts the response frequency under a practical face score no problem. The resolution exceeds that Use of an analog / digital converter IC in the known Techniques achievable resolution.

In example 1, those clock pulses are counted which are present within the duration of the high level of the pulse width modulated signal, as shown in FIG. 2 (c), (d) and (e). It is also possible to count the clock pulses that are present within the duration or period of the low level of the pulse width modulated signal. In this case, the total count decreases with increasing speed command voltage. Furthermore, the total count can be multiplied by a constant value or; be divided by this.

The triangular wave 8 described above with a given frequency and a given amplitude is generated by a triangular wave generator circuit according to FIG. 44 (a), (b). This generator circuit fulfills the functions of three components, ie an output amplitude limiter, a comparator and an integrator.

An operational amplifier Op ₁ integrates the output of an operational amplifier Op ₂ and converts the incoming square wave into a triangular wave. The output amplitude of the square wave, ie the output of the triangular wave generated, is set in accordance with the Zener voltage of a Zener diode Z _D , which functions to limit the amplitude of the output. The output voltage of the square wave is precisely determined by both the diode forward voltage V _F and the Zener voltage V _Z , as shown in Fig. 44 (b).

According to the present invention, the circuit is under Designed to take temperature dependence into account to suppress the effects of temperature fluctuations. That is, the diode forward voltage VF has a tempera turcoefficient of 1.9 mV / ° C, so that a temperature coefficient of +4.0 mV / ° C is provided. For this reason can be the temperature coefficient of the triangular wave output amplitude by means of the Zener diode ZD with 8.2 V to zero ge be brought.

Example 2

FIGS. 3, Example 2 shows that a gate array or a logic circuit 10 with a clock. 11 Corresponding elements are marked with the same reference numerals. When using the clock generator 11 of the gate array 10 , those clock pulses are counted which occur during the duration of the high or low level of the pulse-width-modulated signal from a comparator 2 . For this reason, the clock in a microprocessor 12 is not used. The gate array 10 is connected to the microprocessor 12 via a data bus 13 and an address bus 14 with a suitable number of bits.

The operation of the example 2 shown in FIG. 2 is identical to that of the game 1 described above, so that a description is omitted here. Example 2 does not require the use of an analog / digital converter IC either. However, the number of components is higher. The number of connecting wires between the gate array 10 and the microprocessor 12 is large. Consequently, example 1 shown in FIG. 1 is preferable to example 2. Note that the present invention is not limited to engine speed control circuits; the invention is also applicable to various analog / digital converter circuits.

Example 3

As already described in Examples 1 and 2, the speed command signal 7 can be converted into a digital form if the counter of the microprocessor 3 counts only those clock pulses that occur during the duration of the high level of the pulse width modulated signal 9 . However, if only those clock pulses are counted that occur during the duration of the high level of the pulse width modulated signal 9 , the total count is affected by frequency fluctuations of the triangular wave 8 , which are caused by temperature fluctuations or aging. The result is a deterioration in the accuracy of the analog / digital conversion. The reason for this is explained in detail below.

As shown in Figs. 9A and 9B, the case in which the frequency of the triangular wave 8 is low is different from that in which the frequency is high. It is assumed that the amplitude of the triangular wave 8 is constant and the level of the output 71 of a low-pass filter 1 is also constant. At a low frequency of the triangular wave 8 (see Fig. 9A (a)), the duration of the high level of the pulse-width modulated signal is longer (see Fig. 9A (b)), so that the number of clock pulses counted is larger. As a result, the value of the counter buffer, which is a digital output data, is higher ( Fig. 9A (c)). Conversely, the duration of the high level of the pulse width modulated signal at high frequency of the triangular wave 8 ( FIG. 9B (a)) is shorter, as shown in FIG. 9B (b). This reduces the number of clock pulses counted. As a result, the value of the counter buffer, which is a digital output data, is smaller as shown in Fig. 9B (c).

So if only the clock pulses occurring during the duration of the high level of the pulse-width-modulated signal are counted, a possible frequency fluctuation of the triangular wave 8 due to temperature fluctuations or aging affects the total count. As a result, the accuracy of the analog / digital conversion deteriorates.

Example 3 illustrating relative to Examples 1 and 2 Ver improvement is, with reference to Figs 4 - described. 8. In example 3, the data obtained by analog / digital conversion are not affected by the frequency of the triangular wave 8 . In this example 3, an analog / digital converter circuit for an engine speed control circuit is used in the same manner as in examples 1 and 2 above. It should also be pointed out here that identical components in the various figures are identified by the same reference numerals.

Referring to FIG. 4 is a speed command voltage 7 is applied as an analog signal to a low pass filter. 1 The output of the filter 1 and a triangular wave 8 are applied to a microprocessor 3 , which has two counters 32 and 33 , which correspond to the clock generator 31 of Examples 1 and 2. The microprocessor 3 generates a digital signal corresponding to the speed command voltage 7 , using the total count values of the counters 32 and 33 . The microprocessor controls a frequency converter 4 in such a way that the difference between the signal of an encoder 6 , which reports the speed of an electric motor 5, and the digital signal is reduced to zero.

The mode of operation of Example 3 is also described below with reference to FIG. 5. The speed command voltage 7 contains interference voltages as well as other higher harmonics, as shown in Fig. 5 (a). This voltage 7 is passed through the low-pass filter to remove the higher harmonics. The output of this filter is identified by reference numeral 71 in FIG. 5 (b).

The output 71 of the low-pass filter corresponding to the speed command voltage is compared by the comparator 2 with the triangular wave 8 , which has a constant frequency and a constant amplitude. As shown in FIG. 5 (b), the position where the output 71 of the low-pass filter, which corresponds to the speed command voltage 7 , intersects the triangular wave 8 changes according to the level of the output 71 . The output of the comparator 2 therefore takes the form of a pulse width modulated signal 9 which changes in accordance with the level of the low-pass filter output 71 according to FIG. 5 (c). In other words, the width or duration of the high level of the pulse width modulated signal 9 indicates the amplitude of the speed command voltage 7 . In this game 3, the components are connected so that the output of the comparator 2 , ie the pulse width modulated signal 9 , is at a high level when the output voltage of the low-pass filter 1 exceeds the voltage of the triangular wave.

The microprocessor 3 generates internal clock pulses of a given frequency, which are to be counted by the counters 32 and 33 . These clock pulses are shown in Fig. 5 (d). The first counter 32 of the microprocessor 3 counts those of the clock pulses that appear within the duration of the high level of the pulse width modulated signal 9 , as shown in FIG. 5 (e), while the second counter 33 counts those of the clock pulses that occur within the duration of the low level of the pulse width modulated signal 9 , as shown in Fig. 5 (f). The first counter 32 is initialized such that its total count is stored in the counter buffer on the leading edge of the pulse width modulated signal 9 . The counter 32 then initiates an interrupt and clears the total count. The second counter 33 is initialized in such a way that it loads the total count value into the counter buffer on the leading edge of the pulse-width-modulated signal 9 , leaves an interrupt and clears the total count value.

Th (n) is the value held in the counter buffer of the first counter 32 . Tl (n) is the value held in the counter buffer of the second counter 33 . "(n)" means that the value corresponds to the nth scan. The microprocessor 3 calculates the sum from the values held in the counter buffers
Th (n) + Tl (n) = T all (n)
((Duration of the high level) + (duration of the low level) total duration of the triangular wave))
T all (n) indicates the total duration of the triangular wave when the nth sample is taken. The microprocessor 3 then calculates (Th (n)) / (T all (n)), ie ((duration of the high level) / (total duration of the pulse width modulated signal 9 )).

The signal obtained in this way is a digital signal. That is, the speed command voltage, which is an analog signal as shown in FIG. 5 (a), is converted to a digital form by going through a series of operations as shown in FIG. 5 (af). In particular, the microprocessor 3 calculates the difference between the speed of the motor 5 demodulated by the encoder 6 and the digitized speed command value and controls the frequency converter 4 such that the difference is reduced to zero.

In example 3 above, the calculated value of ((duration of the high level of the pulse width modulated signal 9 ) / (total duration)) is used. In this case, if the frequency of the triangular wave 8 fluctuates, the digitized value is not affected. The reason for this will now be explained with reference to FIGS. 6a and 6b. Fig. 6 (a) shows a case where the frequency of the triangular wave 8 is high. Fig. 6 (b) shows a case where the frequency of the triangular wave 8 is low. Referring to FIG. 6 (a), let A and C be two adjacent peaks of the triangular wave 8 . B is the minimum between these two peaks A and C. D and E are the points at which the output Vin of the low-pass filter intersects the triangular area Δ ABC. Vam is the voltage in the tips A and C of the triangular wave 8 . Vam is the voltage in the minimum B. Ta ₁ (n) is the total duration of the pulse width modulated signal and thus the total duration of the triangular wave 8 . Th ₁ (n) is the duration of the high level of the pulse width modulated signal. Referring to Fig. 6 (b), A ', B', C ', D' and E 'are the points corresponding to the points A, B, C, D and E shown in Fig. 6 (a). Ta ₂ (n) is the total duration of the pulse width modulated signal or the total duration of the triangular wave 8 . Th ₂ (n) is the duration of the high level of the pulse width modulated signal.

Taking into account the similar ranges ΔABC and ΔDBE in FIG. 6 (a), the relation or equation applies

{[Th₁ (n)] / Ta₁ (n)} = (Vam + Vin) / 2Vam (1)

Analogously, in the case of FIG. 6 (b), the relation or equation applies

{[Th₂ (n)] / Ta₂ (n)} = (Vam + Vin) / 2Vam (2)

The relationship results from equations (1) and (2) or equation

{[Th₁ (n)] / Ta₁ (n)} = {[Th₂ (n)] / Ta₂ (n)} = (Duration of high level) / (total duration) = pulse duration (3)

In this way, the value for ((total duration of the high level of the pulse width modulated signal 9 ) / (total duration)) is kept constant, regardless of whether the frequency of the triangular wave 8 is high or low. This means that the pulse width modulated signal 9 does not depend on the frequency of the triangular wave 8 . For this reason, the value for ((number of clock pulses counted during the duration of the high level) / (number of clock pulses counted during the total duration)) does not depend on the frequency of the triangular wave 8 . The same result is obtained if the number of clock pulses counted during the duration of the high level and the number of clock pulses counted during the total duration are multiplied by a constant value. The same result is obtained if the value for ((number of clock pulses counted during the low level duration) / (number of clock pulses counted during the total duration)) is calculated or if the quotient is multiplied by a constant value by a constant value becomes.

Example 4

Various modifications of Example 3 are described below. In the case of the game 3 shown in FIG. 4, the two counters 32 and 33 integrated in the microprocessor 3 count the clock pulses occurring during the high level of the pulse-width-modulated signal 9 and the clock pulses occurring during the low level. A counter can act as a total duration counter that counts T all (n). The other counter may be active and count Th (n) during the duration of the high level. This other counter can also operate during the low level period and count Tl (n) or Th (n) by calculating the difference
Th (n) = T all (n) - Tl (n)
determine.

As described above, Example 3 uses two counters in microprocessor 3 . Fig. 7 shows Example 4, in which a counter 34 is provided for signal processing in the microprocessor. The processing method is shown in FIG. 8. The counter 34 is cleared on the leading and trailing edges of the pulse width modulated signal. At this time, the peak value held in the counter 34 is loaded into the counter buffer. As points a and b of FIG. 8 show, a decision is made immediately after the flanks of the pulse width modulated signal 9 as to whether the level of the pulse width modulated signal 9 is high or low. If the level in point a is low, the measurement value loaded immediately beforehand into the counter buffer is regarded as the measurement value obtained during the duration of the high level. If the level in point b is high, the measurement value loaded into the counter buffer immediately before is regarded as the measurement value obtained during the duration of the low level. The total duration is obtained by adding these two measured values. Thereafter, the value is processed in the same manner as in Example 3 above to obtain digital data.

As already explained in connection with equation (3), the value for ((duration of the high level) / (total duration)) does not depend on the frequency of the triangular wave 8 . If the digital output data are treated in the form of ((duration of the low level) / (total duration)) or as a multiple of this quotient, the data do not depend on the frequency of the triangular wave 8 .

Example 5

In Examples 3 and 4 described above, one Analog / digital converter circuit without using a Analog / digital converter IC can be manufactured. If the Frequency of the triangular wave changes for some reason the digital output data are not affected. In of the analog / digital converter circuit described above However, for the following reason, the digital output data with temperature.

It is assumed that the analog signal 7 shown in FIG. 4 has a constant voltage. If the pulse duration of the pulse width modulated signal 9 or the value for ((duration of the high level) / (total duration)) is constant, then that of the equation should

Dout (n) = {[Th (n)] / [T all (n)]} × (constant) (4)

corresponding output data to be constant. However, the pulse duration of the pulse width modulated signal 9 changes with the temperature fluctuations. As a result, the output data described by equation (4) will also change. The three main reasons for the fluctuations in the pulse duration of the pulse width modulated signal 9 are as follows:

• 1) The amplitude of the triangular wave changes with the Temperature.
• 2) The DC component of the triangular wave changes yourself with the temperature.
• 3) The offset voltage of the comparator changes with the Temperature.

The above cause ( 1 ) can be eliminated in a simple and economical manner by configuring the circuit by taking the temperature dependence of the analog devices forming the triangular wave generator circuit into account. However, if the circuit devices are chosen so that the above problems ( 2 ) and ( 3 ) are avoided without taking any other countermeasures, the costs increase considerably.

In particular, the cause of the temperature dependency of Example 3 shown in FIG. 4 is dealt with below. FIG. 12 shows a model of a comparator. A triangular wave model is shown in FIG. 13. The actual comparator 2 shown in FIG. 12 (a) can be regarded as an ideal comparator 2 a to which an offset voltage Vof according to FIG. 12 (b) is applied. The offset voltage Vof is temperature-dependent. The ideal comparator 2 a compares Vref, ie an analog signal, with (Vtri + Vof), where Vtri indicates the triangular wave 8 .

Fig. 13 (a) shows the ideal triangular wave. Fig. 13 (b) shows the actual triangular wave. The actual triangular wave Vtri can be viewed as the AC component Vac of the ideal triangle wave to which a DC component Vdc is added. The DC voltage component is temperature-dependent. Although the amplitude of the AC voltage component Vac is also temperature-dependent, this dependency can be made negligible compared to the temperature dependence of Vof and Vdc by designing the circuit taking into account the temperature coefficients of the analog devices of the triangle generator circuit, as described above.

As can be seen from FIGS . 12 and 13, the input Vref present at the positive connection of the comparator 2 is compared with (Vtri + Vof) = (Vac + Vdc + Vof). The temperature dependence of Vdc and Vof creates problems. The above problems ( 2 ) and ( 3 ) are related.

Example 5 of the analog / digital converter circuit is described below with reference to FIGS. 10-20. In example 5, the digital output data are kept constant when problem (2) occurs, ie when the DC component of the triangular wave changes with temperature, or when problem (3) occurs, ie when the offset voltage of the comparator changes with temperature. In this example 5, an analog-to-digital converter circuit is used in the same manner as in Examples 1-4 described above for an engine speed control circuit.

With reference to FIG. 10, an analog signal 7 , ie for example a speed command voltage, is compared with a triangular wave 8 by a first comparator 21 and converted into a pulse width modulated signal 9 . This signal 9 is applied to a first counter 32 which is integrated in a microprocessor 3 which, in addition to the first counter 32, has a second counter 33 . The triangular wave 8 is compared by a second comparator 22 with a constant voltage (in this example the voltage against ground), and a square wave 15 is generated. This square wave 15 is placed on the second count 33 of the microprocessor 3 . The total count of the first counter 32 corresponds to the pulse duration of the pulse width-modulated signal 9 . The total count of the second counter 33 corresponds to the pulse duration of the square wave 15 . The microprocessor 3 generates the digital data Dout ₂ (n), ie the difference between the data relating to the pulse duration of the pulse-width-modulated signal and the data relating to the pulse duration of the square wave 15 . The microprocessor controls a frequency converter 4 in such a way that the difference between the signal from an encoder 6 , which reports the speed of an electric motor 5 , and the analog signal 7 is reduced to zero.

The operation of Example 5 above will also be described in detail below with reference to FIG. 11. The analog signal 7 , which is a speed command signal, is compared by the first comparator 21 with the triangular wave 8 . As shown in FIGS. 11 (a) and (b), the level at which the analog signal 7 intersects the triangular wave 8 changes according to the level of the analog signal 7 . For this reason, the output of the first comparator 21 is the pulse width modulated signal 9 , which changes depending on the level of the analog signal 7 . In this example 5 the components are connected such that when the voltage of the analog signal 7 is higher than that of the triangular wave, the pulse width modulated signal 9 from the first comparator 21 is at the high level.

The second comparator 22 compares the triangular wave 8 with the voltage to ground, ie a constant voltage, and generates the square wave 15 shown in FIG. II (c). Since the triangular wave 8 is compared with the voltage against ground or 0 V, the pulse ratio of the square wave 15 is approximately 50%.

The first counter 32 and the second counter 33 of the microprocessor 3 count the internal clock pulses occurring during the high level and the internal clock pulses occurring during the low level of the pulse-width-modulated signal 9 and the three-wave. Th ₁ (n), Tl ₁ (n), Th ₂ (n) and Tl ₂ (n) are the count values of the periods of the different levels according to FIG. 11, (d), (e), (f) and ( g), indicating that (n) denotes the nth scan. From the above count values, the microprocessor 3 calculates the digital output data Dout ₂ (n) according to the formula

where K is a constant. The first term of equation (5) describes data regarding the pulse duration of the pulse width modulated signal 9 . The second term describes data regarding the pulse duration of the square wave 15 . The third term is a constant value. That is, the equation ( 5 ) indicates the difference between the data regarding the pulse duration of the pulse width modulated signal 9 and the data regarding the pulse duration of the square wave 15 . The denominator "(Th ₂ (n) + Tl ₂ (n))" indicates the total duration. The total time can by calculation with "(Th ₁ (n) + Tl ₁ (n))" of the pulse width modulated signal can be expressed 9, but wherein the pulse width modulated signal contains 9 varying data and a large amount of interference voltages. For this reason, the duration of the square wave 15 with a small proportion of interference voltages is used in this example. Since the pulse ratio of the square wave 15 is approximately 50%, Th ₂ (n) = Tl ₂ (n) applies. Because of this relation, the sum of the second term of equation (5) ((K × Th ₂ (n)) / (Th ₂ (n) + Tl ₂ (n))) and the third term (K / 2 ) is approximately 0. Accordingly, the influence of the first term in equation (5) is large. That is, the second and third terms are correction terms. The effects of the correction are explained below.

In Figs. 14 and 15, the models are shown in Fig. 12 and 13 applied to the in the Fig. 10 shown example. The model shown in FIG. 15 is similar to the model shown in FIG. 14, with the exception that ₁ Vof voltage component by the equivalent constant of a triangular wave is replaced. The Th ₁ (n) and Tl ₁ (n) obtained from the first counter 32 can be regarded as measured values of the pulse width modulated signal which are obtained by comparing the analog signal Vref and the triangular wave (Vac + Vdc + Vof ₁ ). Th ₂ (n) and Tl ₂ (n) can be considered as measured values of the square wave signal, which are obtained by comparing 0 V and the triangular wave (Vac + Vdc + Vof ₁ ) using a comparator with an offset voltage

(Vof₂ - Vof₁) = [(Vof₂ - Vof₁) 25 ° C] + [(Vof₂ - Vof₁) Δt ° C] (6)

be preserved.

The first term on the right side of equation (6) corresponds to the value of (Vof ₂ - Vof ₁ ) at 25 ° C. The second gives the amount of change in (Vof ₂ - Vof ₁ ) when the temperature is different from 25 ° C.

Now the following two conditions should be set so that the value of equation (6) is assumed to be 0 can be:

• 1) The value of ((Vof ₂ - Vof ₁ ) 25 ° C) is set using a controller or software;
• 2) A comparator IC, which contains the first comparator 21 and the second comparator 22 of the example 5 shown in FIG. 10 and in which the temperature dependencies of Vof ₁ and Vof ₂ are substantially the same, is used. By configuring the first comparator 21 , the second comparator 22 and their peripheral circuits so that they are satisfied under the above conditions, the relation (Vof ₂ - Vof ₁ ) = 0 including the temperature dependency can be realized. Condition (1) states that ((Vof ₂ - Vof ₁ ) 25 ° C) according to FIG. 15 or the first term of equation (6) is set to 0. Condition (2) states that ((Vof ₂ - Vof ₁ ) Δt ° C) or the second term of equation (6) is set to 0. If both conditions (1) and (2) are met, then there is zero for the right side of equation (6).

If the above conditions (1) and (2) apply, example 5 in FIG. 10 is equivalent to the model in FIG. 16. In the model in FIG. 16, the same triangular wave (Vac + Vdc + Vof ₁ ) is applied to a first one ideal comparator 21 a and a second ideal comparator 22 a placed. Neither of these two comparators 21 a and 22 a is temperature-dependent. The difference between the temperature dependency of the offset voltages of the first comparator 21 and the second comparator 22 has been eliminated. Th ₁ (n), Tl ₁ (n), Th ₂ (n) and Tl ₂ (n) according to FIGS. 10 and 11 are exactly identical to their counterparts of FIGS. 14-16. Only the models that generate the pulse-width modulated signal and the square wave are different.

FIGS. 17 and 18 show waveforms which arise when the value of (Vdc + Vof ₁₎ of the model is changed as shown in FIG. 16 with the temperature. Fig. 17 shows the waveform when (Vdc + Vof ₁ ) = 0. Fig. 18 shows the waveform when (Vdc + Vof ₁ ) <0. To distinguish these two cases, all Th ₁ (n), Tl ₁ (n), Th ₂ (n) and Tl ₂ (n) of Fig. 18 with a quotation mark "'". If the frequency of the triangular wave is sufficiently high compared to the fluctuations of Vref, and if Vref hardly changes within a period of the triangular wave, then the following relation or equation applies:
Th ₁ (n) + Tl ₁ (n) = Th ₂ (n) ⁺ Tl ₂ (n) = A ^- C.

The same principle applies in the case of FIG. 18.

Assuming that Am in Fig. 17 is the amplitude of the triangular wave, it follows

In the above equation (t) means that Vref is constant changes. It follows from equation (5)

With respect to FIG. 18, the relations or equations are obtained analogously

Equation (5) can therefore be in the form

be transferred, in which a "′" is attached to indicate that the terms come from a diagram with different (Vdc + Vof ₄ ).

Equation (7) states that Vref (t) is linearly related to Dout ₂ (n) and that the analog signal is converted linearly to digital form. Accordingly, equation ( 8 ) states that Vref (t) is linearly related to Dout ₂ (n) and that the analog signal is converted linearly into a digital form. Equations (7) and (8) show that the value of equation (5) is kept constant when (Vdc + Vof ₁ ) changes with temperature fluctuations. If AC differs from A'-C in FIG. 18, equation (7) does not differ from equation (8). That is, the value of the equation (5) remains the same when the frequency of the triangular wave changes.

In the above in Fig. Example 5 shown 10 in accordance with equation (5) result on the basis of from the Fig. 11 entnom menen values of Th ₁ (n), Tl ₁ (n), Th ₂ (n) and n Tl ₂ ( ) in the features: (a) the data remain the same when the DC component Vdc of the triangular wave changes; (b) the data remains the same when the offset voltage Vof _{1 of} the first comparator changes; and (c) the data remain the same when the frequency of the triangular wave changes, if the amplitude of the triangular wave does not change with temperature, ie Vac does not change with temperature, and if the difference between the offset voltage of the second comparator and the Offset voltage of the first comparator is zero, ie equation (6) = 0, or the above conditions (1) and (2) apply.

So if the DC voltage components of the triangle wave changes with temperature, if the offset voltage of the first comparator changes, or if the frequency of the triangular wave changes, the digital data taken from equation (5) remain the same. As a result, an improvement is achieved in terms of temperature dependence. From the above-described condition (2) it can be seen that with substantially the same temperature dependency Vof ₂ and Vof ₁ and with the temperature-changing offset voltage of the second comparator, the digital data given by equation (5) is not determined by the temperature be affected.

The above condition (1), ie ((Vof ₂ - Vof ₁ ) 25 ° C) is used as set to simplify the model and the description. Condition (1) has no influence on the above conclusion. This is described in detail below. In addition, a method for software-based setting of ((Vof ₂ - Vof ₁ ) 25 ° C) instead of setting by means of an externally attached controller is described.

FIG. 19 shows a model in which the change, ie ((Vof ₂ - Vof ₁ ) Δt ° C.) of the offset voltage difference caused by temperature fluctuations between the comparators shown in FIG. 15 is set to zero. Fig. 20 shows the operation of the first ideal comparator 21 a and the second ideal comparator 22 a at this time. The second comparator 22 a compares a triangular wave [Vac + Vdc + Vof₁ + Vof₂-Vof₁) 25 ° C] with 0 V. In Fig. 20b, this triangular wave is shown by the dashed line. If the frequency of the triangular wave is higher than the rate of change of Vref, the following relation or equation applies:

Th ₁ (n) + Tl ₁ (n) = Th ₂ (n) + Tl ₂ (n) = L¯N.

Each of FIGS. 17 and 18 shows the output of the first ideal comparator 21 a and the second ideal comparator 22 a at the same time. The first ideal comparator 21 a compares the triangular wave with Vref. The second ideal comparator 22 a compares the triangular wave with 0 V. FIGS . 17 and 18 show different times. Fig. 20 (a) shows the output of the first ideal comparator 21 a, which compares the triangular wave with Vref. Fig. 20 (b) shows the output of the two ideal comparator 22 a, which compares the triangular wave with 0 V. The Fig. 20 (a) and 20 (b) show the same time point. That is, L¯N in (a) is exactly the same as L¯N in (b). It follows from Fig. 20 (a)

It follows from Fig. 20 (b)

By inserting the two equations above into the equation chung (5) results

This can take the form

to be brought. The comparison with equation (8) from the model according to FIG. 16 shows that only ((K / 2Am) ((Vof ₂ - Vof ₁ ) 25 ° C.)) of the left side is different. This term is not affected by temperature.

For this reason, ((K / 2Am) ((Vof ₂ - Vof ₁ ) 25 ° C)) is always subtracted from the value (Dout ₂ (n)) derived from equation (5) to compensate for the offset voltage. This compensated value is used for (Dout ₂ (n)). In this case, the principle according to FIG. 16 applies to the model according to FIG. 19, in which ((Vof ₂ - Vof ₁ ) 25 ° C.)) is not zero. In this way, the offset voltage can be set by software without the need for an externally attached controller. If the setting of the offset voltage is also taken into account, equation (5) takes the following form

The following describes how {(K / 2Am) [(Vof₂-Vof₁) 25 ° C]} is determined. Equation (5) gives (Dout ₂ (n)) as the analog input Vref = 0 V. At this point in time, the digital data (Dout ₂ (n)) take the value

at.

Since K is a predetermined constant, the digital data result accordingly ((K / 2Am) ((Vof ₂ - Vof ₁ ) 25 ° C)) from the above equation. This means that with an analog input of zero, the deviation of the value of the digital data should be determined by K / 2.

Other examples

The following are various modifications of the example 5 described. The essence of Example 5 goes from the Equation (5). This means

(digital output data) = K × (pulse duration of the output of the first comparator) - (pulse duration of the output of the second Comparators) + 1/2) (11)

where K is a constant. To decrease the number of digits Avoiding by multiplying is the right side had previously been multiplied by K. Of course you can by wisely performing the arithmetic operation the multiplication by K is omitted. In the equation above specifies (1/2) the amount of offset and prevents the digital output takes a negative value. If the Digital output can assume a negative value, the Term (1/2) is omitted.

The correction of the offset voltage has been discussed in connection with equation (10). If the offset voltages of the comparators used are so low that they can be neglected, the offset voltage correction may not be necessary. In equation (5), the duration of the output from the second comparator serves as the duration for determining the pulse duration. Instead, the duration of the output from the first comparator can also be used. The input to the second comparator is set to 0 V. The input voltage can be set to any other value as long as it is kept constant despite the temperature fluctuations. In equation (5), the calculation is based on the pulse duration of the high level. The calculation can also be based on the pulse duration of the low level. In the example 5 shown, the counter integrated in the microprocessor is used. Alternatively, a counter circuit is constructed from the gate array shown in FIG. 3 and other devices. The total count obtained during the high level duration and the total count obtained during the low level duration are recorded by a microcomputer for performing the processing according to equation (5) above.

The triangular wave applied to the first comparator need not always be identical to the triangular wave applied to the second comparator. The DC component of the triangular wave applied to the first comparator can be different from the DC component of the triangular wave applied to the second comparator. Δdc is the difference between the two DC components. If (Vof ₂ - Vof ₁ ) according to FIG. 15 is replaced by (Vof ₂ - Vof ₁ + Δdc), the principle described so far can be used in the present form.

Example 6

In the various examples described above, the resolution is not always sufficiently high. In particular then if the number of during the period of high or low level of the pulse width modulated signal counted clock pulses is small, the resolution is low. For example, if the internal frequency of the microprocessor  compared to the carrier frequency of the pulse width modulated Signal cannot be brought to a high value, the desired frequency cannot be achieved. are also in the above examples in the triangular wave generator circuit, the positive or negative equals power supply to each comparator or to earth connected connection interference voltages present, so the Reference voltage of the comparator and the input voltage fluctuate, which increases the pulse width of the pulse width modulated signal changes. As a result, the Digital output of the A / D converter. Especially when used a cheap switching power supply as a power supply the device is susceptible to interference voltages.

Consequently, a Analog / digital converter circuit described, the one can have improved resolution and compared to sturgeon tensions is insensitive.

Referring to Fig. 1, a speed command is voltage-7, is an analog signal when applied to a low pass filter 1. The output of the filter 1 and a triangular wave 8 are applied to a comparator 2 . The output of the comparator 2 is connected to a microprocessor 2 with a clock generator 31 . The microprocessor 3 generates a digital signal corresponding to the speed command voltage 7 , using the internal clock pulses and the clock generator 31 . The microprocessor controls a frequency converter 4 in such a way that the difference between the signal of an encoder 6 , which reports the speed of an electric motor 5 , and the digital signal described above is reduced to zero.

In the following, the mode of operation of the example described above is also described in detail with reference to FIG. 2. The speed command voltage 7 contains interference voltages as well as other higher harmonics, as shown in Fig. 2 (a). This speed command voltage 7 is passed through the low-pass filter 1 to remove the higher harmonics from the output of the low-pass filter. This output is identified by the reference numeral 71 in FIG. 2 (b).

The output 71 of the low-pass filter corresponding to the speed command voltage is compared by the comparator 2 with the triangular wave, which has a constant frequency and a constant amplitude. As shown in FIG. 2 (b), the position changes, in which the output of low pass filter 71, which is the speed command voltage 7 corresponding to the three eckwelle 8 cuts, according to the level of the output 71. The output of the comparator 2 therefore takes the form of a pulse width modulated signal 9 which changes accordingly to the level of the low-pass filter output 71 according to FIG. 2 (c). In other words, the width or duration of the high level of the pulse width modulated signal 9 indicates the amplitude of the speed command voltage 7 .

The clock 31 of the microprocessor 3 has a counter which counts the internal clock pulses of a given frequency as shown in FIG. 2 (d). The clock 31 counts those of the clock pulses that appear within the high level duration of the pulse width modulated signal 9 , as shown in FIG. 2 (e). According to Fig. 2 (f) of the counter is initia lisiert that it loads the total count in a marked as "TIMER" (clock) buffer at the trailing edge of the pulse width modulated signal 9, calls an interrupt and clears the total count. The total count of the counter is a digital signal. The total count obtained at the trailing edge of the pulse width modulated signal 9 is stored in the counter buffer as shown in FIG. 2 (g).

If the request for an interrupt described above is accepted, the processing is carried out in accordance with the sequence shown in FIG. 21. Specifically, (a) the data held in a RAM called Th (n) is copied to another RAM called Th (n-1). (b) The total count of a buffer labeled TIMER is copied to RAM Th (n). (c) The data in the RAM Th (n) and the data in the RAM Th (n-1) are summed and copied to a RAM called REF. After the interrupt has elapsed, the measurement data relating to the duration of the high level of the pulse-width-modulated signal are stored in RAM Th (n). The measurement data regarding the duration of the high level immediately before the pulse width modulated signal are stored in RAM Th (n-1). The sum of the two types of data is stored in RAM REF. This example 6 is characterized in that the value stored in RAM REF ge is used as the output of the A / D converter circuit ver. In contrast to this, in example 1 described above, the value stored in the RAM TIMER is used as the output of the A / D converter circuit.

In this manner, the speed command voltage 7 , which is an analog signal as shown in Fig. 2 (a), is converted into a digital form by performing a series of operations as shown in Figs. 2 (b) to 2 (g) . The value of the counter buffer REF, which is a digital signal, is used as the prescribed speed for the software control provided speed control. In particular, the microprocessor 3 calculates the difference between the speed of the motor 5 demodulated by the encoder 6 and the digitized speed command value and controls the frequency converter 4 such that the difference is reduced to zero.

In this example 6, the sum of the current measured value in the clock generator 31 and the previous measured value is used as a digital output. This improves the resolution of the output of the analog / digital converter circuit. The reason for this is explained in detail below with reference to FIGS. 22 and 23. To simplify the description, it is assumed that the frequency of the internal clock pulses is 1 Hz and the frequency of the triangular wave is 2.5 Hz, as shown in FIG. 22. Since the internal clock pulses are asynchronous to the triangular wave, the actual situation does not always correspond to FIG. 22; cases are selected and presented that are easy to describe. The Fig. 22 (a) shows the internal clock pulses. Figure 22, (b) -. (G) shows pulse-width-modulated signals with Impusverhältnissen of 90%, 80%, 50%, 30%, 10% and 5%. The circles on the waveforms of Fig. 22, (b) - (g), represent samples taken in synchronism with the internal clock pulses. The digit attached to the first stage of each of Figs. (B) - (g) indicates the value that has been counted during the high level period. The number at the second stage indicates the value (corresponding to the value stored in RAM REF according to FIG. 21), which is obtained by summing the previous count value (corresponding to Th (n-1) according to FIG. 21) and the current count value (corresponding to Th (n) according to Fig. 21) is obtained.

The Fig. 22 (b) is now used as an example. If the pulse ratio of the pulse width modulated signal is 90%, the count value of the clock pulses during the duration of the high level is 2 or 3. The sum of the previous count value and the current count value is 5. Since the pulse ratio continuously from (c) to ( g) decreases, the count obtained during the duration of the high level decreases steadily. Finally, the value drops to zero. The total also drops to zero. Therefore, the high level counts can take four values from 3 to 0 depending on the pulse ratio of the pulse width modulated signal. On the other hand, the value obtained by summing the two values derived from two successive high-level periods can take 6 values from 5 to 0. This means that the total value can take on more values than the single count value. This improves the resolution of the digital output by a factor of 1.5.

Fig. 23 shows the case where the internal clock pulse has a frequency of 1 Hz, while the triangular wave has a frequency of 11 Hz. This means that both signals have widely differing frequencies. The count obtained during the duration of the high level of the pulse width modulated signal can assume 12 values from 11 to 0. The total value can take 22 values from 21 to 0. As a result, the resolution is improved by a factor of 22/12 = 1.83 by using the total value. So since the frequency difference between the internal clock pulses and the triangular wave increases, the ratio of the range of the individual values to the range of the sum values approaches 2. That means that by using the sum value the resolution is almost doubled. In practice, the frequency of the internal clock pulses is set to several MHz. The frequency of the triangular wave is set in the range between a few hundred Hz and several kHz.

In the above example 6, the sum of the current measured value in the counter of the clock generator 31 and the previous measured value is used as a digital output, whereby the circuit is operated as a low-pass filter. This improves the immunity to interference voltages for the reason described below. In the field of digital signal processing, the operation of forming the sum of the current value and the previous value of a numerical value present at regular time intervals is known as a primary FIR filter. This is known to work as a low pass filter. FIR is the abbreviation for "finite impulse response". The FIR filter is shown in the block diagram of FIG. 24.

In Fig. 24, Z ^-1 denotes the function for storing the previous value.

In example 6, the operation of summing the two successive values performed in each interrupt, d. H. on each trailing edge of the pulse width modulated Signal. The operation is not always regular Intervals. For this reason, the function is not correct completely with the function of the FIR Filters that match two values at regular intervals were summed up. However, the pulse duration of the changes pulse width modulated signal little, i.e. H. is the Amplitude of the input signal to the analog / digital converter circuit small, so the previous date and the current one Date at substantially regular intervals sum lubricated. It has the same function as the FIR filter executed. In this way, the summing operation Reduce interference voltages with higher frequencies.

In Example 6, the clock pulses are counted for the duration of the high level of the pulse width modulated signal, as shown in Fig. 2 (c), (d), (e). The clock pulses can also be counted during the duration of the low level of the pulse width modulated signal. Since the speed command voltage increases in this case, the count value decreases.

In example 6, the previous and the current date are at the interrupt processing that sums up at each back edge of the pulse width modulated signal takes place. If the output of the analog / digital converter circuit is not on each trailing edge of the pulse width modulated signal is used, the summing operation is not on every way edge of the pulse width modulated signal required. For example, if the output of the analog / digital converter circuit are used after 1 ms, so the  Summing operation within every 1 ms led processing. The one performed every 1 ms Processing can be an interruption. If a strict one Time monitoring is not necessary, the summing opera tion through a routine that runs at regular intervals instead of an interrupt.

Fig. 25 shows the case in which the summing operation is performed every 1 ms. Referring to FIG. 25 (a), the charging is effected of the last date in the RAM Th (n - 1) and the loading of the current date in the RAM Th (n) within the interrupt at each trailing edge of the pulse width modulated signal. According to FIG. 25 (b), processing for determining REF takes place after every 1 ms on each trailing edge of the pulse-width-modulated signal within the interrupt. Control then passes to interrupt processing, under which the entire system is operated. Since the value in the REF, ie the sum value, is not updated on every trailing edge of the pulse-width-modulated signal, the real-time characteristic of the digital output signal is poor. If an output for operating the system is desired every 1 ms by the analog / digital converter circuit, the software shown in FIG. 25 is sufficient.

In the example according to FIG. 25, the previous and the current date are summed after every 1 ms. In obtaining the same effects as in the case of Fig. 21, two kinds of data are preferably summed at substantially the same intervals as those of the square wave. In practice, the circuit is designed so that the ratio of the previous value to the current value is in the range between 1/4 and 4. To accurately measure the duration of the high level of the pulse width modulated signal, the priority assigned to the interrupt processing shown in FIG. 25 (b) should be lower than the priority assigned to the interrupt processing shown in (a). That is, the conditions are such that an interrupt is caused on each trailing edge of the pulse width modulated signal. For this reason, the processing according to (b) should be set so that a multiple interrupt is permitted.

In Example 6 described so far, two successive values obtained during the duration of the high or low level of the pulse-width-modulated signal are summed in the counter. Three consecutive values can also be summed. This example is shown in Figs. 26 and 27. In FIG. 27, the frequencies of internal clock pulses and the triangular wave are 1 Hz and 3/10 Hz. The data obtained from a measurement can take five values from 0 to 4. The sum of the three successive values can take 11 values from 0 to 10. This improves the resolution by a factor of 2.2. As described above, since the frequency difference between the internal clock pulses and the triangular wave increases, the resolution improves and approaches three times the value. At this point in time, the interrupt occurs at each trailing edge of the pulse width modulated signal according to FIG. 26. In this case, the processing for determining REF can also be carried out by a separate processing routine according to FIG. 25.

Furthermore, the data obtained from four or five successive measurements can be summed. However, the interrupt time increases as the number of values to be summed increases. The response time of the analog / digital converter circuit also increases. In practice, the addition of two to four inclusive values makes sense. In Example 6 above, the values obtained during the high or low level of the pulse width modulated signal are summed and used as a digital output. In the same manner as in Examples 3 and 4 above, the values of ((duration of high level) / (total duration)) or ((duration of low level) / (total duration)) of the pulse can be width-modulated to compensate for the frequency changes of the triangular wave Signals or multiples of these periods can be measured. These examples are shown in Fig. 28 (a), (b), (c). Fig. 29 shows the operation of the example of Fig. 28 (a).

First, the example shown in Fig. 28 (a) will be described. The pulse width modulated signal is placed on the first and second clocks integrated in a microprocessor 3 . The first and second clocks are labeled 32 a and 33 b, respectively. The first clock counts the internal clock pulses of the pulse-width-modulated signal that appear during the duration of the high level. The first clock measures the duration of the high level of the pulse width modulated signal. The second clock measures the duration of the low level of the pulse width modulated signal based on the internal clock pulses. The counter 1 of the first clock is initialized so that it counts the internal clock pulses that appear during the high level of the pulse-width-modulated signal, loads the total count value into a buffer labeled TIMER1 on each trailing edge of the pulse-width-modulated signal, a request after a first clock interrupt and clears the total count. The counter 2 of the second clock is initialized so that it counts the internal clock pulses appearing during the low level of the pulse-width-modulated signal, loads the total count into a buffer labeled TIMER2 on each leading edge of the pulse-width-modulated signal, a request for a second clock breaks and clears the total count. The latest value regarding the duration of the high level is therefore always stored in the TIMER1 buffer. The most recent value regarding the duration of the low level is stored in the TIMER2 buffer.

The interrupt processing performed by the second clock on each leading edge of the pulse width modulated signal is explained below with reference to Fig. 30 (b). First, the data from the RAM with the designation Tl (n) are copied into a RAM Tl (1 - n). Then the value of the buffer TIMER2 is copied to Tl (n). The sum of Tl (n) and Tl (n - 1) is loaded into a RAM called TL. The value stored in the RAM TL is therefore the sum of the current count Tl (n) and the previous count Th (n-1) during the low level of the pulse-width-modulated signal. The value in the RAM TL is updated on every leading edge. Fig. 29 (g) represents this processing.

The first clock interrupt on each trailing edge of the pulse width modulated signal is described below. The processing from the top to the third line of FIG. 30 (a) corresponds to the processing of FIG. 30 (b). The same processing is done for the duration of the high level of the pulse width modulated signal. In the fourth column of FIG. 30 (a), the currently determined value TH, ie the sum of the current count value Th (n) with respect to the duration of the high level and the previous count value Th (n-1), as well as the im second clock interrupt he received TL used and the value of ((duration of high level) × (constant K) / (total duration)) calculated. The calculated value is loaded into the RAM with the designation REF. Practical examples of the constant K are 256 (= 2 ⁸ ) and 65536 (= 2 ¹⁶ ), since these values make processing easier for the microprocessor. In this example, who uses the total values derived from the duration of the high level and from the total duration. The reduction of the interference voltages can be achieved for the total duration as well as for the duration of the high level. The lines for determining TH, TL and REF can be processed in a separate routine according to FIG. 25 instead of the first and second clock generator interrupt.

With regard to the total duration, it is not always necessary to use the values obtained by summing two successive values. The total values are only used for the duration of the high level. This also improves resolution and reduces interference voltages. Processing takes place especially when determining REF according to FIG. 30 (a)

REF <- (TH × K) (((TH (n) + TL (n)) × 2).

Since the denominator contains neither Th (n - 1) nor Tl (n - 1), be each data element is pending in terms of total duration a single value.

In the following, the example of FIG. 28 (b) will be described with reference also to FIGS . 31 and 32. The first clock measures the duration of the high level of the pulse width modulated signal. The second clock measures the total duration of the pulse width modulated signal. For this reason, counter 1 of the first clock is initialized to perform the operation shown in Fig. 31 (d). The counter 2 of the second clock is initialized to perform the operation shown in Fig. 31 (e). In Fig. 31 (e), the measurement of the total duration is completed on each leading edge of the pulse width modulated signal. The measurement can also be completed on each trailing edge. The first clock loads the total count obtained during the high level into a buffer called TIMER on each trailing edge of the pulse width modulated signal. The second clock loads the total count obtained during the total duration into a buffer called TIMER2 on each leading edge of the pulse width modulated signal.

Fig. 32 (b) illustrates the interrupt processing by the second clock. The request for an interrupt shown in Fig. 2 (b) is made on each leading edge of the pulse width modulated signal. The value of Tall (n) is copied to Tall (n - 1). The value of the TIMER2 buffer is copied to Tall (n). TALL is the sum of the values of Tall (n) and Tall (n - 1). The sum of the current total count value and the previous total count value of the clock pulses appearing during the total duration is stored in TALL.

Fig. 32 (a) shows the interrupt processing by the first clock. The request for an interrupt shown in Fig. 32 (a) occurs on each trailing edge of the pulse width modulated signal. The value of Th (n) is copied to Th (n - 1). The value of the TIMER buffer is copied to Th (n). Let TH be the sum of the values of Th (n) and Th (n - 1). Through this processing, the sum of the current total count and the previous total count of the clock pulses appearing during the duration of the high level is loaded into TH. In the fourth column of Fig. 32 (a), the value of TH is multiplied by a constant K. In general, this constant K is set to 256 or 65536, as is also the case in the example according to FIG. 28 (a). The product is divided by the value of TALL. The quotient is used in REF to generate the output of the analog / digital converter circuit. The lines in FIG. 32 for determining TH, TALL and REF can be carried out by a separate processing routine according to FIG. 25 instead of the interrupt processing of the first and second clock.

28 (b), 30-32, the current total count and the previous total count for the duration of the high level, as well as for the total duration of the pulse width modulated signal are summed in the previously described embodiments according to FIGS.. This improves the resolution and reduces interference voltages.

The example shown in FIG. 28 (c) is described below with reference also to FIGS. 33 and 34. In this example, a microprocessor 3 has only a first clock generator 31 . This first clock measures the duration of the high level and the duration of the low level of the pulse width modulated signal. The first clock is initialized so that it loads the total count in the buffer labeled TIMER1 on the leading and trailing edges of the pulse width modulated signal, allows the first clock to issue an interrupt request and clear the total count. FIGS. 33 and 34 show the interrupt of the first clock. As shown in this figure, the level of the pulse width modulated signal is evaluated immediately after the beginning of the interrupt Ve 33265 00070 552 001000280000000200012000285913315400040 0002004241702 00004 33146 processing. If the level is high, this condition corresponds to A in Fig. 33 (a). It can be seen that the interrupt processing is now initialized in response to the leading edge of the pulse width modulated signal. The measured value of the duration of the low level is stored in the buffer designated as Timer1. At this time, the value from Tl (n) is copied to Tl (n - 1). The value of the Timer1 buffer is copied to Tl (n). The value of Tl (n) and the value of Tl (n - 1) are summed and loaded into TL. The sum of the previous date regarding the duration of the low level and the current date regarding the duration of the low level is stored in TL. This value of TL is constantly updated.

If the level of the pulse width modulated signal is low, this condition B corresponds to Fig. 33 (a). It can be seen that the interrupt processing is now started on the trailing edge of the pulse width modulated signal. The measured value of the duration of the high level is stored in the buffer designated as Timer1. At this point the value is copied from Th (n - 1) to Th (n). The value of the buffer TIMER1 is copied to Th (n). The sum of the previous date and the current date regarding the duration of the high level is stored in TH. The value of TH is updated continuously. The value of TH and the value of TL are summed and loaded into TALL. That is, the value of TALL is the sum of the two values for the total duration. The calculation is then carried out ((TH × K) / TALL). REF is generated as the output of the A / D converter circuit. As explained earlier, K is set to 256 or 65536. The operations for determining TH, TL, TALL and REF can be carried out in a separate routine according to FIG. 25.

Also in this example the sum is from the previous date and the current date for the duration of the high level and the total duration of the pulse width modulated signal ver turns. As a result, the resolution improves, and the Interference voltages are reduced.

In the following the invention is based on the above benen Example 5 described. If in particular the DC component of the triangular wave with the tempera tur changes or if the offset voltages of the Kompara gates change with temperature, data regarding the pulse duration of the square wave, which is obtained by comparing the Triangular wave can be obtained with a constant voltage of data regarding the pulse width of the pulse width modulated signal is subtracted to prevent the digital output changes. In this case there is also  the following options according to the different so far described examples.

• I) Are the dates for the total duration of first clock or from the second clock.
• II) Which processing routine is used for the determination used by TH, TL, TALL and REF.
• III) If the measured value of the duration of the high level or the measured value of the duration of the low level as Digital signal used.
• IV) Does each data element exist with regard to the Total duration from a single value or from the Sum of two values.
• V) The pulse duration of the square wave is called Reference used. If the pulse duration of the Period with high level or the pulse duration of the Low level period as the reference used.

An example in which the fol conditions.

• a) The total duration is obtained from the second clock. Furthermore, each data element is summed up by get two values.
• b) TH1, TH2, TL2, TALL and REF are used in other routines calculated as the first clock interrupt and the second clock interrupt.
• c) The duration of the high level of the pulse width modulated Signal is measured as a digital signal.
• d) Each data item in terms of total duration obtained by summing two values.
• e) The pulse duration of the period with high level of law Eckwelle is used as a reference.

The index i of Th ₁ and TL ₁ indicates whether the date is obtained from the first comparator or from the second comparator. The index i in Thi () and Tli () has the same meaning. Specific examples with the above conditions are described with reference to Figs. 35-39. Referring provided on the Fig. 35, a first comparator 21 and second comparator 22. The first comparator compares a speed-command voltage 7, which is passed through a low-pass filter 1 , with a triangular wave 8 , in order to generate a pulse-width-modulated signal. The positive connection of the other second comparator is grounded. The triangular wave 8 is connected to the negative terminal of the second comparator. The second comparator thus compares the triangular wave 8 with 0 V, ie the ground potential, whereby a square wave with a pulse ratio of 50% is generated. A microprocessor 3 contains a first clock generator 31 a and a second clock generator 31 b. The first clock measures the duration of the high level of the first comparator. The second clock measures the duration of the low level of the second comparator. The first clock is configured to load the total count into a buffer labeled TIMER1 on each trailing edge of the pulse width modulated signal, issue a request for an interrupt, and clear counter 1 of the first clock. The second clock is configured to load the total count into a buffer labeled TIMER2 on each leading and trailing edge of the square wave, issue a request for an interrupt, and clear counter 2 of the second clock.

The above interrupt processing is described below with reference to FIG. 37. In interrupt processing of the first clock as shown in Fig. 37 (a), the value is copied from Th ₁ (n) to Th ₁ (n-1). The value of TIMER1 is copied to Th ₁ (n). This completes the processing. The current date regarding the duration of the high level of the pulse width modulated signal is stored in Thl (n). The previous date regarding the duration of the high level of the pulse width modulated signal is stored in Th ₁ (n-1). The interrupt of the second clock is caused by the decision to evaluate the level of the square wave as shown in Fig. 37 (b). The control path then branches into two paths. If the level of the square wave is high, it follows that an interrupt occurred on the leading edge of the square wave as indicated by A in Fig. 36 (b). Accordingly, the count value obtained from the duration of the low level of the square wave is stored in TIMER2. This copies the value from Tl ₂ (n) to Tl ₂ (n - 1). The value of TIMER2 is copied to Tl ₂ (n). The current date and the previous date regarding the duration of the low level of the square wave are stored in Tl ₂ (n) and Tl ₂ (n - 1). The same principle applies when the square wave level is high. The current date and the previous date regarding the duration of the high level of the square wave are stored in Tl ₂ (n) and Tl ₂ (n - 1).

Fig. 37 (c) shows the interrupt processing for system operation using the output of the A / D converter circuit. The following values are determined in this interrupt processing: the value TH ₁ , which results from summing two values with regard to the duration of the high level of the pulse-width-modulated signal, the value TH ₂ , which results from summing two values with regard to the duration of the high level of the Square wave results, the value TL ₂ , which results from summing two values with regard to the low level of the pulse width modulated signal, and the value TALL, which results from summing two periods of the square wave. The digital output REF, ie ((K × TH ₁ ) / (TALL) - (K × TH ₂ ) / (TALL) K / 2 - (offset correction amount)), is calculated from the above values. This formula corresponds to the equation (10) used in the description of Example 5.

In this way you get each in this example Data element by summing two consecutive ge measured values for the entire duration of the high level, the Duration of the high level of the square wave and the duration of the low level of the square wave. Consequently, the on solution improved, the interference voltages are reduced. A Change in digital output is prevented if the DC component of the triangular wave and the Off change the set voltages of the comparators with the temperature, by adding the totals of the periods of high and low Square wave level corresponding to the pulse duration of the Square wave can be subtracted from the sum values that one by summing two successive measured values according to the pulse width of the pulse width modulated Receives signal, with each of the previous sum values by Sum of two successive values is obtained.

As shown in Fig. 38, the input signals to the two input terminals of the second comparator may have an inverse relationship to each other as that in the example of FIG. 35. In particular, the triangular wave 8 is applied to the positive input terminal of the second comparator. The ground potential or 0 V is connected to the negative circuit. The operation of this example is shown in FIG. 39. This example is similar to the example of FIG. 35, except that the polarity of the square wave is reversed. In this example, two successive values obtained during the duration of the high level of the pulse width modulated signal are summed to a value TH1. Two successive values obtained during the period of the high level of the square wave are summed to a value TH2. Two successive values obtained during the low level of the pulse width modulated signal are summed to a value TL2. Two successive periods of the square wave are summed up to a value TALL. The digital output REF, ie ((K × TH ₁ ) / (TALL) - (K × TL ₂ ) / (TALL) K / 2 - (offset correction amount)), is calculated from the above values. This example differs from the example in FIG. 35 in that the pulse duration of the square wave is calculated from the sum values TL ₂ with regard to the duration of the low level of the pulse-width-modulated signal, and that the calculated pulse duration is subtracted from the pulse duration of the pulse-width-modulated signal becomes.

Example 7

The engine control unit with the analog / Digital converter circuit does not require an analog / digital Converter IC and is inexpensive. Furthermore, the Microprocessor input / output ports effective be used.

However, the above-mentioned engine control unit that actually uses the A / D converter circuit has room for improvement. The reason for this will be explained with reference to FIGS. 44 and 45. As previously described, a speed command voltage, which is an analog signal, is compared to a triangular wave to produce a pulse width modulated signal. The clock pulses appearing during the high level of this signal are counted to convert the analog signal to digital form. The desired operation is only permissible if the level of the speed command voltage is lower than the amplitude of the triangular wave. When the level of the speed command voltage exceeds the amplitude of the triangular wave, the pulse width modulated signal is coupled to the high or low level depending on the level of the speed command voltage, as shown on the right side of Fig. 45 (b). The counter of the clock generator continues to count the clock pulses. The result is that the digital signal takes an abnormal value. Since the microprocessor 3 controls the motor 5 via the frequency converter 4 according to the digital signal, the microprocessor is no longer able to control the motor 5 correctly if the digital signal assumes an abnormal value; the motor 5 may run uncontrollably.

As a result, an improvement over the above Proposed engine control unit proposed. If in particular the level of the speed command voltage the amplitude of the Triangular wave exceeds and the pulse width modulated Signal is coupled to the high or low level the engine turned off to operate uncontrollably or any other abnormal engine behavior to prevent.

This improvement is described below as Example 7 with reference to FIGS. 40-43. This example is an engine control unit with an analog / digital converter circuit. Example 7 shown has numerous components that are identical to those of the examples described above. In the different figures, the same components are identified by the same reference signs.

Referring to FIG. 40, a speed command is voltage-7, is an analog signal when applied to a low pass filter. 1 The output of the filter 1 and a triangular wave 8 are applied to a comparator 2 . The comparator 2 compares the speed command voltage 7 with the triangular wave 8 in order to generate a pulse-width modulated signal 9 as mentioned above. The output of the comparator 2 is placed on a first clock 32 integrated in a microprocessor 3 . The first clock generator 32 causes a counter 31 contained in the microprocessor 3 to count the clock pulses appearing in the pulse-width modulated signal during the duration of the high or low level. The analog signal is thereby converted into a digital form. The microprocessor 3 forms a control circuit for controlling the speed of an electric motor 5 . The microprocessor receives the digital signal received by the first clock generator 32 as well as the signal from an encoder 6 which reports the speed of the motor 5 . The microprocessor controls a frequency converter 4 in such a way that the difference between the digital signal corresponding to the speed command voltage 7 and the signal reporting the speed is reduced to zero.

The example 7 shown in FIG. 40 differs from example 1 according to FIG. 1 in that a second clock generator 33 is provided which functions as an alarm clock generator. The clock 33 recognizes that the speed command voltage 7 has exceeded the amplitude of the triangular wave 8 . The alarm clock generator can use a clock generator integrated in the microprocessor 3 . The clock generator 33 is preset on each leading and trailing edge of the pulse width modulated signal 9 and counts the clock pulses backwards. Theoretically, this default setting is set to a value that is approximately equal to the amplitude of the triangular wave 8 . In practice, the preset value is 0.9 to 1.5 times the amplitude of the triangular wave 8 . In the illustrated example 7, the default setting of the alarm clock 33 is set equal to the amplitude of the triangular wave 8 . After presetting the clock generator 33 , this generates an output signal which signals when the total count value reaches a given value (0 in this example, 7). The output signal is applied to the microprocessor 3 .

The operation of Example 7 is profiled in the following detail with reference to Fig. 41 - discussed 43rd Fig. 41 shows the operation when the level of the pulse width modulated signal 9 is high, the command signal exceeds the amplitude of the triangular wave, and the pulse width modulated signal is coupled to the high level. Whenever the level of the pulse width modulated signal changes after the high or low level, the alarm clock 33 is preset and counts down the clock pulses as shown on the left side of FIG. 41 (b). As a result, while the pulse width modulated signal 9 is switched between the high and low levels, the timer 33 is preset when the total count reaches a value corresponding to the pulse width of the pulse width modulated signal 9 . However, if the level of the pulse width modulated signal 9 is high when the speed command signal 7 exceeds the amplitude of the triangular wave 8 and the pulse width modulated signal 9 is coupled to the high level, the alarm clock 33 counts the clock pulses further downward, as on the right side of FIG. 41 (b). Finally, the total count value reaches 0, whereupon an alarm signal is generated which shows the detection and is shown in FIG. 41 (c). In response to this signal, the microprocessor 3 brings the motor 5 to a standstill.

Fig. 42 shows the operation when the pulse modulated signal 9 is at a low level, the speed command signal 7 exceeds the amplitude of the triangular wave and the pulse width modulated signal is coupled to the low level. When signal 9 is coupled to the low level, the alarm clock continues to count down the clock pulses as shown on the right hand side of Fig. 42 (b). Finally, the total count reaches 0. At this time, the alarm signal shown in Fig. 42 (c) is generated, which reports the detection.

In response to this signal, the microprocessor 3 brings the motor 5 to a standstill.

In this way, in the above example, the alarm clock generator 33 generates an output signal which reports the detection when the pulse width modulated signal 9 is coupled to the high or low level. The microprocessor 3 can therefore accept the digitized value and store it until the clock generator 33 generates its output signal. The microprocessor can control the motor via the frequency converter 4 in accordance with the digital signal. If, on the other hand, the clock generator 33 generates its output signal, the microprocessor immediately switches off the frequency converter 4 , de-energizes the motor 5 , brakes the motor 5 backwards and brings all other functions to a standstill. If in the motor control circuit with the A / D converter circuit described in Examples 1-6, the pulse width modulated signal is at a low level, the speed command signal exceeds the amplitude of the triangular wave, so that the digital value assumes an abnormal value. In this case, the abnormal value is taken over unchanged. This puts the motor 5 in a position to work uncontrollably. In Example 7, if the digital value becomes abnormal, the timer 33 detects this abnormality and generates its output. This output signal affects the standstill of the motor 5th Malfunction of the motor control circuit can thus be prevented.

The alarm clock 33 acting as a detector device can also be preset when the A / D converter circuit is started. When the system starts, the speed command signal 7 may have already exceeded the amplitude of the triangular wave 8 . If the system is started in this case, it can work incorrectly and uncontrollably. For this reason, the clock 34 will be preset before the start of the entire system. Fig. 43 shows an example. When the entire system is started, e.g. For example, when the power supply is turned on or the reset button is operated after the speed command signal 7 8 has already exceeded the amplitude of the triangular wave, it seems neither a front edge nor a rear edge of the pulse width modulated signal. It is therefore impossible for the alarm clock 33 to be preset in response to the leading or trailing edge. Accordingly, when the microprocessor 3 is started, the alarm clock 33 is preset once regardless of the leading or trailing edge of the pulse width modulated signal, as shown in Fig. 43 (b), (c), (d).

Thus, if the pulse width modulated signal 9 is already coupled to the high or low level when the A / D converter circuit is started, then the alarm clock 33 can generate its output signal when the total count reaches a given value after a given period of time since the clock 33 is preset. As a reaction to the output signal of the clock generator 33, the microprocessor blocks the operation of the motor 5 . It is therefore unlikely that the engine 5 will run incorrectly and in an uncontrollable manner.

In example 7 shown, a microprocessor is considered one Control circuit used. The first clock and the Alarm clock or the second clock are in the micro processor integrated. A control circuit can also be a device other than a microprocessor can be used. Independent clocks not integrated in the microprocessor can also act as the first clock or alarm clock be used. In the example above, a micropro is used processor as a control device. The one as an A / D converter clock generator or acting as a detector device Clock generators are integrated in the microprocessor. Every scarf section can be a combination of different  Represent circuits. That is, each circuit section can be constructed in the form of hardware. The same radio tion can be carried out through software processing will.

The advantages of the present invention are as follows explained.

• 1) According to the present invention, an analog / Digital converter circuit only from a comparator and its peripheral components without using a Analog / digital converter IC can be manufactured. A Analog / digital converter circuit can thus be inexpensive Tobe offered.
• 2) According to the present invention, there is an analog / Digital converter circuit consisting of a comparator and one Counter. The comparator compares a command signal which is an analog signal with a Triangular wave with given frequency and given Amplitude to convert the analog signal into a pulse width convert modulated signal. The counter measures that Duration of the high level of the pulse width modulated Signal to convert it into a digital signal. The Analog / digital converter circuit can therefore only from the comparator and its peripheral components without Built using an analog / digital converter IC will. This allows the analog / digital converter circuit can be manufactured at low cost.
• Furthermore, the digital data from the value from ((duration of high level of pulse width modulated signal) / (total duration)) or a Multiple of this value determined. That changed digital starting date therefore does not depend on the Frequency of the triangular wave, which is used to obtain the  pulse width modulated signal is used. This ensures a stable and accurate conversion into a enables digital form.
• 3) According to the present invention, an analog / Digital converter circuit one comparator and one Counter. The comparator also compares an analog signal a triangular wave to convert the analog signal into a pulse to convert width-modulated signal. The counter measures the duration of the high or low level of the pulse wide modulated signal to convert it into a digital Signal to convert. The data regarding the impulse duration of a square wave will depend on the data visibly the pulse duration of the pulse width modulated Signal subtracted, the square wave by Comparison of the triangular wave with a given voltage is produced. In this way the analog signal is in changed a digital form. So if that DC component of the triangular wave with the Temperature changes, or if the offset voltage changes of the comparator changes with temperature and thereby the pulse duration of the pulse width modulated signal and the pulse duration of the square wave is changed the change in data regarding the pulse duration of the pulse-width-modulated signal, which by the changes tion of the DC component of the triangular wave is caused by temperature fluctuations, as well as the fluctuations in the offset voltage of the Comparator due to temperature fluctuations gentle change of data switched off. Hence can realizes an accurate analog / digital converter circuit light that is not caused by temperature fluctuations is affected.
• 4) According to the present invention, an analog / Digital converter circuit: an analog / digital converter  device for comparing an analog speed command signal with a triangular wave of given Frequency and given amplitude and to convert the Analog signal into a digital signal; a detector device that queries whether the speed command signal lies within the amplitude of the triangular wave; a Control device that controls the output of the analog / digital Converter device, the output of the detector device and receives the output of an encoder that does the rotation number of an electric motor demodulated; one of the Control device in the manner controlled frequency converter that the difference between that from the rotation number command signal specified speed and from Frequency converter controlled actual speed the engine is reduced to zero. If the detector is on direction detects that the speed command signal the Leaves the amplitude of the triangular wave Control device to stop the engine. So if the speed command signal the amplitude of the three Eckwelle leaves and the analog / digital converter setup malfunctions, can be an uncontrolled preventable operation of the engine.
• 5) According to the present invention, an analog / Digital converter circuit which is based on an analog / digital Converter IC dispenses with the following: a comparator that an analog signal with a triangular wave of given Frequency and given amplitude compares to that Analog signal into a pulse width modulated signal walk; and a counter that measures the duration of the high or low level of the pulse width modulated signal measures to convert it to a digital signal. The from Get counters from the pulse width modulated signal current total count value and the previously received Total counts are totaled. The resulting value serves as the digital output of the analog / digital converter  circuit. This allows the resolution of the output of the A / D converter circuit can be improved. The resolution the output of the A / D converter circuit is further ver improves by the current measurement of the pulse width modulated signal and several previous measurements of the pulse width modulated signal are summed and the sum value is used as the digital output. The signal from the pulse width modulated by the counter current total count received and at least one Total counts previously received are summed. The The resulting total value serves as a digital output. On in this way the counter acts as a low pass filter. A deterioration in the accuracy of the digital Output due to interference voltages can be prevented will.
• The values of (duration of the high level of the pulse width modulated signal) / (total duration of the pulse width modulated signal), (duration of the low Pulse Width Modulated Signal Level) / (Total duration of the pulse width modulated signal) or that Ratio of the multiples of the above periods are measured and converted into a digital signal. The resulting digital output data hang does not depend on the frequency of the triangular wave leading to the Generation of the pulse width modulated signal is pulled. It is a stable and accurate analog / Digital conversion possible. The current reading of the pulse width modulated signal and at least one previous measured value of the pulse width modulated signal are summed up. Using the resulting The data is of value with regard to the pulse duration a square wave from the data regarding the Pulse duration of the pulse width modulated signal sub trahed, the square wave by comparing one Get triangular wave with a given voltage  becomes. In this way he becomes a digital output testifies. If the DC component of the Triangular wave changes with temperature, or when the offset voltage of the comparator with the temperature changes and thereby the pulse width of the pulse width modulated signal and the pulse duration of the rectangle wave changes, these changes are switched off. As a result, the output of the analog / digital Converter circuit not due to temperature fluctuations impaired and is therefore accurate.
• 6) According to the present invention, an analog / Digital converter circuit the following: a comparator, which is an analog command signal with a triangular wave ver given frequency and amplitude equalizes to the analog signal in a pulse width convert modulated signal; and a counter that those during the duration of the high or low level of the pulse width modulated signal appearing Clock pulses count to convert it into a digital signal walk. The converter circuit is with an alarm clock equipped in response to the front and trailing edges of the pulse width modulated signal is preset. If the total count of the clock sensor reaches a certain value, the Clock an alarm signal. If the command signal is the Amplitude of the triangular wave exceeds and that pulse width modulated signal with the high or coupled low level, the alarm generates clock the alarm signal to report that the won delte digital signal takes an abnormal value. The converted digital signal can therefore ver ver be used as long as the alarm signal is not generated becomes.  
• If the alarm clock is designed to work with the start of the analog / digital converter circuit the alarm signal can be generated, if the pulse width modulated signal is already at Start of operation with the high or low level was coupled. A malfunction of the A / D Converter circuit and an uncontrollable operation of the Entire system can be prevented.

Claims (25)

1. Analog / digital converter circuit with:
a comparator for comparing an analog input signal with a triangular wave signal with a given frequency and a given amplitude to convert the analog signal into a pulse width modulated output signal; and
a counter responsive to the pulse width modulated output signal for measuring the clock pulses appearing during a period of the high or low level of the pulse width modulated output signal in order to convert it into a digital output signal which corresponds to the analog input signal,
wherein a digital output signal output by the analog circuit is defined by adding up a current measured value detected by the counter and at least one previous measured value of the pulse width modulated signal. 2. Analog / digital converter circuit according to claim 1, at which is the digital output signal by a sum the current measured value and a large number of previous measurements values of the pulse width modulated signal defined is. 3. Analog / digital converter circuit according to claim 1, at which synchronizes the digital output signal with the pulse width modulated signal is generated. 4. Analog / digital converter circuit according to claim 1, of the digital output signal within a front given time period is generated. 5. Analog / digital converter circuit with:
a comparator for comparing an analog input signal with a triangular wave signal with a given frequency and a given amplitude to convert the analog signal into a pulse width modulated output signal; and
a device for generating a digital output signal, which corresponds to at least one of the following variables: a duration or period of the high level of the pulse-width-modulated signal, a total duration of the pulse-width-modulated signal and a duration or period by multiplying the duration of the high level and the total duration is defined with a predetermined value,
the duration of the high level of the pulse width modulated signal speaks ent the digital output signal. 6. Analog / digital converter circuit with:
a comparator for comparing an analog input signal with a triangular wave signal with a given frequency and a given amplitude to convert the analog signal into a pulse width modulated output signal; and
a device for generating a digital output signal which corresponds to at least one of the following variables: a duration or period of the low level of the pulse-width-modulated signal, a total duration of the pulse-width-modulated signal and a duration or period by multiplying the duration of the high level and the total duration is defined with a predetermined value,
the duration of the low level of the pulse-width modulated signal speaks ent the digital output signal. 7. Analog / digital converter circuit according to claim 1, at the current measured value generated by the counter and min at least a previous measured value generated by the counter pulse width modulated signals from data accordingly a pulse duration or a pulse duty factor width-modulated signal or data accordingly a pulse duration or a duty cycle by comparing the triangular wave with a given one The resulting square wave is subtracted where at least one counter of the pulse duration or Duty cycle of the pulse width modulated signal through the digital output signal of the analog / digital Converter is obtained. 8. Analog / digital converter circuit with:
a comparator for comparing an analog input signal with a triangular wave signal with a given frequency and a given amplitude to convert the analog signal into a pulse width modulated output signal; and
a counter responsive to the pulse width modulated signal for measuring the pulse appearing during a period of the high or low level of the pulse width modulated output signal to convert it into a digital output signal corresponding to the analog input signal;
and an alarm clock preset on a leading edge and a trailing edge of the pulse width modulated signal, the alarm clock generating an alarm signal when the total count of the clock reaches a predetermined value. 9. Analog / digital converter circuit according to claim 8, at which the alarm clock is preset when the Analog / digital converter circuit is started.   10. Device for controlling a speed of an electric motor with:
an analog / digital converter device for converting an analog speed command signal into a digital output signal by comparing the analog speed command signal with a triangular wave with a predetermined frequency and amplitude;
a detector device for determining whether or not the speed command signal is within the amplitude of the triangular wave;
a control device for receiving the digital output signal from the detector device, an output signal of the detector device and an output of a speed of the motor detecting or demodulating encoder; and
a inverter or frequency converter controlled by the control device in such a way that a difference between a speed reported by the speed command signal and an actual speed of the motor is brought to zero,
wherein the motor is controlled by the frequency converter and the control device comes into operation when the predetermined amplitude is exceeded by the speed command signal in order to bring the motor to a standstill. 11.Analog / digital converter circuit with:
a comparator for comparing an analog input signal with a triangular wave signal with a given frequency and a given amplitude to convert the analog signal into a pulse width modulated output signal; and
a counter responsive to the pulse width modulated signal for measuring the pulse appearing during a period of the high or low level of the pulse width modulated output signal to convert it into a digital output signal corresponding to the analog input signal. 12. Analog / digital converter circuit according to claim 11, in which the digital output signal based on one of the following values is determined. ((Duration of high Level of the pulse width modulated signal) / (Total duration of the pulse width modulated signal)), a multiple of this ratio, ((duration of the low level of the pulse width modulated signal) / (Total duration of the pulse width modulated signal)) or a multiple of this ratio. 13. Analog / digital converter circuit according to claim 12, in which is the duration of the high or low Level of the pulse width modulated signal by the Counter is measured, and assumed at the that the total duration of the pulse width modulated Signal the sum of the measured duration of the high Level and the measured duration of the low level is. 14. Analog / digital converter circuit according to claim 11, in which converts the analog signal into digital data, adding data regarding the pulse duration of a right corner wave of data regarding the pulse duration of the pulse width modulated signal are subtracted, where the square wave by a comparator Comparison of the triangular wave with a given voltage is obtained. 15. Analog / digital converter circuit according to claim 14, in which are those obtained with a zero analog input digital data used as an offset correction value will.   16. Analog / digital converter circuit according to claim 11, a device for storing previously measured Values of the pulse width modulated signal are provided in which the current measured value supplied by the meter and at least one previous measured value are summed, and where the resulting value is a digital output is viewed by the converter circuit. 17. Analog / digital converter circuit according to claim 16, which is the sum of the current measured value and several previously measured values of the pulse width modulated Signal is considered as a digital output signal. 18. Analog / digital converter circuit according to claim 16, which synchronizes the digital output signal with the pulse width modulated signal is generated. 19. Analog / digital converter circuit according to claim 16, of the digital output signal in regular time intervals is generated. 20. Analog / digital converter circuit in which the value of (Duration of the high level of the pulse width modulated Signals) / (total duration of the pulse width modulated Signals) or a multiple of this ratio as a digital output signal is generated and at digital output defined in claim 6 as a date regarding the duration of the high level is used. 21. Analog / digital converter circuit of claim 16 defined type, where the value of (duration of low level of the pulse width modulated signal) / (Total duration of the pulse width modulated signal) or a multiple of this ratio as one digital output signal is generated and at that in Claim 6 defined digital output signal as a date  used for the duration of the low level becomes. 22. Analog-digital converter circuit of the defi in claim 16 nier type, in which the digital output signal of a counter indicating the current measured value, and at least one previous measurement of the pulse width modulated signal is generated by data with regard to the pulse duration of a square wave of Data regarding the pulse width of the pulse width modulated signal are subtracted, the Square wave by comparing the triangular wave with a predetermined voltage is obtained, and wherein at least the counter of the pulse duration of the pulse wide modulated signal the digital output signal used according to claim 6. 23. Analog / digital converter circuit according to claim 11, the also one on a front flank and a rear edge of the pulse width modulated signal posed alarm clock includes an alarm signal generated when the total count of the clock one predetermined value reached. 24. Analog / digital converter circuit according to claim 23, which the alarm clock is also preset when the analog to digital converter circuit started becomes. 25. Device for controlling a speed of an electric motor with:
an analog / digital converter device for converting an analog speed command signal into a digital output signal by comparing the analog speed command signal with a triangular wave with a predetermined frequency and amplitude;
a detector device for determining whether the speed command signal is within the amplitude of the triangular wave;
a control device for receiving the digital output signal output by the detector device, an output of the detector device and the output of a motor demodulating the speed of the motor;
a frequency converter controlled by the control device in such a way that a difference between a speed reported by the speed command signal and an actual speed of the motor is brought to zero; and
in which the control device brings the motor to a standstill when the detector device detects that the speed indicated by the speed command signal exceeds the amplitude of the triangular wave.