DE4234194A1 - SYSTEM AND METHOD FOR MEMORY SEGMENTATION FOR A MICROPROCESSOR - Google Patents

Description

The invention relates generally to a storage man management system for computers and in particular on a storage Segmentation system for microprocessors, which has an increased Da access speed and efficiency.

Memory management is a hardware mechanism that Be drive systems causes simplified program execution conditions to create conditions. Several can run simultaneously Independent address spaces are assigned to the programs to avoid mutual interference. The storage ma Management typically consists of segmentation and pages change (paging). Segmentation is used by every pro several independent, protected address spaces ("segments") to give. Paging is used to support an environment when large address spaces using a small direct access memory - ("HAM -") space and a disk memory simulated will. System designers can use any one or both of the Mecha Select mechanisms. If several programs are running at the same time, can any mechanism to protect programs from interference used by other programs.

The segmentation enables the use of a complete dig unstructured and simple memory, similar to the Spei Model of a simple 8-bit processor, or one high structured memory with address translation and protection. Each Segment is an independent, protected address space. The To access to segments is controlled by data which their Size, the access privilege level required for access, the types of memory references that can be made (Command fetch, batch input or output, read opera tion, write operation, etc.) and indicate whether they are in the Memory are available.

Referring now to Fig. 1 (a), a pictorial representation of the memory address translation mechanism is shown. The segmentation mechanism 105 converts the segmented (logical) address 100 into an address called linear address 110 for a continuous, non-segmented address space. When a page break is enabled, the page break mechanism 115 translates the linear address 110 into a physical address 120 . If page change 115 is not enabled, linear address 110 is used as physical address 120 . The physical address 120 finally appears on the address bus coming out of the processor.

An example of a memory management system is implemented in the i486 microprocessor from INTEL CORPORATION, the applicant. In the i486 microprocessors, a logical address consists of the 16-bit segment selector for its segment and a 32-bit offset into the segment. In the embodiment of FIG. 1 (a), the logical address 100 is translated into the linear address 110 by adding the offset 101 to the base address 103 of the segment. The base address 103 is derived from the segment descriptor 104 . This is a data structure in memory that provides the size and location of a segment as well as access control information. For example, the segment descriptor in an i486 microprocessor is obtained from one of two tables, the global descriptor table (GDT) or the local descriptor table (LDT). There is a GDT for all programs in the system and an LDT for each separate program or running task. If the operating system allows it, different programs can access the same LDT together. The system can also be built without LDT's; all programs then use the GDT. For more information regarding the i486 microprocessors, see the Programmer Reference Guide for the i486 microprocessor.

The translated address is linear address 110 . When the paging mechanism is not needed, the linear address 110 is the physical address 120 . If paging is used, a second level of address translation is needed to generate the physical address 120 .

Again reference is made to Fig. 1 (a). The segment selector 102 there points to the segment descriptor 104 , which defines a segment. A program in the i486 microprocessor can call up more segments than the segment selectors currently occupy segment registers. If this is the case, the program uses MOVE commands to change the content of the segment register when it needs to access a new segment. As shown in Fig. 1 (b), the segment selector 132 identifies a segment descriptor by specifying the descriptor table 133 and the descriptor index 134 within that table.

Referring now to Figure 2, a descriptor format in the i486 microprocessor is shown. Since the descriptor format must ensure backward compatibility for previous process architectures, the descriptor format is scrambled (or reformatted) when stored in memory. To simplify the internal processor information, a scrambled, unprocessed descriptor must be transformed into an unscrambled descriptor. The transformation of a scrambled segment descriptor 300 into an unscrambled descriptor 310 is shown for the i486 processor in FIG. 3.

The invention provides improved memory management system for memory operations in microprocessors supply. As will be described, a segment descriptor is used Cache for holding previously fetched, unscrambled and tested Descriptors such that in subsequent segment registers traces the segment descriptor from cache to source and directly into the segment descriptor register file in one cycle can be loaded. This can usually be done with the Loading of segment related work and operations be circumvented. As is clear to the expert, this enables Storage system according to the present invention that segment end descriptors can be loaded directly into the segment register if the segment descriptors after the associative search by the  Segment selector are stored in the segment descriptor cache. If the descriptor doesn't exist in the descriptor cache, the selector is used to get the descriptor from a descript Tortabelle in memory, for descrambling and testing the De scriptors and to update the descriptor cache with the newly fetched, unscrambled and tested descriptor, see above that the latter may subsequently be available.

The invention has for its object an improved Memory segmentation system to increase data access to provide speed and efficiency. The Spei The chersystem is said to use a segment descriptor cache be provided that previously fetched and not scrambled Seg cache descriptors for subsequent use can be saved.

This object is achieved by the features of Claim 1 or procedural by those of Pa claim 4 solved.

In a memory management system according to the invention for Microprocessors becomes a segment descriptor depending on generated a segment selector. In one embodiment According to the invention, the memory system has a descriptor cache for holding previously fetched, unscrambled and tested Descriptors for subsequent access by the same se proofreaders. If the descriptor is not in the descriptor cache is found, the selector is used to fetch a scrambled, unprocessed descriptor from memory. The scrambled one The descriptor is then descrambled before entering a segment register is loaded. The same descrambled descriptor is also used used to update the descriptor cache such that it can be found below.

In the following, the invention will be described with reference to the drawing explained. The drawing shows:

Fig. 1 (a) is an illustration of a memory address translation mechanism;

Fig. 1 (b) the format of a segment selector;

FIG. 2 shows the format of a segment descriptor;

Fig. 3, the method of descrambling a gescram Belts segment descriptor;

Fig. 4 is a block diagram representation of the method of loading a segment register in protected mode;

Fig. 5 is a block diagram representation of the teaching of the invention-containing memory segmentation assurance system;

Fig. 6 is a flowchart of the operation of loading a segment descriptor;

Fig. 7 is a currently implemented descriptor cache;

Fig. 8 is a currently implemented pseudo-LRU replacement algorithm.

An improved memory management system is described for storage operations in computers, the special application Possibilities for microprocessor memory systems under use of segmentation technology and memory access efficiency improved. In the following description, the Purpose of explanation special stores, organizations, ar chitectures, data rates, etc. given to the understanding of to facilitate the present invention. However, it is for the Those skilled in the art will appreciate that the invention can be practiced without this particular Details can be realized. In other cases known circuits shown only in block form to the Er not burden the invention with unnecessary details.

Referring now to Fig. 4, the process of loading a segment register is shown in block diagram form. Note that segment register loading is a basic operation for each segmentation memory management scheme. When the processor encounters a selector from a command such as MOVE SEG REG, the processor first tests the selector for any privilege violations, such that a less privileged program cannot use a more privileged program to access protected data . If no privilege violation is detected, an 8-byte descriptor is fetched from the memory / data cache by the processor based on the identification of a descriptor table and a descriptor within that table by the selector. This descriptor is checked for privilege violations. If no privilege violation is found, the descriptor is descrambled and information related to the segment, such as segment size and location, and control and status information can be loaded into the segment register to be executed by the program.

As is understood by those skilled in the art, the invention provides an improved storage system is available by using previously fetched and tested descriptors in an associative memory allows to hold back. With subsequent segment descriptor Loads of the same descriptor become the segment descriptor cache searched. If the segment descriptor cache is the one you want Contains the segment register file directly from the Segment descriptor cache can be loaded, making it all in one Processor with no segment descriptor cache steps required be ignored. This way the performance the memory segmentation system significantly increased.

Referring now to Figure 5, the segment register load memory system is shown in accordance with the teachings of the present invention. It should be understandable for a person skilled in the art that the dimensions of the buses are given only for reasons of clarity and that the invention can be realized without the special details of this illustration. As shown in FIG. 5, system 500 includes a selector privilege checker 510 for checking privilege violations in selector 501 such that a less privileged program cannot gain access to protected data. In the current implementation, the selector overrides the privilege level of the program if the privilege field of the segment selector contains a privilege level higher (ie, less privileged) than the program. When the selector 501 passes the privilege checker 510 , it is transferred to the descriptor address generator 520 . The descriptor address generator 520 then generates the correct descriptor address for the selector in the descriptor table. Two descriptor tables are currently used - global and local descriptor tables. The address generation process involves changing the current segment to specify a table based on the selection by selector 501 and setting the rms address to the selector index value. With the effective address, a descriptor can be fetched from the memory 530 and temporarily stored in the descrambler 550 and the descriptor checker 540 . Descriptor checker 540 checks the descriptor to control its access to the segment. If an access violation occurs, an error is given to the processor. If there is no access violation, the descrambler 550 transforms the descriptor into an internal descrambled form, as shown in FIG. 3. A successful descriptor is loaded into segment register file 560 and updates descriptor cache 570 for future use.

In the following, reference is made to FIG. 6. In this is shown a flow chart indicating the sequence of operations of loading a segment descriptor. When the selector 501 occurs, as in a MOV Sreg instruction, the descriptor cache 570 is searched. If a corresponding descriptor is found ("a hit"), the descriptor is loaded from the descriptor cache 570 into the segment register file 560 together with the selector 501 . If no corresponding descriptor is found ("a failed attempt"), the selector 501 is checked for privilege violations, and an error can be generated in a selector with an insufficient level of privilege. When selector 501 passes privilege checker 510 , the linear descriptor address can be calculated and the descriptor is fetched from memory 530 . The descriptor is also checked for its privilege level, and an error is generated in the event of privilege violations. The descriptor is descrambled or reformatted and then loaded into the segment register file 560 . The descrambled descriptor is also used to update descriptor cache 570 .

Referring now to Fig. 7, a diagram of a segment descriptor cache is shown in current implementation. While a 4-by-16 set associative cache is shown, it should be apparent to those skilled in the art that other organizations can be readily implemented to achieve the desired functionality. The descriptor cache 770 is divided into three arrays: a tag array 720 , a data array 730, and a longest unused (LRU) array 710 . The selector bits (4: 3) serve as the record number and as an index in the descriptor cache. Each sentence consists of 4 "paths", each of which is searched associatively for the desired entry.

The LRU entry 715 consists of 3 bits, which are used to determine the path that has been used the longest in the block. When a new entry is to be entered into the descriptor cache, the LRU entry of the set determines which entry can be replaced with minimal performance degradation. As shown in Fig. 8, a pseudo LRU algorithm in conjunction with the three LRU bits, called L0, L1 and L2, is used to determine the entry to be replaced.

Descriptor tag 740 from tag array 720 contains the remaining selector bits and processor privilege level when the entry was placed in the descriptor cache. The tag also contains a valid bit 741 , which indicates whether the entry is valid, and a code segment flag (CS) 742 . The CS flag 742 is used to identify the type of cache-stored descriptor, because - unlike data segments - different protection checks are used for CS. The data array 730 contains unscrambled segment descriptors, each of which contains access rights 751 , base address 752 and boundary 753 .

Claims (6)

1. Memory segmentation system for a microprocessor, a segment descriptor ( 350 ) in a second format being loaded into a segment register ( 560 ) as a function of a load command with a segment selector ( 501 ), characterized by
the segment selector ( 501 ) receiving descriptor cache ( 570 ; 770 ) for storing a plurality of segment descriptors ( 350 ) in the second format, which are each assigned to a plurality of segment selectors ( 501 ) such that the descriptor cache means ( 570 ; 770 ) output a segment descriptor ( 350 ) in the second format to the segment register ( 560 ) if the segment descriptor ( 350 ) in the second format is assigned to the segment selector ( 501 );
Selector checking means ( 510 ) which receive the segment selector ( 501 ) if no segment descriptor located in the descriptor cache means ( 570 ; 770 ) is assigned to the segment selector ( 501 ), the selector checking means ( 510 ) being designed in such a way that that they determine whether the segment selector has a first predetermined privilege level;
Descriptor linear address generator means ( 520 ) coupled to the selector checking means ( 510 ) and generating a linear descriptor address from the segment selector ( 501 );
Descriptor fetching means that, based on the linear descriptor address, fetches a segment descriptor ( 300 ) in a first format from a descriptor table;
Descriptor test means ( 540 ) for determining whether the segment descriptor ( 300 ) in the first format has a second predetermined privilege level; and
Descriptor formatting means ( 550 ) for reformatting the segment descriptor in the first format into the second format when the segment descriptor ( 300 ) in the first format has the second predetermined privilege level, the formatting means ( 550 ) indicating the segment descriptor ( 350 ) in the second format output the descriptor cache means ( 570 ) to update their content such that the segment descriptor ( 350 ) in the second format is assigned to the segment selector ( 501 ), the descriptor cache means ( 570 ) also the segment descriptor ( 350 ) in output the second format to the segment register ( 560 ) and wherein the segment descriptor ( 350 ) in the second format can be loaded directly from the descriptor cache means ( 570 ) when the segment selector ( 501 ) is received by the descriptor cache means ( 570 ) . 2. Memory segmentation system according to claim 1, characterized in that the descriptor cache means ( 570 ; 770 ) contain ent:
a set array ( 710 ) with a plurality of sets, one of which is selected by the segment selector ( 501 ) and each can be replaced according to a predefined replacement algorithm ( FIG. 8);
a tag array ( 720 ) having a plurality of descriptor tags ( 740 ) where the tag array is organized into multiple sets, each of which consists of multiple paths associative with the sets from the set array; and
a data array ( 730 ) with a plurality of segment descriptors ( 750 ) in the second format, the data array being set associative with each of the sets of the tag array. 3. Memory segmentation system according to claim 2, characterized in that the set array ( 710 ) is designed such that it implements a longest-unused replacement algorithm (LRU). 4. A method of loading a segment descriptor in a second format into a segment register in response to a segment selector load using a microprocessor memory management system in which a segment of the memory is specified by the segment descriptor in the second format in a segment register and wherein the segment descriptor in the second format is specified by a segment selector, characterized in that
that a segment selector is entered into a descriptor cache,
that the descriptor cache is searched to determine whether a segment descriptor corresponding to the segment selector is present in the second format in the descriptor cache, that if the segment descriptor is present in the second format it is loaded into the segment register, the descriptor Cache contains a plurality of segment descriptors in the second format which are assigned to a plurality of corresponding segment selectors;
that in the absence of the segment descriptor in the second format in the descriptor cache, the segment selector is subjected to a selector check to determine whether the segment selector has a first predetermined privilege level;
that a linear descriptor address is generated;
that the segment descriptor is fetched in a first format from a descriptor table based on the linear descriptor address, the descriptor table storing a plurality of segment descriptors in the first format;
that the segment descriptor in the first format is checked to determine whether the segment descriptor in the first format has a second predetermined privilege level;
that the segment descriptor is reformatted in the first format into the second format,
that the segment descriptor is loaded into the segment register in the second format and
that the descriptor cache is updated with the segment descriptor in the second format such that the descriptor cache causes the segment descriptor in the second format to be loaded directly into the segment register when the same segment selector is subsequently received,
thereby specifying a segment that is loaded into the segment register based on the segment descriptor in the second format. 5. The method according to claim 4, characterized in that a descriptor cache with a set array, a tag array and a data array is used and that the search of the descriptor cache is carried out as follows:
the selector specifies a sentence from the sentence array,
a tag from the tag array corresponding to the sentence from the sentence array is selected, the tag array being organized in several ways associative with the sentence array, and
the second format segment descriptor is selected according to the tag from the tag array. 6. The method according to claim 5, characterized in that each of the sentences from the sentence array corresponds to a given one replacement algorithm is replaced.