DE4139314C1 - Coupling circuit for transputer forming data processing network - uses complementary logic circuits coupled to data interfaces for generating service signals and decodes augmented acknowledge signal at receiver - Google Patents

Abstract

The transputers have a number (pref. four) of data interfaces (LINKS) for the exchange of information signals (DATEN) and acknowledge signals (ACK), through which service signals are exchanged between the transputers for re-setting (RESET), analysing states (AN-ALYSE), and indicating errors (ERROR). The data exchange of the service signals takes place in combination with an acknowledge signal through the approp. data interface, each of these having a complementary logic unit (20,30) on the receiving and the tnasmitting side. The transmitting side (20) generates the service signal, producing an extended acknowledge signal which the receiving side (30) decodes. The receiver then eliminates the serice signals. The transputers are 16 or 32 bit computers with microcoded commands. ADVANTAGE - Reduction in wiring and leads.

Description

The present invention relates to a coupling circuit for transputers according to the preamble of claim 1.

Transputer 1 are 16-bit or 32-bit computing units with a microcoded instruction set. The basic or structural principle can be seen from the illustration in FIG. 1 and is known from
- Eckelmann, Peter: Transputer multiprocessor systems without bus.
In: the electronics engineer, 1986, No. 4, pages 55 to 61, in particular Fig. 3, or
- Eckelmann, Peter: 2nd generation transputer.
In: Electronics 1987, No. 18, pages 61 to 64 and 67 to 70, especially Fig. 6 and page 70, last chapter.

The output or core element of a transputer is a processor 2 with a (not shown) hardware distribution mechanism (scheduler) for parallel processes and with a timer 3 . The processor 2 is connected to an on-chip RAM 5 via an internal bus 4 ; the internal bus 4 also leads to an external memory interface (EMI) 6 , via which an additional external address space is open to the transputer 1 .

The so-called LINKS 7 , which are data or communication interfaces, are also coupled to the internal bus 4 . These are four bit-serial, bidirectional input / output channels. It is these data and communication interfaces (LINKS 7 ) that enable a direct point-to-point connection of transputers to complex computer networks and that clearly distinguish this chip family, ie the transputers 1 , from other microprocessors. The LINKS 7 are the bearers of the intertransputer communication, the connection of two LINKS of two transputers being made simply by the two connections (LINK IN 8 / LINK OUT 9 ) being coupled as a once crossed two-wire connection.

The LINK interface sends every data byte that still is provided with two prefix and a terminating bit, simply off and then waits for an acknowledgment signal. The LEFT represents the idle state. The 0 level Information bytes therefore begin with two at 1 level set start bits, to which the eight data bits in the Follow the order of their numerical value. The The rearguard forms a stop bit with 0 level. An information signal has the following format:

The acknowledgment signal (ACK) consists of the two bits 1 and 0 and signals the successful reception of the last sent information signal.

For the sake of completeness, it should also be noted that, for the "interplay" of the transputers 1 coupled to one another in a network, a series of service signals are also exchanged. In connection with the present invention, the signals "RESET" R, "ANALYZE" A and "ERROR" E are important in this regard, which - according to the computer networks shown in FIG. 2 - each have their own data line 10 , 11 , 12 are transmitted between the interconnected transputers 1 . The "RESET" signal R is used to normalize a transputer, ie the transputer 1 is reset when it receives the "RESET" signal and begins with a new work cycle; the "ANALYZE" signal A is generated in conjunction with the "RESET" signal and is used to monitor the state of the transputer 1 coupled via the LINK interface 7 ; the "ERROR" signal E serves, as it were, as an error message for a transputer 1 connected upstream.

As mentioned, computer or transputer networks are shown in FIG. 2. These basic representations shown in FIG. 2 are only intended to show different network configurations by way of example. The illustration on the left shows a toroid network, the middle one a grid network and the right one shows a tree structure.

As mentioned in the prior art, the above-mentioned service signals R, A and E are each carried individually via a data line 10 , 11 , 12 between the interconnected transputers 1 . This requires - as can easily be seen from the composite structures shown in FIG. 2 - a considerable amount of wiring.

The object underlying the present invention is to reduce the wiring effort that occurs when coupling transputers.

The solution to this problem is specified in the characterizing part of patent claim 1 and, according to the main idea - in other words than used in patent claim 1 - consists in the fact that the service signals "RESET" transmitted by hardware via data lines 10 , 11 , 12 according to the prior art. , "ANALYZE" and "ERROR" are now each attached to the acknowledgment signal (ACK) outgoing via the LINK interface. The data lines 10 , 11 , 12 can consequently be omitted and this plays a very important role, in particular in connection with the construction or the costs of transputer networks via coaxial or light conductor lines - the costs decrease quite significantly.

The logic circuits for realizing the claim 1 defined core solution are the subject of Subclaims.

The invention is described below with reference to the drawing explained in more detail. This shows in

Fig. 1, the above-explained block diagram of a transputer,

Fig. 2 shows three schematic representations of transputer network,

Fig. 3 is a block diagram of an inventive wired transputer,

Fig. 4, the transmitter-side logic circuit for the generation of the extended acknowledgment signal,

Fig. 5 shows the logic circuit on the receiver side for converting the extended acknowledgment signal into a conventional acknowledgment signal.

Fig. 1, the basic elements of a transputer 1 is already described with respect to, said service signals "RESET", "Analysis" and "ERROR" are transmitted each for itself via a data line 10, 11, 12 in the illustration of FIG. 1. According to the present invention - compare FIG. 3 - the conventional management logic for the above-mentioned service signals R, A and E, as well as the three data lines 10 , 11 , 12 are eliminated as connections between two transputers of a network. For this purpose, the inputs / outputs of the LEFT 7 are modified in terms of circuitry to the extent that they are each assigned a logic circuit 20 or 30 , which in turn take over the management of the service signals R, A and E mentioned.

The transmitter-side or output-side logic circuit 20 is thus part of the output connection LINK OUT 9 ; on the other hand, the logic circuit 30 on the receiver or input side is part of the input connection LINK IN 8 . This results in three signal connection identifications for each LINK connection between the actual LINK 7 and the data line outgoing to the connected transputer 1 or incoming from the connected transputer 1 , namely

viewed at the entrance from the coupled transputer
LINK in (IN) compare reference numerals a
LINK in (OUT) compare reference symbol b
LINK in compare reference numerals c = 8 , and
viewed at the exit from the transputer itself
LINK out compare reference numerals d = 9
LINK out (IN) compare reference symbol e
LINK out (OUT) compare reference numerals f

From a functional point of view, an information signal or an acknowledgment signal is transmitted via both data lines, care being taken in the transmitter-side logic circuit 20 that an information signal is simply "looped through" while an acknowledgment signal (ACK) is expanded to the extent that a "RESET" is added to the service signals "," ANALYZE "and" ERROR "supplemented, ie expanded acknowledgment signal (ACK ′) is output. In the receiver-side logic circuit 30 , on the other hand, it is again ensured that an information signal is “looped through” while an incoming extended acknowledgment signal (ACK ′) is freed from the attached service signals; the LINK 7 itself only receives the usual acknowledgment signal (ACK).

An exemplary embodiment of a transmitter-side logic circuit 20 will be explained with reference to FIG. 4. The individual switching elements or circuit complexes are:
The core element is a sequential control system (finite state machine) 201 , which ensures the correct predefined sequence of the logic circuit 20 as a whole. This sequence is ensured by means of an assigned counter 202 , which is connected to the sequence controller 201 via four status lines 203 . Depending on the counter reading, a specific step is triggered in the sequence control 201 , which in turn causes the logic circuit 20 to do something specific. To synchronize the incoming data or signals, a synchronizing circuit 204 with a clock generator is provided, in which a working clock synchronized with the incoming data stream is generated via a shift clock generator 205 with a frequency (n × shift clock) and a clock divider 206 (division: n).

The circuit elements or components mentioned are also connected to a detection circuit designed as a two-stage shift register 207 (flip-flop R1 and R2), in which the two prefix bits "11" of an information signal or the classic acknowledgment signal (ACK) "10" are decoded. Depending on the inserted or recognized bits, a specific sequence of the logic circuit 20 is then continued in the sequence controller 201 .

If the bit sequence "11" is recognized in the shift register 207 , a data stream arriving via the connection LINK out (IN) e is recognized as an information signal. . . it is clocked via a flip-flop L1 and via a first OR gate 208 to the output of the logic circuit 20 LINK out (OUT) f, via a further OR gate 209 . At the end of the information signal - compare above - there is a stop bit, via which the end of the data transmission and finally the resetting (normalization) of the logic circuit 20 is indicated or initiated.

If the bit sequence "10" is recognized in the shift register 207 , the acknowledgment signal (ACK) is initially expanded by a 0 bit depending on the respective counter reading. Then one bit at a time for the signals "RESET", "ANALYZE" and "ERROR" are generated and added. At the end there is again a 0 bit. Ultimately, an extended acknowledgment signal (ACK ′) is therefore output LINK out (OUT) f

1 0 0 R A E 0

submitted. It should be noted that the service signals mentioned are each switched to the transmission line via an AND gate 210 , 211 , 212 each. The output of these AND gates 210 , 211 , 212 is in each case on the input side at said second OR gate 209 of the LINK out (OUT) output f.

The functions mentioned are again shown below using the status table for data transmission on the one hand and the receipt generation on the other. The essential point is that depending on the content of the shift register 207, a selection is made after data transmission or receipt generation.

Data transfer

receipt

As is well known, there is also the work of computers and transputers states in which a program does not terminate is no longer possible. Of course, this must be prevented, but what is not possible if no acknowledgment signal (ACK) is generated for normalization.

To counteract this possibility from the outset, "Automatic" is provided in a special embodiment, which by itself an acknowledgment signal (ACK) generate and thus normalize the transputer, d. H. can reset.

This automatic acknowledgment signal generation takes place again via the counter 202 , specifically via a signal "AUTOACK", which activates the sequential control unit 201 , is generated by the coupled transputer 1 and is supplied via a connection 213 . The process is as follows:

AUTOACK

For the sake of completeness, it should also be noted with regard to the transmitter-side logic circuit 20 that an ERROR signal P for a parity error is additionally integrated in the signal conditioning circuit 214 consisting of the AND and OR elements 210 , 211 , 212 and 208 , 209 can, which possibly leads to a change in the extended acknowledgment signal (ACK '), namely

1 0 0 R A E P 0.

The logic circuit 20 described so far on the transmitter side therefore outputs the information signal or the extended acknowledgment signal (ACK ') at the output f. In order to reliably avoid that incoming information signals and the extended acknowledgment signal (ACK ') do not overlap in time, a shift register can be inserted for time equalization - optionally as an alternative to flip-flop L1 - in which the interval required for clock-correct processing is set .

Referring to Fig. 5, the receiver-side logic circuit will be explained in the 30th Based on the principle of a transputer 1 of FIG. 1 is, this logic circuit 30 between the terminals LINK in (IN) a and LINK in (OUT) b, and the principal function of this logic circuit 30 is an incoming extended acknowledgment signal (ACK ') exempt from its appendix, ie from the attached service signals "RESET", "ANALYZE" and "ERROR".

The structure of this logic circuit 30 on the receiver side essentially corresponds to that of the logic circuit 20 on the transmitter side, that is to say a sequential control 300 is provided with an associated counter 302 and a synchronization circuit 304 , and a shift register 307 consisting of two flip-flops R1 and R2 is assigned in FIG which - depending on the bit sequence of the first two incoming bits - selects whether the incoming data stream as an information signal is directly - via an AND gate 309 to the output LINK in (OUT) b, ie to the actual LINK input c ( 8 ) or whether the data stream is to be treated as an extended acknowledgment signal (ACK ′). In the latter case, the extended acknowledgment signal (ACK ') is recognized in the shift register 307 and flip-flops 310 , 311 , 312 connected downstream of the sequence controller 301 are processed in such a way that the eliminated service signals "RESET", "ANALYZE" and "ERROR" via at the output the control lines 313 , 314 , 315 coupled to the flip-flops 310 , 311 , 312 are transferred to the associated transputers and that a classic acknowledgment signal (ACK) is emitted at the output LINK in (OUT) b via the AND gate 309 .

The function should be based on the following status table are represented differently:

Data transfer

receipt

In the event that a PARITYERROR signal is implemented, the receiver-side logic circuit 30 must be adapted accordingly.

For the sake of completeness, it should be targeted again be noted that unlike conventional Networks - where the service signals of a transputer only by a parent transputer managed - is according to what is proposed here Procedure management of service signals from everyone communicating transputer possible. This is particularly so then relevant when different processes of a transputer can be controlled via various LEFT or if there is a changeable network topology, in which - according to conventional technology - the case occurs can that the LINK networking is not with the wiring the service signals match what is going on here administrative problems.

Claims (7)

1. coupling circuit for transputer,
in particular to set up a data processing network,
wherein the transputers have a plurality (preferably four) of data interfaces (LINKS) for exchanging information signals (DATA) and acknowledgment signals (ACKNOWLEDGE), and
service signals for resetting (RESET), status analysis (ANALYZE) and error messages (ERROR) are also exchanged between the transputers,
characterized in that the data exchange of the service signals takes place in combination with the respective acknowledgment signal via the corresponding data interface, for which purpose a complementary logic circuit ( 20 , 30 ) is assigned on the receiving and transmitter sides,
whose transmitter side ( 20 ) generates the service signals and connects them with the acknowledgment signal to form an expanded acknowledgment signal, and
whose receiver-side ( 30 ) decodes the extended acknowledgment signal consisting of the acknowledgment signal and the service signal and eliminates the service signals. 2. Coupling circuit for transputer according to claim 1, characterized in that the transmitter-side logic circuit ( 20 )

• a sequence control (finite state machine) ( 201 ) with a counter ( 202 ) which determines the steps to be initiated by the sequence control ( 201 ),
• a synchronizing circuit ( 204 ) with a clock generator which decodes the signals coming from the data interface ( 7 ) of the transmitting transputer ( 1 ) and synchronizes them with the operating cycle of the logic circuit ( 20 ),
• a detection circuit (shift register 207 ), in which, depending on an identification signal preceding the information or acknowledgment signals, it is recognized whether an information signal or an extended acknowledgment signal is to be sent, and
• a signal processing circuit ( 214 ) in which output signals of the sequential control system ( 201 ) corresponding to the service signals are linked to the service signals generated in a generation logic of the transputer ( 1 ) and optionally attached to the acknowledgment signal,

having. 3. coupling circuit for transputer according to claim 2, characterized, that to be sent out for forced synchronization between one Information signal and one if necessary extended acknowledgment signal not fully transmitted a shift register is provided.   4. Coupling circuit for transputer according to claim 2 or 3, characterized in that the transmitter-side logic circuit ( 20 ) has a logic logic circuit via which an acknowledgment signal is generated independently of the coupled transputer ( 1 ). 5. Coupling circuit for transputer according to claim 1, 2 or 3, characterized in that the receiver-side logic circuit ( 30 )

• a sequence control (finite state machine) ( 301 ) with a counter ( 302 ) which determines the steps to be initiated by the sequence control ( 301 ),
• a synchronizing circuit ( 304 ) with a clock generator which decodes the signals coming from the data interface ( 7 ) of the transmitting transputer ( 1 ) and synchronizes them with the operating cycle of the logic circuit ( 30 ),
• - a detection circuit (shift register) ( 307 ), in which, depending on an information signal preceding the information or acknowledgment signals, an identification is made as to whether an information signal or an extended acknowledgment signal is to be processed, and
• - a logic circuit ( 316 ) in which, depending on the identification signal of an extended acknowledgment signal, this is freed from the service signals and which feeds these service signals into control lines ( 313 , 314 , 315 ) of the transputer ( 1 ),

having.