DE3917666A1 - Pulse signals deriving circuitry for VTR - has clock pulse signal generating circuit, pulse width and pulse position testing circuit, and phase control loop - Google Patents

Abstract

The pulse signals are coupled to the sync. signal of a video signal, transmitted by a video tape recorder. The pulse signal derivation uses a video signal clamping circuit and a threshold value circuit for separating the sync. signal from the video signal. A circuit (13) test the pulse width and position of the separated sync. signal in dependence on a cloch pulse signal from a generating circuit (12), and a gate pulse signal. A digital phase control loop comprises a counter (14), fed back via an EPROM (15), for the cloch pulse signal pulses counting. ADVANTAGE - Reliable evaluation of sync pulses, contg. in video signal.

Description

The invention relates to a circuit arrangement Derivation of pulse signals according to the generic term of Claim 1.

From German published patent application 26 25 775 is one Synchronous pulse separation circuit for a BAS television signal known in a video recorder, in which with a Trigger circuit sync pulses from the adjacent BAS television signal can be separated. The sync pulses control two switches for clamping and blanking the BAS television signal are provided.

Furthermore, from German patent DE 34 44 764 C2 Pulse isolation circuit with a feedback Operational amplifier known as a clamp stage. The clamping step controls a downstream comparator to separate the Sync pulses in the video signal.

Furthermore, a digital is from the US patent 44 91 870 Sync separator with a counter known, the pulses of a Clock signal counts. The counter is logical AND operation reset by horizontal sync pulses.  

There is a decoder arrangement at the outputs of the counter connected which has a vertical synchronizing signal and a gate signal the color synchronizing signal from the applied synchronizing signal derives.

These known circuit arrangements are prone to failure against drop-out interference in the reproduced video signal, so that of the synchronous signal of that taken from a magnetic tape Video signal derived pulse signals have errors that increase an incorrect segment switchover or time error correction to lead.

The present invention has for its object a Specify circuit arrangement according to the type mentioned at the outset, which reliably contained sync pulses in the video signal evaluates and is insensitive to drop-out disturbances.

This task is carried out in the characterizing part of the Features specified claim 1 solved.

The circuit arrangement according to the invention with the characterizing features of claim 1 has the Advantage that through defects in the magnetic tape or through lack of head-to-band contact caused interference in the removed video signal that derived from the synchronous signal Impulse signals remain almost unaffected. Through the interference-free derivation of the pulse signals can playback-side functions, such as switching the Magnetic heads, clamping, gain control, burst-gate or Time error correction of reproduced video signals more reliable be performed.

By the measures listed in the subclaims advantageous developments and improvements in Claim 1 circuit arrangement possible. It is particularly advantageous that time-critical switching elements such as B. monostable multivibrators or analog phase locked loops, are built digitally. The invention  Circuit arrangement is therefore free from aging and Temperature drift phenomena.

An embodiment of the invention is shown in the drawing and explained in more detail in the following description. In the single figure, 1 denotes a magnetic tape 1 , which is scanned by two magnetic heads 2 and 3 of a rotating scanning device (not shown) on tracks running obliquely to the tape edge of the magnetic tape. When the magnetic tape 1 is wrapped around 180 ° around the rotating scanning device, it is necessary to connect the magnetic heads 2 and 3 via a controlled changeover switch 4 to the input of a stage 5 which pre-amplifies and equalizes the signal taken from the magnetic tape 1 . Stage 5 is followed by stage 6 with a drop-out detector and a frequency demodulator. The frequency demodulator emits a video signal provided with synchronous pulses and the drop-out detector emits a drop-out signal in the event of signal dips in the FM signal.

The video signal obtained is supplied on the one hand to a clamping stage 7 and on the other hand to a synchronizing pulse separation circuit 8 . In the present exemplary embodiment, the synchronizing pulse separating circuit 8 consists of a peak value rectifier, which determines the voltage value of the synchronous cause of the negatively directed synchronizing pulses. The determined voltage value serves as a reference level for a comparator, which separates the sync pulses from the applied video signal. The separated sync pulses are logically combined with the drop-out signal in an AND stage 9 and forwarded to the clamp stage 7 as a clamp pulse signal. With the help of the clamping pulse signal, the demodulated video signal is clamped to the synchronous ground in terms of DC voltage. With a comparator 10 connected downstream of the clamping stage 7, the synchronizing pulse signal is then separated from the clamped video signal depending on the reference level of a reference voltage source 11 .

The synchronization pulse separation with the comparator 10 works more precisely than the synchronization pulse separation circuit 8 used to generate the clamping signal, so that timing errors in the video signal can be determined exactly on the basis of the edges in the synchronization pulse signal. In the normal operating state, the synchronous pulse separation circuit 8 and the comparator 10 deliver simultaneous pulses. In the event of a fault, however, the peak value rectifier located in the synchronizing pulse separating circuit 8 can charge itself to such a negative value that no synchronizing pulses can be separated for a short time. In order to prevent this in the event of a drop-out, the peak value rectifier is controlled by the drop-out signal, during which time the voltage value determined so far is stored.

According to the invention, the synchronous pulse signal emitted by the comparator 10 is checked for plausibility. The synchronous pulse signal is examined in relation to the pulses of a clock signal generated by a clock generator 12 . In the present exemplary embodiment, the clock signal is coupled to 264 times the horizontal frequency of an HDTV video signal (1250 line system). At a line frequency of 31.25 kHz, the frequency of the clock signal is 27 MHz.

To check the pulse width and the pulse position, the 27 MHz clock signal and the separated synchronizing signal are fed to a test circuit 13 . The test circuit 13 contains a counter for counting the pulses of the clock signal. When there is a falling edge in the synchronous signal, the counting process is started and stopped when there is a rising edge. The number of clock pulses counted determines the width of the synchronizing pulses present. In the present exemplary embodiment, 20 clocks of the 27 MHz clock signal must be present for a synchronizing pulse in order to provide information about a valid synchronizing pulse. In this number, a tolerance range is taken into account, which results from the asynchrony of the 27 MHz clock signal with the removed video signal. If there is a drop-out in the counting interval, the counting process is aborted by control via the drop-out signal and the counter is reset.

As mentioned at the beginning, the pulse position of the synchronizing pulses is also checked. For this purpose, the test circuit 13 is supplied with a gate pulse signal with a defined time window by a digital phase-locked loop, which consists of a counter 14 , a programmable read-only memory 15 and an OR stage 16 . The time window of the gate pulse signal limits the interval in which a synchronizing pulse can be expected in the synchronizing pulse signal. Counter 14, which acts as an address counter, counts pulses of the 27 MHz clock signal. The address values obtained at the output of the counter 14 are forwarded via an address bus to the programmable read-only memory 12 , at the output of which a large number of horizontally frequency-coupled pulse signals can be removed. Among other things, when a certain counter reading is reached, the programmable read-only memory 15 emits a pulse signal which, via the OR link 16, resets the counter 14 to an initial address value. In addition, the synchronous pulse signal, which has been checked for plausibility, is fed to the counter 14 in order to synchronize the digital phase locked loop.

The accuracy of the circuit arrangement according to the invention is determined by the clock frequency of the clock signal generated by the clock generator 12 . The accuracy is independent of temperature changes, aging or drift phenomena.

The synchronous pulse signal checked for plausibility is required for the various playback circuits of a video magnetic tape device. However, the requirements of these playback circuits on the synchronous pulse signal are quite different. Synchronous pulses that are used to derive a clamping signal must be suppressed in the blanking interval in the event of a drop-out, so that no clamping errors occur. The clamping signal is therefore expediently derived from the synchronizing pulse signal H _band output by the test circuit 13 . On the other hand, pulses that are required for head switching must also be available when the video signal is disturbed. These pulses are advantageously taken from outputs of the programmable read-only memory 15 . The same applies to pulses that are used to evaluate the time error in the time error compensator.

In the case of a circuit implementation, the test circuit 13 advantageously consists of a programmable module (GAL) which is programmed as a state machine and which queries the timing of the synchronous pulses according to certain conditions or according to a specific requirement profile. It has proven to be advantageous to replace the digital phase locked loop with the counter 14 , the programmable read-only memory 15 and the OR link 16 by a programmable component (GAL) in terms of circuitry. Targeted address decoding can be used to derive pulse signals of any shape.

Claims (4)

1. Circuit arrangement for deriving pulse signals which are coupled to the synchronous signal of a video signal taken from the magnetic tape of a video magnetic tape device
a circuit for clamping the video signal and
a threshold circuit for separating the synchronous signal from the clamped video signal, characterized by

• - a circuit ( 12 ) for generating a clock signal,
• - A circuit ( 13 ) for checking the pulse width and the pulse position of the synchronizing pulses in the separated synchronizing signal as a function of the clock signal and a gate pulse signal and
• - A digital phase locked loop with a via a programmable read-only memory ( 15 ) fed back counter ( 14 ), which counts pulses of the clock signal and can be reset by a horizontal-frequency pulse signal at the output of the checking circuit ( 13 ) or the programmable read-only memory ( 15 ) and which address signals are programmable Read-only memory ( 15 ) supplies, at the outputs of which the pulse signals and the gate pulse signal can be removed.

2. Circuit arrangement according to claim 1, characterized in that the checking circuit ( 13 ) can be controlled by a dop-out signal such that when a drop-out is present, no pulse signal ( H _band ) to the phase locked loop ( 14 , 15 , 16 ) will give up. 3. Circuit arrangement according to claim 1 and 2, characterized by a checking circuit ( 13 ) with,
a further counter, which starts when there is an edge in the synchronous signal for counting clock pulses of the clock signal, is stopped again by a subsequent edge in the synchronous signal and is reset by the drop-out signal, and
a logical linking device at the output of the counter, which is provided for evaluating the counter reading of the further counter. 4. Circuit arrangement according to claim 1, characterized in that the frequency of the clock signal is much higher than that Frequency of the separated synchronizing signal.