DE3739423A1 - Frame buffer - Google Patents

Abstract

A frame buffer exhibits a serial/parallel converter in order to convert serial input data into parallel data, a first latching device for latching the parallel data from the serial/parallel converter, a data buffer for storing parallel data which were output by the first latching device, a second latching device for latching parallel data which were read out from the data buffer, a parallel/serial converter for converting parallel data, which were read out at the second latching device, into serial data, an address generator for supplying a write address and a read address to the data buffer on a time-division basis, and an address control device for controlling the address generator.

Description

The present invention relates to an image memory which is suitable for storing and playing back video signals, and relates in particular to an image memory which is used for digital signal processing with a predetermined time delay of the sampled and quantized video signals suitable is.

The frame buffer for delaying a predetermined time interval or save sampled and quantized Video signals is considered a fundamental building block of Televisions with high picture quality, a video recorder with multiple functions, a digital television device and the like, requires a simple one Handling and must comply with general purpose requirements.

In the past it has been practice that a variety of general-purpose dynamic RAMs (random access memories) connected in parallel at a low price per bit have been used as image storage in such Serve device. However, the storage capacity is pro Chip has recently grown to 256 Kbit or 1 Mbit and allows the realization of one for video signal processing necessary storage capacity with a chip, and therefore the usual parallel connection is a multitude of storage has become disadvantageous because of the utility efficiency the storage capacity has deteriorated.  

In particular, since the cycle time in the dynamic memory is short or slow, very fast data, as represented by a video signal, is usually subjected to a serial / parallel conversion in units of N bits ( N an integer) by to be reduced in speed, and then write / read of the memory with the converted data is effected. As a result, a large number of memories are required, and especially when general-purpose memories with a large capacity and a low price per bit are used, many areas of the memory that are not in use occur, resulting in deterioration in the efficiency of use Word processing leads.

To solve this problem has recently been a dynamic one Memory designed for the very fast serial input / output operation of data is determined connected to a horizontal scan line as described in "Serial Input / Output type Dynamic Memory Dedicated to Picture of 320 Rows × 700 Columns of Field Memory for Television and VTR "by Nagami and Hara, NIKKEI Electronics, February 11, 1985, pages 219-239. However, to to create a system with the proposed memory which has a sampling frequency which is four times the chrominance carrier frequency (referred to here as fsc) is, in Terms of improving resolution or order features such as B. shrinking and enlarging the image bring about, by desirably thinning the written into the memory and read out from the memory Data are sophisticated connector circuits necessary and the proposed memory is not versatile can be used in the general function of video signal processing.

Since in the above representations of the state of the Technique cycles for a write clock signal (referred to here as W. CLK), which is used to write data to an image memory are used, and a read clock signal (here  referred to as R. CLK), which is used to collect data from the Image memory read, not set independently the manufacturing of circuits, which are provided outside the memory, disadvantageous complicated when it is intended to have functions realize, such as introducing a reduced image into memory by thinning out the Write data (referred to here as Din), with an enlarged one Cycle of the W. CLK and an enlargement by Expansion of the read data (referred to here as Dout) at an enlarged cycle by R. CLK.

In addition, the aforementioned prior art is missing the additional function of arbitrary access to the Memory at an externally designated address, and to in the conventional image memory, for example, the function the "Image and Image" display of two different images same screen and a function of displaying different Information on part of the screen Realize the construction of an external circuit disadvantageously very complicated for this purpose.

In addition, there is none in the conventional memory Possibility of writing / reading very simultaneously fast serial data and it is unsuitable for digital processing of continuous video signals based on real time. More specifically, is under construction according to the prior art, a single data register, corresponding to one line, in the input / output stage of a Memory cell array is provided and is shared for write and read operations, so that data between the memory cell array and the data register, in units the data corresponding to a cell can. Consequently, if the continuous video signal for example, the memory will continue to be entered put in write mode, which prevents that data in the previous field comes from the Memory can be read out. Separate image memory for reading  and letters must therefore be provided for the purpose of Execution of simultaneous write and read operations.

Because the data transfer to the memory cell array in Units of data that correspond to one row, In addition, the delay time can only be in units of data that corresponds to a row, and it is difficult to set them to a desired value.

With regard to the disadvantages mentioned in the prior art it is an object of this invention to provide the cycles for the W. CLK and R. CLK independently adjustable to thereby the functions not achievable in the prior art easy to accomplish and enable that Writing data is interrupted while, for example the blanking period or rewind suppression period of the video signals for improvement the useful efficiency of the storage capacity.

Another object of the present invention is in providing an image store that is very fast Input and output operations is suitable and one Capable of performing multi-function processing such as B. a multiple display of two different Images on two sections or sections of the screen and ordinary video signal processing.

Another object of the present invention is in providing an image memory that can be used simultaneously Write / read very fast serial data in the Capable and set the delay time to a value that is not fixed to the data unit that corresponds to a line, but is freely variable.

According to one embodiment of the invention, control circuits are (gate circuits) separately provided for writing and reading,  which serve to thin out a master clock signal (referred to here as CLK), which is used to to control an image memory so that the clock signal from various control signals controlled on the control circuits becomes a W. CLK to fetch a data signal Din and R. CLK to output a data signal Dout create a counter (referred to here as a W counter) for Counting the W. CLK and a counter (here referred to as R counter) for counting the R. CLK are provided separately, and Request generators are provided separately, the counts-decoded values of the counters W and R respond to generate a request signal (here as W. Req) to start a write operation to request data stored as Din in a memory cell field have been entered and a request signal (here referred to as R. Req) to request the start of a Operation to read data from Dout from the memory cell array.

According to a further embodiment, the Invention a counter (referred to here as a CLK counter) provided that counts the CLK, and this counter is reset with a reset signal (referred to here as RES), to initialize its count and that End counting when the count value reaches a predetermined one Value reached, causing the R counter to count to end during the CLK counter counting operation, and the R. Req generator speaks to count-decoded values of the CLK counter and the R counter to generate an R. Req in response to which the operation to read data starts from the memory cell field.

According to a further embodiment, an image memory has a memory cell array, a serial / parallel converter which receives serial data and outputs parallel data from m bits, a parallel / serial converter which receives the parallel data with m bits and it converts to output serial data, an address controller for generating a control signal based on a time division to write the parallel data subjected to serial / parallel conversion into the memory cell array and a control signal for reading the parallel data from the memory cell array, and an address generator responsive to the control signals from the address controller to provide a write address (more specifically, write address data) and a read address (more specifically, read address data) to the memory cell array, wherein the address generator has at least one write and read register, an input selector for selecting each of the outside n supplied desired address data and an incremented / decremented address value and for moving the selected signals into the write register or read register, and an output selector for selectively moving each of the values stored in the write and read register to output a selected value to a memory register , wherein the value of the memory register is given to the memory cell array and at the same time is led to an address increment / decrement device to generate the incremented / decremented address. In this embodiment, a time interval in which both the write and read registers are selected, a selected value is moved into the storage register, and data passed through the address increment / decrement device is again selected by one of the input selection switches , so that either the write or read registers are moved and treated as one cycle in the address generator, and during this one cycle the output of the other register cannot be selected to be moved into the memory register (it is locked).

According to a further embodiment, an image memory has a serial / parallel converter device (SP converter device) for moving and sequentially converting serial input data into parallel data in units of 2 ⁿ bits ( n a natural number), a parallel / serial converter device (PS converter device) for sequentially converting the parallel data in units of 2 ⁿ bits into serial data and outputs of the serial data, a memory cell array of ( K × 2 ⁿ ) columns × m rows, where K and m are natural numbers , a write counter for counting the pulses of a write clock used to move the input data into the SP converter and for outputting a predetermined signal every time it has counted up to ( L × 2 ⁿ ) times ( L is a natural number ), a first holding device, responsive to the output signal of the write counter, for holding the converted data from the SP converter, a read counter, for counting the pulses nes reading clock, which is used to output data from the PS converter device and to output a predetermined signal every time it has counted up to ( J × 2 ⁿ ) times ( J a natural number), a second holding device for temporarily holding parallel ones Data input in units of 2 ⁿ bits for responding to the output of the read counter to supply the parallel data to the PS converter device, a cycle generator device responsive to the output signals of the write and read counters generate a write cycle and a read cycle based on the time division for the memory cell array, address generator means for generating write and read addresses for the memory cell array, reset means for externally resetting the write counter and the read counter independently of one another, and an initialization device for initializing the address value of the write address or read address, the is generated by the address generator in synchronism with the reset of the write counter or read counter, the parallel data being written into the memory cell array during the write cycle in units of 2 ⁿ bits, which are held in the first holding device, on the basis the write address from the address generator, and during the read cycle, the parallel data is read out in units of 2 ⁿ bits from the memory cell array and output to the second holding device based on the read address generator.

Further advantages, features and possible applications of the present invention result from the following Description of exemplary embodiments in connection with the Drawing.

Fig. Is a block diagram explaining a first embodiment of the invention;

FIG. 2 is a timing diagram exemplifying the operation of the embodiment shown in FIG. 1;

Fig. 3 is a timing chart explaining another example of the operation of the embodiment shown in Fig. 1;

FIG. 4 is a circuit diagram showing an exemplary R. Req timer generator as used in the embodiment shown in FIG. 1;

FIG. 5 is a circuit diagram showing an exemplary W. Req timer generator used in the embodiment shown in FIG. 1;

Fig. 6 is a circuit diagram showing an exemplary REF. Req timer generator shows how it is used in the embodiment shown in Fig. 1;

Fig. 7 is a timing chart explaining the operation of the circuits shown in Figs. 4 to 6;

Fig. 8 is a circuit diagram showing an exemplary cycle generator used in the embodiment shown in Fig. 1;

Fig. 9 is a timing chart explaining the operation of the circuit shown in Fig. 8;

Fig. 10 is a block diagram explaining a second embodiment of the invention;

Fig. 11 is a timing chart explaining an example of the operation of the embodiment shown in Fig. 10;

Fig. 12 is a timing chart explaining another example of the operation of the embodiment shown in Fig. 10;

Fig. 13 is a circuit diagram showing an exemplary generator for generating a SEL. R and a latch pulse to an R register which are supplied to an address generator of the embodiment shown in Fig. 10;

Fig. 14 is a timing chart explaining an example of the operation of the circuit shown in Fig. 13;

Fig. 15 is a timing chart explaining the operation of the embodiment shown in Fig. 10 when a W. CLK is controlled with a CGW;

Fig. 16 is a circuit diagram showing a generator for generating cycle signals used to control the address generator of the second embodiment;

Fig. 17 is a timing chart explaining the operation of the circuit shown in Fig. 16;

Fig. 18 is a block diagram explaining a modification of the second embodiment;

Fig. 19 is a timing chart explaining the operation of the modification shown in Fig. 18;

Fig. 20 is a block diagram explaining a third embodiment of the invention;

Fig. 21 is a timing chart explaining the typical operation of the embodiment shown in Fig. 20;

Fig. 22 is a timing chart explaining the operation of the embodiment shown in Fig. 20 when a read reset is effected as desired;

Fig. 23 is a timing chart explaining the operation of the embodiment shown in Fig. 20 when a read and write reset is effected as desired;

FIG. 24 is a circuit diagram showing an exemplary W counter, W. Req generator, and W. Load generator used in the embodiment shown in FIG. 20;

Fig. 25 is a circuit diagram showing an exemplary R-counter, a R. Req-generator and a load R. generator as used in the embodiment shown in Figure 20. and

Fig. 26 is a block diagram explaining a modification of the third embodiment.

Referring to FIGS. 1 and 2, an image memory will be described according to a preferred embodiment of the invention, together with its exemplary switching operation.

In Fig. 1, an SP converter 3 for serial / parallel conversion is connected to an input terminal 1 which receives very fast serial data Din and it responds to a predetermined clock signal to move the serial data and convert it into parallel data convert, which are then output. An input controller 4 is coupled to the output of the SP converter 3 and it responds to an external command signal, which will be described later, for a group of converted m- bit parallel data which are sent by the SP converter 3 move and spend.

The output signal of the input register 4 is fed to a memory cell field 5 , so that each parallel data item of m bits is entered sequentially into the memory cell field 5 . An output register 6 , which is coupled to the output of the memory cell array 5 , stores m- bit parallel data that have been output by the memory cell array 5 . A PS converter 7 is coupled to the output of the output register 6 and converts the parallel input data into serial output data. The PS converter 7 responds to the external command signal, which will be described later, to move the parallel data out of m bits from the output register 6 and responds to an external clock signal to convert the moving parallel data into serial data, and as very fast serial data Dout, which are output from an output terminal 2 .

An address decoder 8 is connected to the memory cell array 5 and, on the basis of the time division, supplies the memory cell array 5 with a write address signal, more precisely a write address data signal (here referred to as a W address signal). To designate addresses in the memory into which the parallel data from m bits, which are sent from the input register 4 , are written, a read address signal, more precisely a read address data signal (here as R addresses Signal) for designating addresses from which data is read out to the output register 6 , and a renovate (refresh) address signal, more precisely a renovate address data signal (referred to here as a REF address signal) for designating addresses in the store, which are to be renovated or refreshed. The address decoder 8 is provided with time-division addresses which are sent by an address generator 9 which operates on the basis of output signals from the address control device 26 .

The structure of the address control unit 26 is now specified in detail. The address controller 26 has a read control circuit (referred to herein as an R control circuit) 15 which is responsive to a read control signal CGR from a terminal 12 to pass a system clock signal CLK from a terminal 14 , and a write control circuit (gate circuit) 16 (referred to herein as a W control circuit) that is responsive to a write control signal CGW to pass the CLK. A read clock signal R. CLK, which is output by the R control circuit 15 , and a write clock signal W. CLK, which is output by the W. control circuit 16 , are in a read counter 17 (here as an R counter referred to) or a write counter 19 (referred to here as a W counter).

A system clock counter 18 (here referred to as a CLK counter) is also provided to count the system clock which is not gated, a renovation counter 20 (here referred to as a REF counter), and one Terminal 11 , through which a reset signal RES is input.

The reset signal and the output signals of the R counter 17 and CLK counter 18 are OR-connected to an OR circuit 22 in order to be supplied to a read request generator 23 (R. Req). Similarly, the count values of the W counter 19 and REF counter 20 are fed to a write request generator 24 (W. Req) and a renovation request generator 25 (REF. Req). If the R. Req, W. Req and REF. Req generator 23, 24 and 25 receive output signals of the OR circuit 22 , or W counter 19 or REF counter 20 , they generate an R. Req, W. Req and REF. Req signal, which in turn is applied to a cycle generator 10 . When the cycle generator 10 receives the input signals R. Req, W. Req and REF. Req receives, it sets a priority in the order of, for example, read, write and renovate and applies to the address generator 9 a read cycle signal (R cycle), a write cycle signal (W cycle) and a renovation cycle signal (REF Cycle) such that these cycle signals do not overlap with each other. The address generator 9 responds to the cycle signals in order to generate corresponding address signals based on the time division, which in turn are applied to the address decoder 8 .

The address controller 26 also has a timing generator 21 which divides the CLK in frequency in order to generate signals Φ ₀ to Φ _n .

The timing generator 21 is configured to generate signals for determining timings on which control signals for determining the operating cycles of the address generator 9 are generated, and it divides the CLK in frequency by 1 / K, for example, and shifts a 1 in phase / K frequency-divided signal at the rate of the CLK, giving signals that are used as timing signals.

In addition to the OR circuit 22 , the R counter 17 , the CLK counter 18 and the W counter 19 are connected to receive the aforementioned reset signal RES from terminal 11 , and each counter is resettable with the reset signal RES.

The output signals R. CLK and W. CLK of the R control circuit 15 and W control circuit 16 are also supplied to the PS converter 2 and SP converter 3 , respectively, so that these converters in each case output and receive the serial data synchronously with the Carry out clock signals.

The R. Req generator 23 and W. Req generator 24 emit an R. load signal and a W. load signal to the PS converter 7 and to the input register 4 , simultaneously with the output of the R. Req signal and the W. Req signal. When the PS converter 7 receives the R. load signal, it thus moves the parallel data from m bits out of the output register 6 . When the input register 4 receives the W. load signal, it moves m bits from the SP converter 3 in the same way and outputs the parallel data from m bits stored therein to the memory cell array 5 .

The input signals at the input terminals 11 to 14 are designated 2 b , 2 c , 2 e and 2 a, respectively, and the CGR and CGW allow the CLK 2 a to pass through to the R. CLK 2 d and W. CLK 2 f to be made available at the outputs of R. control circuit 15 and W. control circuit 16 . The R. CLK 2 d and W. CLK 2 f are used as clock signals to shift the PS converter 7 and SP converter 3, respectively, and are also routed to the R counter 17 and W counter 19 . Accordingly, when a bit of the Din is moved by the SP converter 3 in response to the W. CLK 2 f and the data is shifted, for example, the count value of the W counter 19 is also advanced by one. Similarly, when a bit of the parallel data moved into the PS converter 7 is shifted serially from the R. CLK 2 d to the output terminal 2 , the count value of the R counter 18 has also advanced by one. By selecting the count values of the R counter 17 and W counter 19 such that they are identical to values of the BIT conversion on the PS converter 7 and SP converter 3, respectively, even if the R. uses CLK and W. CLK which are passed on to the respective control circuit 15 and 16 in the desired manner, it is therefore possible to detect a count value which indicates a timing at which bits of the data read out in parallel by the PS converter 7 are all converted and output in series and it is also possible to acquire a count value indicating a timing at which the SP converter 3 is filled with bits of data which are moved serially into the SP converter 3 . In an example of FIG. 2, the number of BIT conversions in the PS converter 7 and SP converter 3 is set to 12 bits, and the count of both the R counter 17 and the W counter 19 is selected to be 12. In this case, the count output signal 2 h of the R counter 17 is generated, for example, at a time period which corresponds to 12 cycles of the R. CLK.

The count output signal of the W counter 19 , although not explained in FIG. 2, is generated in the same way at a time period that is equal to 12 cycles of the W. CLK. Since the count of the REF counter 20 is different from the counts of the R counter 17 and W counter 19 , it is chosen to optimize the renovation cycle in the memory cell array 5 , and in the example of FIG he voted 15.

After receiving the output signals of the respective counters 17 , 19 and 20 , the respective Req generators 23 to 25 generate an R. Req 2 i , W. Req 2 j and REF. Req 2 k , and the cycle generator 10 , which will be explained in more detail later with reference to FIGS . 8 and 9, designate cycles as are indicated in a signal 20 in synchronism with the Φ ₀ 2 l . The address generator 9 , which is ready to receive the cycle signal 20 , generates respective addresses as represented by 2 p on a time division basis. In this way, during a cycle (in the example of FIG. 2, one cycle covers 12 bits of the R. CLK) in which bits of parallel data from the output buffer register 6 to the PS converter 7 in response for example, the R. load signal 2 q are all subjected to serial conversion, and then the following bits of parallel data are passed in response to the R. load signal 2 q that R. Req generates, so that the R cycle is assigned and data read from the memory cell array 5 in accordance with R addresses are transferred to the output buffer register, thereby preparing for repeated transmission of new data to the PS converter 7 . This allows a continuous reading of the very fast serial data of the output signal Dout, which are referred to as 2 s . In addition, during a cycle (in the example of FIG. 2, corresponding to 12 bits of the W. CLK) in which a number of bits to be converted, the serial data Din are moved into the SP converter 3 and in parallel are transferred to the input buffer register 4 in response to the W. load signal 2 r and then a number of the following bits to be converted, the serial data Din is repeatedly moved, the W. Req is generated so that the W cycle is assigned and data is written from the input buffer register 4 into the memory cell array 5 according to W addresses, which prepares for the repeated transmission of parallel data from the SP converter 3 into the input buffer 4 .

This allows the very fast serial data Din to be written continuously, as denoted by 2 t .

Since the count values of the CLK counter 18 are counted for counting the CLK and are fed to the R. Req generator 23 via the OR circuit 22 , even during a pause of the R. CLK 2 d , the R. Req can during this Break are generated.

In addition, the RES 2 b is detected and led to the R. Req generator 23 via the OR circuit 22 to generate the R. Req. In this case, the CLK counter 18 is reset with the RES 2 b and it ends the counting after the output of a set count value 2 g . During a time interval in which the CLK counter 18 continues to count, the R counter 17 is caused to stop counting, thereby providing an R counter output as indicated at 2 h . With the CLK counter output signal 2 g , the R counter output signal 2 h and RES 2 b , which are fed to the R. Req generator 23 , the R. Req is generated immediately after the RES 2 b subsequently generated by the output signal 2 g from the CLK counter 18 and then generated by the cyclical output signal 2 h from the R counter 17 , as denoted by 2 i . As a result, immediately after the RES 2 b , the R cycle as designated 20 is assigned, and this R cycle causes data at an address value of, for example, (0) R from the memory count field 5 into the Output buffer register 6 are read. Then the data is transferred to the RES converter 7 in response to the R. load signal 2 q and, as denoted by 2 s , the data are given to the address value (0) R in roughly temporal relationship with the count value 2 g of the CLK Counter 18 . This ensures that data at the initialized address value can be obtained more quickly and a memory that can be handled more easily is thus created.

FIG. 3 is a timing chart explaining another example operation of the image memory shown in FIG. 1. In FIG. 3, signals denoted by 3 a to 3 t are identical to the signals 2 a to 2 t in FIG. 2.

The operation shown in FIG. 3 differs from the operation shown in FIG. 2 in that the clock pause duration on the CGR 3 c and CGW 3 e is longer than that on the CGR 2 c and CGW 2 e , and in that they are identical to one another are. The R. CLK 3 d and W. CLK 3 f are therefore generated simultaneously after the generation of the CLK counter output signal 3 g , as can be seen from FIG. 3.

By selecting the CGR 3 c and CGW 3 e in this way, the Dout 3 s and Din 3 t can be addressed with the same timing as shown in FIG. 3 and data that is used as Din during the delivery of the data Dout, for example at a Address (1) R can be entered, can be written into an address (1) W. Accordingly, by using the memory output of this embodiment as an input to the subsequent step memory, for example, data subject to a doubled amount of delay can be easily obtained. Then the R. CLK 3 d is generated as designated 3 s and data can be delivered sequentially, starting with the initialized address (0) R. This can be conveniently applied to an example in which write and read operations are stopped during the blanking period of the image signals to improve the efficiency of use of the storage capacity because data at other addresses is protected from being released can.

If the CLK 3 a is executed by using the CGR 2 c or CGW 2 e , the R. Req 3 i or W. Req 3 j generation cycle can be increased and the R cycle or the W cycle can be applied to the cycle signal 30 are assigned to an increased cycle, with the result that individual data in the Dout 3 c can be thin-out or individual data in the Din 3 t can be thinned out. This effect can easily be brought about and is not described in more detail here. It is therefore seen from the above that reading an enlarged image from the memory and writing a reduced image to the memory can be easily accomplished in accordance with the teachings of the present invention.

Referring to FIG. 1, an R. Req timing generator includes an R control circuit 15 , an R counter 17 , a CLK counter 18 , an OR circuit 22, and an R. Req generator 23 as by one dashed line block shown; a W-Req timing generator includes a W control circuit 16 , a W counter 19, and W-Req generator 24 ; and a REF. Req timing generator includes the REF counter 20 and the REF. Req generator 25 . An exemplary hardware construction of each of the above Req timing generators will now be described.

The Req timing generators, each of which is specifically constructed as explained in FIGS . 4 to 6, operate according to a timing diagram as shown in FIG. 7.

With reference to FIGS. 4 to 6, there can be seen input connections 50 to 53 for the CLK, CGR, RES and CGW, output connections 54 to 56 for the R. Req, W. Req and REF. Ref., Counters 60 to 75 , D-type flip-flops 80 to 83 , inverters 90 to 100 , NAND circuits 110 to 118 , and AND circuits 120 to 124 , respectively. The R counter 17 and CLK counter 18 are exemplified by dashed line blocks in Fig. 4, the W counter 19 is represented by a dashed line block in Fig. 5, and the REF counter 20 is represented by a block 6. place a dashed line in Fig. in the time diagram of Fig. 7 7 a which occur to 7 v waveforms constitute the essential points of Fig. 4 to Fig. 6. The operation of the circuit shown in Fig. 4 will first be explained. In Fig. 4, the CLK of port 15 is shown by 7 a , the RES of port 52 by 7 b , the CGR of port 51 by 7 c , the R. CLK, the passage of the CLK 7 a with the CGR 7 c on the AND circuit 127 , by 7 d , and a decoding pulse, which is obtained at the output of the NAND circuit 112 by NAND connection of the Q output signals of the counters 60 to 63 , by 7 e . The CLK counter 17 may only perform the counting operation while the decoding pulse 7 e is "high". Conversely, while both the RES 7 b and the output signal 7 e of the NAND circuit 112 "high", the counting operation of the R-counter 18 stops, a carrier output Co from the counter 63 is represented by 7 f, a Q₁ output signal, which is obtained by latching on the flip-flop 80 of the D type of a logical sum of the RES 7 b and the carrier output signal 7 f of the CLK counter 17 , represented by 7 g , an output signal for example of the NAND circuit 111 for the NAND connection of the Q₁ output signal 7 g and the CLK 7 a , is represented by 7 h , a carrier output signal of the R counter 18 is represented by 7 i , output signals which are equally from the Q₂ Output and the NAND circuit 114 are obtained by 7 j and 7 k , and the R. Req, which is formed by AND connection of 7 h and 7 k , by 71 .

The W. Req is generated as described below. With reference to FIG. 5, the CLK 7 a and RES 7 b are the same as those shown in FIG. 4, the CGW of connection 53 is represented by 7 o , the W. CLK which results from the passage of the CLK 7 a with the CGW 7 o on the AND circuit 122 arises, by 7 p , a carrier output signal of the W counter 19 by 7 q , a Q₃ output signal, which by holding the carrier output signal 7 q on the flip-flop 82 from D -Type is obtained by 7 r , and the W. Req, obtained for example by AND connection of the Q₃ output signal 7 r and an inverted signal of the CLK 7 a , by 7 s .

The operation for generating the REF. Req will now be described. Referring to FIG. 6, the CLK 7 a and RES 7 b are the same as those shown in FIG. 4, a carrier output of the counter 75 is represented by 7 t , a Q₄ output signal obtained by holding the carrier output 7 t is obtained from the REF counter 20 by 7 u , and the REF. Req, which is obtained in the same way as in the previous, by 7 % .

Then, an exemplary hardware structure of the cycle generator 10 , which represents the address control unit 26 , will be explained and explained.

An embodiment of the cycle generator 10 , as shown in the diagram of FIG. 8, has an input terminal 150 for receiving the Φ ₀ phase signal obtained by dividing the CLK in frequency at the timing generator 21 , an input terminal 151 for the R. Req, an input port 152 for the W. Req, an input port 153 for the REF. Req, output terminals 154 to 156 for the R cycle signal, W cycle signal and REF cycle signal, flip-flops 157 to 159 of the SR type, inverters 160 and 161 , AND circuit 162 and 163 , flip-flops 164 to 166 D-type, and edge detectors 167 to 169 . FIG. 9 shows a timing chart explaining the operation of the embodiment shown in FIG. 8, and essential parts of the embodiment shown in FIG. 8 operate in accordance with waveforms as shown in FIG. 9. For example, if the R. Req 9 a is input into the SR-type flip-flop 157 , a Q 1 output signal 9 e "high" is set to the Q 2 and Q 3 output signals 9 f and 9 g of the remaining flip Let flops 158 and 159 pass, and only the Q₁ output signal 9 e is led to flip-flops 164 to 166 of the D type, held by Φ ₀ 9 d and output as the R cycle signal 9 h . The edge detector 169 detects a leading edge 9 o of the R cycle signal 9 h , which in turn leads to an R input of a flip-flop of the SR type, thereby resetting the Q 1 output signal 9 e to "low". The remaining cycle signals work in the same way and, as shown in FIG. 9, the respective cycle signals 9 h and 9 j do not overlap with one another. In this case the duration of each cycle signal is set by Φ ₀.

In this way, the R. Req is supplied during the cycle in which the PS converter 7 connected to the output port 2 moves the serial data in response to the R. CLK, the W. Req is supplied during the cycle in which the SP converter 3 connected to the input terminal 1 moves the serial data in response to the W. CLK and the REF. Req is supplied during the renovation cycle for the memory cell array 5 , whereby the very fast serial data can be input and output continuously and simultaneously in the memory.

As is apparent from the foregoing description, using the individual Req timing generators shown in Figs. 4 to 6 and the address generator shown in Fig. 8, can be used in conjunction with that shown in Fig. 1 Embodiment explained operation of the invention can be clearly realized.

A second embodiment of the invention will be described with reference to FIG. 10.

In comparison with the embodiment in Fig. 1, the second embodiment uses an address generator 9 which moves the address data SAD in the form of serial continuous addresses which are determined externally as desired, thereby ensuring that if the serial data Din converted into parallel data in units of, for example, m bits, a random access function can be obtained in units of blocks with m bits. Therefore, the second embodiment is identical to the embodiment of FIG. 1, with the only difference that the address generator 9 and an address control device 26 differ from those of the previous embodiment, and only the address generator 9 and the address control device 26 are therefore described in order to simplify the explanation.

In the second embodiment, the address controller 26 has an R control circuit 15 to pass a CLK with a CGR, an R counter 17 for counting an output signal of the R control circuit, and an R. Req generator 23 , which responds to a count value of the R counter 17 in order to emit a read request signal (R. Req), in the same way a W control circuit 16 is provided in the address control unit 26 for passing the system clock CLK with a CGW, a W Counter 19 for counting an output signal of the W control circuit, and a W. Req generator 24 which responds to a count value of the W counter 19 in order to emit a write request signal (W. Req). Likewise, a REF counter 20 for counting the system clock CLK, which is not subject to passage, and a REF are provided in the address control unit 26 . Req generator 25 , responsive to the count of the REF counter to provide a renovation request signal (REF. Req). The address control unit 26 also has a cycle generator 10 , which the R. Req, W. Req and REF. Req receives these signals to generate control signals for R-cycle, W-cycle and REF-cycle on the time division basis, and a timing generator that divides the system CLK in frequency to provide Φ ₀ to Φ _n . At the timing of the R cycle, the cycle generator 10 supplies the address generator 9 with a read address selection signal (here referred to as SEL.R), a read hold signal (here referred to as R.L.) and a read register selection signal ( referred to here as R. SEL). Likewise, when the write cycle is timed, the cycle generator 10 gives a write address selection (referred to here as SEL. W), a write hold signal (referred to here as W. L), and a write register selection signal (here referred to as W. SEL denotes), and at the time of the REF cycle, it outputs a renovation hold signal (REF. L) and a renovation register selection signal (REF. SEL).

As in the case of the embodiment of FIG. 1, the R. CLK and W. CLK signals are also applied to the PS converter 7 and SP converter 3 , respectively, and the R. load signal from the R. Req generator 20 and the W. load signal from the W. Req generator 24 are applied to the PS converter 7 and the input register 4 , respectively.

The address generator 9 will now be described. The address generator 9 has an input terminal 27 for the SAD, an input terminal 28 which is designed to receive an SAD pulse signal (strobe) (here referred to as SAS) which is used for moving the SAD, and an input terminal 29 , which is configured to receive a transmit / address pulse signal (strobe) (here referred to as TAS) for determining a timing at which the externally supplied SAD and SAS are converted into parallel addresses and the parallel addresses to an R register 34 or to a W register 35 of the subsequent stage to be described later, wherein the SAD, SAS and TAS signal are routed to a serial address data register 30 (here referred to as SAD reg). In addition to the read address register (R register) 34 and the write address register (W register) 35 , a renovation address register (REF register) 36 is provided. The outputs of registers 34, 35 and 36 are coupled to a selector switch 37 which is assigned to R. SEL, W. SEL and REF. SEL signals respond to selectively indicate one of the values stored in the three registers 34 , 35 and 36 . The output selection switch 37 is coupled to the subsequent stage of a memory address register 38 , which stores an optionally output address and outputs it in accordance with a timing signal Φ _m , which is emitted by the timing generator 21 . An output signal of the memory address register 38 is supplied in parallel to the address decoder 8 and an increment register 33 . An address value input to the increment register 33 is incremented and supplied to a first and second input selector switch 31 and 32 . The first and second input selector switches also receive a read address (R. Addr) and a write address (W. Addr) from the SAD reg. The first input selector 31 selects data from the SAD reg 30 and feeds it to the R register 34 when the SEL. R, which is sent by the address controller 26 , is "high", selects an output value of the increment register 33 and feeds it to the R register 34 when the SEL. R is "low". Similarly, the second input selector 32 selects data from the SAD reg 30 and feeds it to the W register 35 when the SEL. W from the address controller 26 is "high", selects an output value of the increment register 33 and feeds it to the W register 35 when the SEL. R is "low". The REF register 36 is continuously supplied with an output value of the increment register 33 . The R register 34 is responsive to the latch signal R. L to move the address selected by the first input selector 31 and the W register 35 is responsive to the latch signal W. L to address the address move selected by the second input selector switch 32 .

The operation of the embodiment shown in FIG. 10 will now be described with reference to a timing chart of FIG. 11.

In Fig. 11, the CLK, which is applied to the terminal 14 , by 11 a , and a setting signal SET, which is generated on the basis of the SAD, SAS and TAS, which are applied to the terminals 27 to 29 , is through 11 b shown. The SET 11 b forces the R. Req generator 23 to generate the R. Req signal 11 c synchronously with the CLK 11 a . The R-W-counter 17 and counter 19 are set to initial values as well forcibly b by the SET. 11 In the example of FIG. 11, the two counters 17 and 19 and the REF counter 20 operate at the rate of a count cycle of 18 clock pulses, and the number of bits that are subject to both SF and PS conversion will also elected to 18 .

The Req generators 23 to 25 generate the Req signals 11 c to 11 e in synchronism with the count cycle of the counters 17 and 19 . One of the signals obtained by 1 / K frequency division of the CLK at the timing generator 21 is shown by 11 f . When K = 6, six signals Φ ₀ to Φ ₅ can be generated which are out of phase with each other, and 11 f represents a signal Φ ₀ from them. A cycle signal is represented by 11 g , in which, for example, its first appearance a cycle of Φ ₀ 11 f , followed by the generation of each of the Req signals 11 c to 11 e , is assigned to each of the different cycles. However, in the event when, for example, the R cycle and the W cycle occur simultaneously, the timing in the cycle generator 11 can be set to prioritize so that the R cycle has a preference over the W cycle and therefore the W cycle is generated after the R cycle, ensuring that the individual cycles can be assigned based on time division so that they do not occur simultaneously. An R. SEL signal 11 h is shown, which is generated at the timing of Φ ₁ phase for the R cycle and is led to the input selector switch 37 . When the input selector 37 responds to the R. SEL 11 h , it selects the output of the R register 34 , among the registers 34 through 36 , and supplies the selected signal to the memory address register 38 . Although not shown, the W. SEL signal is generated during the W cycle and the REF. SEL signal is generated during the REF cycle in a similar manner, and the output of one of registers 34 through 36 is selected according to one of the SEL signals to be fed to the memory address register. The hold pulse signal for moving the output data of each of the registers 34 to 36 into the memory address register 38 is represented by 11 i , and the memory address data which is moved into the memory address register 38 by the hold pulse signal 11 i is represented by 11 j shown. The memory address data signal 11 j is supplied to the address decoder 8 and the increment circuit 33 . In the memory address data signal 11 j , (K) R represents an R address (more specifically, R address data) of an address value of K, (K) W represents a W address (more specifically, W address data) of an address value of K , and (K) REF represents a REF address (more specifically, REF address data) of an address value of K. With 11 k and 11 l are the SEL signal and the SEL. W signal shown, which are respectively led to the first and second selector switches 31 and 32 . For example, during the SEL. R is "high", a desired designated address is selected from the SAD register 30 and passed to the R register 34 and during the SEL. R is "low", an incremented address value is selected by the increment circuit 33 and fed to the R register 34 . In the same way, during the SEL. W is "high", an address designated as desired is selected by the SAD register 30 and passed to the W register 35 and during the SEL. W is "low", an incremented address value is selected by the increment circuit 33 and led to the W register 35 . The hold pulse signals for registers 34 through 36 are represented by 11 o , 11 p and 11 q and are generated at a timing of, for example, Φ ₄ phase for each cycle to cause each of registers 34 to 36 to either the incremented address on the increment circuit 33 or the address designated as desired. The address data signals, which are thus fed to the R register 34 , W register 35 and REF register 36 , are represented by 11 r , 11 s and 11 t . For example, in the signal 11 r (N) R is an R address designated as desired which is passed from the SAD register 30 to the R register 34 and ( N +1) R is an R address which is generated by incrementing an R address value designated as desired is obtained on the increment circuit 33 .

As is apparent from the above operation of the address generator 9 , when the number m of the parallel bits subjected to the SP conversion is 18 , for example, the count of the R counter 17 also becomes 18 , thereby inputting bits of the serial data Din 11 u , after SET 11 b is written sequentially, in units of blocks of 18 bits during the W address periods of the memory address signal 11 j , namely in the memory cell field 5 for sequential write addresses which are designated with a write address designated as desired ( Start N) W and start with ( N +1) W, ( N +2) W. . . Continue. In addition, when the count cycle of the W counter 19 is also selected to be 18 , data through an output buffer register 6 from the memory cell array 15 in units of blocks of 18 bits during the R address periods of the memory address signal 11 j read. Then bits of the serial data Dout 11 v , which follow the SET 11 b and two blocks are released sequentially, from write addresses starting with a read address (N) R designated as desired and continuing with ( N +1) R, ( N +2) R. . . In this case, since there is a time difference of two blocks between the serial data Din denoted by (N) W and the serial data Dout denoted by (N) R, it is possible to determine the amount of delay of the Dout by the RES signal when the address value is shifted two blocks between, for example, the (N) W and the (N) R, and therefore this amount of delay can be easily adjusted exactly according to a field or a frame.

As described above, in the present embodiment, by selecting the sum of the clock pulses for both the R cycle, W cycle, and the REF cycle in the address generator 9, smaller than the number m of bits required for the SP conversion 11, that is to say by selecting six clock pulses for each cycle in the example in FIG. 11, the very fast serial data Din can be written to the bit memory and the very fast serial data Dout can be read, and random access (random accessing ) can be guaranteed in units of blocks by designation of the SAD, whereby multifunctional requirements are met.

Another example of the embodiment shown in Fig. 10 is illustrated in Fig. 12. In the example of Fig. 12, the phases of the latch pulse signals for latching the selector switches 31, 32 and 37 and the registers 34 to 36 and 38 are the same are associated with individual cycles in a cycle signal 12 g , different from those of the latching pulse signals in the example of Fig. 11. Accordingly, in contrast to the example in Fig. 11, in which the serial data Dout 11 v corresponding to the SET 11 b follow, and two blocks are given, starting with the read address (N) R designated as desired, given in the example of FIG. 11, the data 12 v following SET 12 b and one block are given , starting with the read address (N) R designated as desired. This will now be described further.

Referring to FIG. 11, the signals 12 a to 12 v correspond to the signals 11 a to 11 v in FIG. 11, but the signals 12 h to 12 v occur in timings different from those for the signals 11 h to 11 v are. In particular, the R register 34 and the W register 35 are operated by the signals 12 k to 12 t at different times, like that of the signals 11 k to 11 t , and this will be described first. A part of the cycle generator 11 , which when generating the SEL. K 12 k and the hold pulse signal (R. L) 12 o for the R register 34 is specifically explained in FIG. 13. A timing chart for an operation of the circuit shown in FIG. 13 is explained in FIG. 14. With reference to Fig. 13, input connections for the clock signals of different phases Φ ₅, Φ ₂ and Φ ₁ are shown with 170, 171 and 175 , input connections for an R. Req 14 b represented by 172 , an input connection for a SET 14 a by 173 , an input terminal for an R cycle signal 14 e represented by 174 , output terminals for a hold pulse signal 14 o of the R register 34 or a SEL. R 14 h represented by 176 and 177 , flip-flops represented by 178 and 179 , AND circles represented by 180 to 183 , and an OR circuit represented by 184 . If the SET 14 a is entered, a Q₁ output signal 14 c of the flip-flop 178 is set to "high", and then "low" by the R. Req 14 b , which is subsequently entered, whereby the flip-flop 179 of the subsequent stage is caused to generate its Q₂ output signal 14 d , as explained in Fig. 14. The Q₂ output signal 14 d and the R cycle signal 14 e are AND-connected to provide a signal N ₁ (R) 14 f , and the N ₁ (R) 14 f and a Φ ₁ signal 14 g are AND -connected to the SEL. R 12 h to deliver, which is used to select an R address designated as desired after the SET. The R. Req 14 b and a Φ ₅ signal 14 k are ANDed together to provide a signal N ₃ (R) 14 l , which is used as a hold pulse signal, which is normally data from the increment circuit 30 in the R register 34 moves. The latch pulse signal N ₁ (R) 14 f and a Φ ₂ 14 i are ANDed to provide a signal N ₂ (R) 14 j , which is used as the latch pulse signal, which is designated R- as desired Address data moved into the R register 34 . The two signals N ₂ (R) 14 j and N ₃ (R) 14 b are OR-connected to provide the signal 14 o , which is supplied to the R register 34 as the hold pulse signal. In contrast, the SEL. W 12 l and the hold pulse signal 12 p for the W register 35 in FIG. 12 are generated by a generator which is similar to that of the circuit in FIG. 13. But to create the SEL. W 12 l and the hold pulse signal 12 p , the R. Req 14 b and the R cycle signal 14 e are each replaced by a W. Req 14 p and a W cycle signal 14 s , and the two flip-flops 178 and 179 generate their Q₁ (W) signal 14 q or Q₂ (W) signal 14 r . The Q₂ (W) signal 14 r and the W cycle signal 14 s are AND-connected to provide a signal N ₁ (W) 14 t . The signal N ₁ (W) 14 t and the signal Φ ₁ 14 g are AND-connected to a signal SEL. W 14 u to deliver, which is fed to the second input selector switch 32 . The same as the hold pulse signal 14 o for the R register 34 is a hold pulse signal 14 v for the W register 35 from the signals N ₁ (W) 14 t , W. Req 14 p , Φ ₂ 14 i and Φ ₅ 14k recovered.

Through the above operation, the address data signals, as shown by 12 r to 12 t, can be stored in the registers 34 to 36 , whereby, especially during the first occurrence of the R cycle period after the SET 12 b, an address designated as desired ( N) R can be moved into the R register 34 , and the moved (N) R can be selected by the R. SEL 12 h which is input as the address signal 12 j into the memory address register 38 in response to the latch pulse signal 12 i is then fed as R address data into the address decoder 8 and to the increment circuit 33 to be incremented in the address value, and finally moved back into the R register 34 . In this way, data of an address designated as desired can be read out from the memory cell array one block earlier than that of the example of Fig. 11 and can also be output in the form of serial data Dout one block earlier than explained in FIG. 12.

In this case, by providing a one-block shift between address values of the (N) W and (N) R address values of Din and Dout at the same time, the adjustment of the amount of delay of the Dout due to the RES 12 b is facilitated.

When the W. CLK is passed with the CGW in the embodiment 10 , an operation follows as described with reference to FIG. 15.

In Fig. 15, a CLK with 15 a is shown, the CGW 15 b, the W. CLK obtained by, for example, AND-connection of the CGW 15 b and CLK 15 a at the W control circuit 16 in Fig. 10, 15 c is shown, an RES is represented by 15 d , an R. Req is represented by 15 e , a W. Req is shown in 15 f and REF. Req is shown with 15 q . In this example, the CLK is not let through with the CGR and the R. CLK is identical to the CLK 15 a . Accordingly, the R. Req 15 e and the REF. Req 15 g is identical to that of the example in FIG. 12 and the W. Req signal 15 f is obtained at a rate of, for example, 18 clock pulses from the W. CLK 15 c , which follows the RES 15 d . Therefore, the generation time of the W. Req 15 f is delayed compared to the example of FIG. 12. In this case, in response to a phase signal Φ ₀ 15 h , an address cycle signal 15 i is generated from individual address cycles. A generator of the address cycle signal 15 i is shown in FIG. 16 and its exemplary operation is explained in FIG. 17. With reference to FIG. 16, input connections for a signal Φ ₀ 17 d , an R. Req 17 a , are one W. Req 17 b and a REF. Req 17 c , as shown in FIG. 17, each represented by 185 to 188 , output connections for an R cycle signal 17 h , a W cycle signal 17 i and a REF cycle signal 17 j are each represented by 189 to 191 . Set / reset flip-flops (referred to here as SRFF) are designated 191 to 193 , inverters represented by 194 and 195 , AND circuits represented by 196 and 197 , D-type flip-flops (referred to here as DEF's) by 198 to 200 shown, and edge detector (edge) represented by 201 to 203 . The SRFF 191 to 193 respond to Req signal 17 a to 17 c to produce their Q₁, Q₂ and Q₃ output signals 17 e to 17 g . The priority among the Q₁ to Q₃ output signals is set by the inverters 194 and 195 and AND circuits 196 and 197 , so that the Q₁, Q₂ and Q₃ output signals are graded in this order. The Q₁, Q₂ and Q₃ output signals so graded are fed to the D inputs of the DFFs 198 to 200 . Each D input signal is held by the Φ signal 17 d on each of the DFFs 198 to 200 in order to provide the R cycle signal 17 h , a W cycle signal 17 i and a REF cycle signal 17 j at their Q outputs. The edge detectors 201 to 203 detect, for example, rising edges of the cycle signals 17 h, 17 j, and edge signals 17 k to 17 o, which are thus detected are jweils led to reset inputs of the SRFF 191 to 193 to their reset Q outputs, thereby new Req Signals are moved. By setting up the cycle generator 10 constructed as above, the individual cycle signals can be allocated on the basis of the time division without interfering with one another on the time axis. By assigning the cycles for the addresses on a time-sharing basis in this way, the W. SEL 15 j , by latch pulse signal 15 k for the memory address register 38 , SEL. R 15 o , the SEL. W 15 p and hold pulse signal 15 g and 15 r for the R register 34 and W register 35 as shown in Fig. 15 are obtained, and by using these control signals, address values of the memory address register 38 , R- Register 34 and W register 35 can be obtained as shown by 15 l , 15 s and 15 t . In this case, data Din 15 u , which are entered serially after the RES 15 d , are written in units of 18 bits synchronously with the W. CLK 15 c in the memory cell field 5 , for example at an address designated as desired ( N) W corresponding to (N) W in the address signal 15 1 from the memory address register 38 and matching, and serial output data Dout 15 v belonging to an address (N) R designated as desired also become given after a block. As is clear from the above, by using the W. CLK 15 c as desired, passed with the CGW signal 15 b and CGR signal and the R. CLK, continuous writing of the Din 15 u and continuous reading of the Dout can be ensured without causing difficulties, such as. B. Failure to write the Din to be moved and failure to read the Dout to be issued.

Fig. 18 explains a modification of the embodiment in Fig. 10. The modification in Fig. 18 is such that the addresses designated as desired by the SAD register 30 , together with address data from the registers 34 to 36 are selected at a time by means of a selector switch 80 . The operation of the modification of FIG. 18 will be briefly described with reference to FIG. 9, which explains a timing chart for this modification.

The components shown in FIG. 18 are identical to those of the embodiment in FIG. 10, with the exception of the selector switch 80 . Referring to Fig. 19, a CLK is designated 19 a , a SET 19 b , an R. Req 19 c , a Φ ₀ signal with 19 d , and a cycle signal for assigning cycles with 19 e , the above Signals are identical to those of the timing diagram in FIG. 12. Selection control signals are denoted by 19 f to 19 j , which are passed from the timing generator 26 to the selector switch 18 . For example, an R address designated as desired is selected by the SAD register 30 when the SEL. R 19 f is "high", a W address from the SAD register 30 designated as desired is selected when the SEL. W 19 g is "high", an R address from the R register 34 is selected when the R. SEL 19 h is "high", and a REF address from the REF register 36 is selected when the REF . SEL 19 j is "high" with each of the signals selected as above moved into the memory address register 38 at the timing of the latch pulse signal 19 k . Address values which are moved into the memory address register 38 are denoted in the case of an address signal 19 l , and 19 o to 19 g denote hold pulse signals for moving the address values, which increments in the registers 34 to 36 in the increment circuit 33 are. Address data signals as designated 19 r to 19 t are moved to registers 34 to 36 . Through the above operation, as in the case of the operation shown in Fig. 12, the moving of the serial data Din 19 u and the output of the serial data Dout 19 v can be done by freely designating an address.

With FIG. 20, a third embodiment of the image memory will be described. This embodiment differs from the first embodiment shown in Fig. 1 in that it intends to process data in parallel in units of 2 ⁿ bits ( n a natural number). Accordingly, the SP converter 3 is equipped so that it carries out a serial / parallel conversion of 2 ⁿ bits of the data, the PS converter 7 is designed such that it carries out parallel / serial conversion of 2 ⁿ bits of the data executes, and a memory cell array 5 has a structure ( K × 2 ⁿ ) columns × m rows, where K and m are natural numbers. The address generator 9 , address decoder 8 , input buffer register 4 and output buffer register 6 have the same structure as the corresponding components of the first embodiment and are not described separately. An address controller 26 'of this embodiment has the function of initializing the W address and R address in addition to the function of the address controller 26 of the first embodiment, and will be described in more detail below.

The address controller 26 ' has an input terminal 11' for a write reset signal (W. RES), an input terminal 16 for a write clock signal (W. CLK), an input terminal 14 for a system clock signal (CLK), one Input terminal 11 for a read reset signal (R. RES), and an input terminal 15 for a read clock signal (R. CLK). A W counter 19 is connected to the terminals 11 ' and 16 to be supplied with the W. RES and CLK signals.

With the output of the W counter 19 , a W. Req generator 24 and a W. charging generator 24 'are connected, which respond to a count of the W counter 19 to a W. Req signal or W. charging signal to create.

A REF counter 20 is operable to count the system clock signal CLK and a REF. Req generator 25 , which is connected to the output of the REF counter 20 , responds to a count value of the REF counter 20 by a REF. Generate Req signal.

An R counter 17 , which is connected to the terminals 11 and 15 , is supplied with the R. RES and R. CLK signals. Connected to the output of the R counter 17 are an R. Req generator 23 and an R. charging generator 23 ' , which respond to a count of the R counter 17 to an R-charging signal and an R-Req signal produce.

The W. Req, REF. Req and R. Req signals are fed to a cycle generator 10 and the cycle generator 10 generates W cycle, REF cycle and R cycle signals which are output to the address generator 9 on a time division basis.

A timing generator 21 is also provided, which divides the system clock signal CLK in frequency in order to generate Φ ₀ to Φ _n phase clock signals.

In the address control unit 26 ' , the W counter 19 can be reset with the W. RES signal and the R counter 17 can be reset with the R. RES signal, these reset signals also being applied to the address generator 9 .

As in the case of the embodiment in Fig. 1, the W. CLK signal is also applied to the SP converter 3 , the R. CLK signal is also applied to the PS converter 7 , the W. load signal to the input buffer register 4 applied and the R. load signal applied to the PS converter 7 .

In this embodiment in particular, the count value of the W counter 19 and of the R counter 17 is selected such that it coincides with the amount 2 ^{n of} the bit conversion in the SP converter 3 and PS converter 7 .

The operation of the embodiment in FIG. 20 will now be described with reference to a timing diagram of FIG. 21.

In the timing chart of FIG. 21, a normal operation is shown, where n = 4 and no W. R. RES and RES signals from the terminal 11 'and 11, as indicated at 21 b and 22 j in FIG. 21, input will.

In FIG. 21, REF, W and R in an address signal 21 p represent a renovation address (REF address), or a write address (W address) and a read address (R address), and M, K and L in brackets are natural numbers that show the values of the respective addresses. Thus, (M) REF indicates that the renovation address has a value of M , (K) W indicates that the write address has a value of K , and (L) R indicates that the read address has a value of L. Likewise in FIG. 21 , * W in a data signal 21 q represents a write address (W address) into which 16 bits 0 to 15 of input data in the data signal 21 q are written, and * R in a data signal 21 r represents a read address ( R address), from which 16 bits 0 to 15 of output data are read, a value in brackets inserted between the * and the W as well as between the * and the R representing an address value.

Referring to Fig. 21, when the input 21 a designated W. CLK from the Ansch 23702 00070 552 001000280000000200012000285912359100040 0002003739423 00004 23583luß 16, generates the W-counter 19 having the count value 2⁴, an output pulse signal 21 c in a duration of 16 counts of the W. CLK 21 a . In the same way, the W. charging generator 24 ' generates the output signal W. loading signal 21 d with a duration of 16 counting steps and the W. Req generator 24 generates the output signal W. Req 21 e with a duration of 16 counting steps. Accordingly, the SP converter 3 , which responds to the W. load signal 21 d , transmits the input data signal Din 21 q to the input buffer register 4 in units of 16 bits 0 to 15 as explained. The generator 10 responds to the W. Req 21 e to assign W cycles to the cycle signal 21 o , and the address generator 9 , which responds to the W cycle signals, generates W addresses, such as. B. (K) W, (K +1) W. . . as shown in the address signal 21 p , which in turn are led to the memory cell array 5 via the address decoder 8 . In response to a W address, parallel data is transferred from the input buffer register 4 to the memory cell array 5 in units of 16 bits. Accordingly, the input data Din 21 q are transmitted from the terminal 1 in units of 16 bits to the memory cells of the memory cell array 5 , which are identified by W addresses, such as. B. * (K) W, * (K +1) W, * (K +2) W. . . be designated.

In contrast, the R counter 17 , which has the count value 2 an, responds to the R. CLK 21 i , which is input from the terminal 15 , by an output pulse signal 21 k for a duration of 16 counting steps of the R. CLK 21 i to create. In the same way, the R. charging generator 23 ' generates the R. charging signal 21 l with a duration of 16 counting steps and the R. Req generator generates the R. Req 21 m with a duration of 16 counting steps. Then the cycle generator 10 responds to the R. Req 21 m to assign R cycles to the cycle signal 21 o , and the address generator 9 , which responds to R cycle signals, generates R addresses such as e.g. B. (L) R, (L +1) R. . . , as shown in the address signal 21 p , which in turn is passed to the memory cell array 5 via the address decoder 8 , which causes 16 bits of the parallel data, corresponding to an R address, from the memory cell array 5 to the output buffer register 6 are transmitted. The PS converter 7 then responds to the R load signal 21 1 to move the 16 bits of the parallel data that are transferred to the output buffer register 6 . In this case, the data is transferred to the PS converter 7 , in units of 16 bits, as shown in the output data signal 21 r , from memory cells of the memory cell array 5 which are associated with R addresses such as e.g. B. * (L -1) R, * (L) R. . . and are converted by the PS converter 7 , which responds to R-CLK, into serial data, which are output as Dout to the terminal 2 .

The cycle assignment operation by the cycle generator 10 will be described in more detail. A comparison of the entered W. Req 21 e , R. Req 21 m and REF. Req 21 h with the cycles assigned to the cycle signal 21 o clearly shows that the cycles are assigned according to a sequence of occurrence of the input request signals and that they have the same duration. If the W. Req, R. Req and REF. Req signals are input, for example in this order, the W cycle, the R cycle and REF cycle, which have the same duration, are assigned in this order or order. If the R. Req signal is input while the W cycle is still running, the start of the R cycle is extended until the W cycle is finished.

If the REF. Req is specified while the W cycle is still running, the start of the REF cycle 'is extended until the R cycle is finished, which begins after the W cycle. In this way, the cycle generator 10 allocates each cycle.

As described above, in this embodiment, the SP converter 3 and the PS converter 7 are provided on the input side and output side of the memory cell array 5 , respectively, the W counter 19 and R counter 17 are provided separately and have the count value corresponding to that Amount of BIT conversion in the SP converter 3 and PS converter 7 to count the respective W. CLK 21 a and R. CLK 21 i , the W and R counter output signals 21 c and 21 k are used to To generate the W. Req 21 e and R. Req 21 m that occur on the talc period according to the amount of BIT conversion, the W. Req and R. Req signals 21 e and 21 m are used to time-sharing cycles Allocate, and according to the respective cycles, the data transfer between the memory cell array 5 and both input and output buffer registers 4 and 6 and the data transfer between the input buffer register 4 and the SP converter 3 in response to the W load signal 21 d as well as the output buffer register r 6 and the PS converter 7 , executed in response to the R load signal 21 l , which enables simultaneous writing / reading of the serial data Din 21 q and Dout 21 r with respect to the image memory.

By selecting the amount of the BIT conversion in the SP converter 3 and PS converter 7 between 1 and 2 ⁿ ( n is a natural number), the switching structure of the counters 15 and 17 can be simplified.

Further in the embodiment of FIG. 20, the CLK 21 f is different from the W. CLK 21 a and the R. CLK 21 i is used as the input signal of the REF counter 20 and this REF counter 20 responds to the CLK 21 f and generates an output signal 21 g , which is used to the REF. Generate Req and REF cycle signals in the same manner as described above, the REF cycle signal generating the REF addresses on a time division basis which is fed to the memory cell array 5 to complete the renovation operation for the memory cell array.

The timing generator 21 divides the CLK 21 f in frequency by, for example, 1/5 in order to generate the signals Φ ₀ to Φ ₄ which are out of phase with respect to one another by a period of the CLK 21 f , one of these output signals being explained by way of example as the signal Φ ₀ 21 n in Fig. 21.

Another example of the operation of the embodiment in FIG. 20 will be explained with reference to a timing chart of FIG. 22.

In FIG. 22, n has the same value as in the example of FIG. 21 and signals 22 a and 22 r corresponding to signals 21 a to 21 r in FIG. 21. In contrast to the example in FIG. 21, where neither W. RES 21 a that R. RES 21 j still occurs, one of W. RES 22 a and R. RES 22 j occurs, for example, R. RES 22 j in FIG. 22. In response to the R. RES 22 j , the R counter 17 and the R address in the address generator 9 are reset. As a result, the phases of the R counter output signal 22 k and R. load signal 22 l , which occur during the duration of the 16 counting steps of the R. CLK, are initialized, as explained in FIG. 22. The R. Req 22 m is initialized in the same way, but it can occur in synchronism with the R. RES 22 j by leading the R. RES 22 j to the R. Req generator 23 . The value of the R address in the address generator 9 is also initialized. Thus, the R. RES 22 j assigns the individual cycle signals as indicated at 22 o and individual addresses are assigned on a time division basis as shown at 22 p .

In particular, in this example, an address value assigned by the R. Req 22 m in synchronism with the R. RES 22 j is initialized (0) R as described above , and then R addresses (1) R, (2nd ) R. . . given sequentially. According to an R address value, the data signal Dout is output as shown at 22 r . For example, with the initialized address * (0) R, the data are output, starting with the seventh counting step of the R. CLK 22 i after entering the R. RES 22 j . In the data preceding the occurrence of the initialized address * (0) R, 16 bits of data corresponding to the previous address * ( L -1) R are sequentially output as explained, and the last sixteenth bit is retained.

In this way, by providing means (not shown) for externally designating the R. RES 22 j and resetting the R counter 17 with the R. RES 22 j to initialize the address, it is possible to obtain a pulse number R. To designate CLK, which occurs after the R. RES 22 j is entered and at which data the initialized address (for example * (0) R) is output. Furthermore, by resetting the R counter 17 with the R. RES 22 j to initialize the phase of the period in which the R load signal 22 1 and R. Req 22 m are generated, transmission of new parallel data from the output buffer register to the PS converter 7 is prevented during a time interval in which data of the initialized R address (* (0) R) which occurs after the input of the R. RES 22 j is led to the output connection, whereby during a time interval in which 16 bits of data, for example, * ( L -1) R address, as denoted by 22 r , are sequentially delivered, and hence the subsequent data of the * (0) R address, and the last one Bit of the * ( L -1) R address data can be held. By entering the R. RES 22 j during a time interval in which the amplitude of the image signal does not change, for example during the flyback period, the flyback period can be maintained to avoid a disadvantage due to loss of bits of the output data Dout.

When the frame buffer containing an input stage of the SP converter and an output stage of the PS converter, each having the amount of the BIT conversion, which is between 1 to 2 ^n, is generally used to obtain a field delay which results in a delay of 262 or 263 lines or a frame stroke delay which results in a delay of 525 lines, one line corresponds to 910 clock pulses if the clock frequency is chosen to be four times the chrominance carrier frequency fsc, and thus the delay of 262, 263 or 525 lines cannot be fully divided by 2 ⁿ , leaving a remainder responsible for data loss. According to the following embodiment, such a disadvantage due to data loss can be eliminated by the operation described above.

Another example of the operation of the embodiment in FIG. 20 will be described with reference to a timing chart of FIG. 23.

In FIG. 23, n has the same value as in the example in FIG. 21 and the signals 23 a to 23 r correspond to the signals 21 a to 21 r in FIG. 21. In contrast to the example in FIG. 21 or FIG. 22 both R. RES 23 k and W. RES 23 b occur in the example of FIG. 23. In response to the R. RES 23 j , the signal 23 k generated by the R counter, the R. load signal 23 l and the R. Req 23 m act in such a way that they assign the R address and the Dout 23 r in the same manner as in the example of FIG. 22. In contrast, when the W counter 19 is reset in response to the W. RES 23 b , the periods at which the W counter output signal 23 c , W. load signal 23 b and W. Req signal 23 e are generated , initialized by the W. RES 23 b , as explained in FIG. 23. the W. Req 23 e is therefore generated starting with, for example, the seventeenth counting step of the W. CLK 23 a , namely after the W. RES 23 b has been entered . The value of the W address in the address generator 9 is also initialized with the W. RES 23 b . Thus, the individual W cycle signals are assigned as indicated at 23 o and individual W addresses are assigned as shown at 23 b . As a result, 16 bits in units of, for example, the serial data Din are written sequentially into the memory cell field 5 after input of the W. RES 23 b at W addresses that begin with the initialized W address * (0) W and begin with * ( 1) W, * (2) W. . . Continue. Accordingly, by using the W. RES 23 b, it is possible to specify which bits of the Din are to be written into the memory cell field 5 at the initialized address. By using the W. RES 23 b and R. RES 23 j , the delay time for the data can be set outside of the memory as desired.

The W counter 19 , the W. charge generator 24 ' and W. Req generator 24 used in the embodiment in FIG. 20 may be specifically constructed as shown in FIG. 24, and the R counter 17 , the R. charge generator 23 ' and the R. Req generator 23 used in the embodiment of FIG. 20 may be specifically constructed as shown in FIG. 25.

Referring to FIGS. 24 and 25, reference numerals 204-210 inverter, the numbers from 211 to 218 meters, 219 and 220 flip-flops for holding, 221 and 222 AND circuits, and 223 a NAND circuit, wherein the other elements are the same like those of Fig. 20.

In Fig. 24, the W. CLK from terminal 16 is counted by the 4-bit counters 211 through 214 , and a counter output pulse signal generated at the period of 16 pulses of the W. CLK is latched, for example by the Flip-flop 219 so that the W. Req signal shown in the timing chart of Figs. 21 to 23 can be obtained. The counter output pulse signal is to also generate AND-connected to the W. CLK to the AND gate 221 to the W. load signal shown in the timing chart of Fig. 21 to 23. In the structure of Fig. 24, the W-counter 19 can be reset with the RES W. easily, which is input from the terminal 11 '.

From the above explanation, it can be easily deduced that the R. Req and the R. load signal as shown in FIGS . 21 to 23 can be obtained with the structure of FIG. 25.

FIG. 26 explains a modification of the embodiment in FIG. 20.

In contrast to the embodiment in Fig. 20, in which an ordinary shift register is used as the SP converter 3 , which serves as the input stage to the memory cell array 5 , the serial / parallel conversion of the input data signal Din is performed using two Input buffer registers 104 and 105 effect in this modification. In the same way, the parallel / serial conversion at the output stage is also effected using two output buffer registers 106 and 107 .

The modification of Fig. 26 works as follows:
The input registers 104 and 105 as well as the output registers 106 and 107 of this modification are 2 ⁿ bit registers. This serial data Din from the port 1 is first written continuously by 2 ⁿ bits into, for example, the first input register 104 and then into the second input register 105 . During a time interval in which the subsequent bits are written into the second input register 105 , the 2 ⁿ bits in the first input register 104 are transferred to the memory cell array 5 as parallel data. Subsequently, when all 2 ⁿ bits have been written into the second input register 105 , the writing of the data into the first input register 104 is started again. While the second data is being written into the first input register 104 , the 2 ⁿ bits in the second input register 105 are transferred to the memory cell array 5 as parallel data.

In this way, two groups of bits of the input data signal Din are continuously moved from the terminal 1 into the two input registers 104 and 105 , respectively, and both two input registers can be prevented from moving new bits of the Din before the previous bits which are in the input register has been moved, all have been transferred to memory cell array 5 .

To accomplish this operation, address data from a W counter 19 having the count of 2 ⁿ equal to the W counter in the embodiment of Fig. 20 is decoded by an input register address decoder 102 to sequentially designate which addresses are written in each input register with bits of Din from terminal 1 and the output signal of the W counter 19 is frequency divided by 1/2 by means of a 1/2 frequency divider to provide a signal which is used to indicate to which of the first and second input registers 104 and 105 the data signal Din from terminal 1 is fed and from which of the first and second input registers the data are transferred to the memory cell array 5 .

The two output registers 106 and 107 and an output register address decoder 103 provided in the output stage operate essentially identically to the input registers 104 and 105 and the input register address decoder 102 . Thus, during a time interval in which bits of the data in the first output register 106 are fed as serial data to the terminal 2 , 2 ⁿ bits are transferred as parallel data from the memory cell array 5 to the second register 107 . Subsequently, when the serial conversion of the 2 ⁿ bits of data of the first output register 106 is finished, the serial conversion of the data of the second output register 107 is started and new 2 ⁿ bits of parallel data are transferred from the memory cell array 5 to the first Output register 106 transferred. An output of an R counter 17 for counting the 2 ⁿ is 1/2 frequency divided by a 1/2 frequency divider 101 to provide a signal which is used to add the first and second output registers 106 and 107 switch.

Except for what has just been said, the operation of this modification is the same as that of the embodiment in FIG. 20, providing output data that is exactly the same as that in the embodiment of FIG .

The amount of bit conversion from 1 to 2 ⁿ is expressed as 1 to 16 in the description of the embodiment with reference to FIGS. 20 to 26, but it is not limited to this value and can be, for example, 1 to 8 or 1 to 32 be.

The third embodiment handles data in units of 2 ⁿ bits, and therefore it can be applied to a digital memory for use in a facsimile and the like.

In the previous embodiments, the renovation Signal generation system included because of the  DRAM, which is used as the memory cell, however obviously it can also be omitted if a static memory is used.

Claims (23)

1. Image storage with
a serial / parallel converter ( 3 ) for converting serial input data into parallel data;
a first holding device ( 4 ) for holding the parallel data from the serial / parallel converter;
data storage means ( 5 ) for storing parallel data output from the first holding means;
a second holding device ( 6 ) for holding parallel data which are read out from the data storage device;
a parallel / serial converter ( 7 ) for converting parallel data read out from the second holding device into serial data;
an address generator ( 8 ) for supplying a write address and a read address to the data storage device on a time division basis; and
an address controller ( 26 ) for controlling the address generator. 2. Image memory according to claim 1, wherein the address control device is characterized by
first and second thinning means ( 15; 16 ) for thinning out at least more than two pulses from a master clock signal, the two pulses being different for the first and second thinning means;
first and second counters ( 17; 19 ) for counting clock signals output from each of the two thinning devices;
a third counter ( 18 ) for counting the master clock signal; and
means ( 23 ) responsive to count outputs of the first and third counters to produce a read control signal;
wherein the clock signal generated by the first thinning means in response to a count output from the second counter is used as a clock signal that serially transmits the parallel data moved in the parallel-to-serial converter, and the clock signal, which is generated by the second thinning device is used as a clock signal which transmits the data moved into the serial / parallel converter sequentially to the first holding device. 3. Image memory according to claim 2, characterized in that the address control device further comprises a cycle generator ( 10 ) which receives the read control signal and a write control signal and supplies the address generator with a read cycle and a write cycle which in predetermined preference sequence on a time division basis. 4. Image memory according to claim 2, characterized in that the first counter has the count value equal to that Amount of bit conversion in the serial / parallel converter is set and the second counter is the count value which is equal to the amount of bit conversion in the Parallel / serial converter is set.   5. Image memory according to claim 3, characterized in that the address control device has a fourth counter ( 20 ) which counts the main clock signal and a device ( 25 ) which responds to a count output signal from the fourth counter, and a Renovation signal is generated, the cycle generator receiving the renovation signal to provide the address generator with a read cycle, a write cycle and a renovation cycle that are in a predetermined preferred sequence on a time sharing basis. 6. Image memory according to claim 5, characterized in that the write control signal and the read control signal are generated during a cycle in which the first and the second holding device the parallel Data and then the held parallel data submit. 7. Image memory according to claim 2, characterized in that the generator for the read control signal responsive to the input of a reset signal to to immediately output the read control signal, immediately responsive to the output signal of the third counter, to output the read control signal and then to the cyclic count output from the first counter responds to generate the read control signal. 8. Image memory according to claim 2, characterized in that the count output signal of the first counter with the of the second counter coincides. 9. Image memory according to claim 1, wherein the address generator is characterized by
a desired address register ( 30 ) for moving an externally designated desired address;
a read address register ( 34 ) for storing a read address;
a write address register ( 35 ) for storing a write address;
an output selector switch ( 37 ) for selecting an address in each of the registers and for supplying the selected address;
a memory address register ( 38 ) for storing the address output from the output selector switch and for outputting the address in accordance with a predetermined clock signal;
address increment / decrement means ( 33 ) for receiving the address and outputting an incremented / decremented address;
a first and second input selector switch ( 31, 32 ) for selecting a desired address of the desired address register and the output signal of the address increment / decrement device and outputting a selected signal to the read register or write register. 10. Image memory according to claim 9, wherein the address control device is characterized by
first and second thinning means ( 15, 16 ) for arbitrarily thinning out at least more than two pulses from a master clock signal, the two pulses being different for the first and second thinning means;
first and second counters ( 17; 19 ) for counting clock signals output from the first and second thinning means;
means ( 23 ) responsive to a count output of the first counter and generating a read control signal; and
means ( 24 ) responsive to a count output of the second counter to produce a write control signal. 11. Image memory according to claim 9, characterized in that the address generator the desired address that  was received from the desired address register into which Read address register and write address register when it moves the read control signal and the write control signal and the output selector to the read control signal and the write control signal responds to the read address and write address Submit time division basis. 12. Image memory according to claim 10, characterized in that the first input selector and the read address register are controlled by the read control signal, the second input selector and that Write address register by the write control signal can be controlled and the output selector switch the read and write control signal on a time division basis is controlled. 13. Image memory according to claim 10, characterized in that the address control device further comprises a counter ( 20 ) which counts the main clock signal, and a device ( 25 ) which generates a renovation control signal on the basis of the count value of the counter and that the address generator further includes a renovation address register ( 36 ) responsive to the renovation control signal to operate. 14. Image memory according to claim 10, characterized in that the second counter or first counter to the first and second holding device emits command signals to cause them to transfer data, being to everyone Time the second or first counter up the pulses counts corresponding to a number of bits which subject to parallel / serial conversion and one Number of bits that the serial / parallel conversion subject to. 15. Image memory according to claim 10, characterized in that the generating device for the read control signal has a first flip-flop ( 178 ), which is set with an external data reading designation signal, and a second flip-flop ( 179 ), which reads a set signal of the first flip-flop and moves it in response to a read request signal generated in the read control signal generating means. 16. Image memory according to claim 1, characterized in that the serial / parallel converter, the parallel / serial converter, the first holding device and the second holding device handle the parallel data in units of 2 ⁿ bits ( n a natural number), the data Is a memory cell array ( 5 ) which consists of ( K × 2 ⁿ ) columns × m rows, where K and m are natural numbers, and the first address control device has a first and a second counter ( 19, 17 ) to count the various clock signals, means ( 24 ' ) that generates a write control signal each time the first counter ( L × 2 ⁿ ) counts up ( L a natural number), and means ( 23 ' ) which generates a read control signal every time the second counter ( J × 2 ⁿ ) counts ( J a natural number) up. 17. Image memory according to claim 16, characterized in that the address control device further comprises a cycle generator ( 10 ) which receives the read control signal and the write control signal and supplies the address generator with a read cycle and a write cycle which in predetermined sequence on a time division basis. 18. Image memory according to claim 16, characterized in that parallel data which are held in the holding device are written in units of 2 ⁿ bits into the memory cell field, namely by the write cycle output signal on the basis of a write address of the address Generator, and parallel data stored in the memory cell array are read in units of 2 ⁿ bits by the read cycle output based on a read address from the address generator, and input to the second latch . 19. Image memory according to claim 16, characterized in that that the address control unit further includes a reset device having the first and second counters resets each other independently, and one Initialization device that the address value of the Write address or read address by the address generator is generated, initialized. 20. Image memory according to claim 17, characterized in that if the first counter continues to read pulses of a read clock signal and is reset by the reset device before it has counted up to the ( J × 2 ⁿ ) th pulse, the cycle generator assigns a new read cycle for the memory cell array in synchronism with the reset of the first counter, and the parallel / serial converter outputs all bits of data that were converted when the reset occurred, and then repeated outputs the last bit of this data during a time interval in which the subsequent signal is output from the first counter, and then parallel data, which are held in the second holding device, are again passed to the parallel / serial converter. 21. Image memory according to claim 16, characterized in that that the first and second counters are supplied externally Reset signals are reset. 22. Image memory according to claim 17, characterized in that the first and second counters have n binary counters for counting 2 ⁿ bits of data. 23. Image memory according to claim 17, characterized in that the first and second holding devices have two holding devices ( 104, 105; 106, 107 ) which are connected in parallel in order to alternately carry out the input and output of the data.