DE3500248A1 - High-speed multiple bus structure and method of data transmission - Google Patents

Abstract

The bus structure comprises both a parallel bus (35) and a series bus (37), which connect to one another data processing units (25, 26) and peripheral devices (30), jointly referred to as "stations", in order to permit the interchange of data and messages at high speed using a minimum of "handshake" events before the actual data transmission. The serial and parallel bus protocols are controlled by message control devices (44, 50), which are coupled to each participating station. A local bus (56) is coupled to processing stations (25, 26) within the system in such a way that access can be made to local memories (54) and secondary processing resources (57) without adversely affecting the data traffic via the parallel bus (35). A direct access by other bus stations to resources (54) coupled to the local bus (56) of one station is likewise controlled by the message control device (44). <IMAGE>

Description

High speed multiple bus structure and method

for data transfer The invention relates to a high speed parallel bus structure and a method of transferring data between a source and a plurality of receiving data processing devices. In particular, the invention relates to the transfer of data along a bus between a source and a plurality of data processing and peripheral devices using multiple bus structures.

In the computer industry, it is common to have data and commands between various data processing devices, e.g. computers, printers, memories or the like. to be transmitted via a system or data bus. A data processing system has typically has a processor stored at addresses in a memory Executes commands. The processed data is transmitted with the help of input / output (I / O) Devices are transferred to and from the system over a bus that controls the data processing system connects to other digital hardware. Usual speed limits data transfer between data processing devices connected to a bus are protocol or handshake restrictions that prevent a specified Sequence of events within specified time periods before the actual one Make data exchange between the devices necessary.

Different methods have been given to compare data between a Data processing device and a peripheral device, for example a memory unit, A second processor unit, a disk drive or the like. To transfer. A known method uses direct memory transfers and enables movement large amounts of information between a processor memory and a peripheral device. A disadvantage of existing direct memory transfer systems is that a certain processor function or activity for each direct memory transfer is required.

Various commands or other signals are needed for the transmission to start or stop, and the generation of these signals requires an interruption the processor unit. In data processing systems that use multiple processors, requires the direct memory transfer between the memory and a first processor and the memory and a second processor a complex system log and a complicated addressing to avoid ambiguity. For example, requires the data transfer between a local resource memory of a primary processor A and the local resource memory of a secondary processor B via a common one Bus typically interrupting secondary processor functions in order to secondary storage access and initiate a data transfer over the bus to the primary processor. In addition, any overlap of memory addresses between that of the primary processor complicates allocated memory and the memory of the secondary processor additionally the data transfer protocol, if ambiguities regarding the contents of each memory numbered on identically Address spaces should be excluded. It is clear from this that in data processing systems with several processors the appropriate allocation and access of the system resources are of vital importance to optimal efficiency in data transfers to ensure.

The invention provides a data processing system architecture that Multiple bus structures to optimize data and message transmission between multiple processors and a proper allocation of system resources all devices within each bus. The bus structure according to the invention contains a general-purpose parallel bus as well as special buses that interfere with the system are interconnected and define the communication and data transmission protocols.

A multiple bus system architecture and an improved one are specified Data transmission method for data transmission between several data processing resources. The bus structure according to the invention has both a parallel bus and a serial bus Bus on which the data processing units and peripheral devices - together as "Stations" ("agents") denoted-connects with each other in order to exchange data and messages at high speed with a minimum of "handshake" events before the actual data transfer. Both the serial and the parallel bus protocols are also controlled by message control devices, which are coupled to each subscriber station. A local bus is with the processing stations coupled within the system so that the local storage and secondary Processing resources without affecting data traffic over the parallel bus can be accessed. A direct access to the one with the local bus Station-coupled resources from other bus stations are also used by the message control device controlled.

When a calling bus station has a data exchange over the parallel bus seeks to initiate, it sets a bus request signal (BREQ) and sends a digital code according to their special station decision number (agent arbitation number) to an I.D. Bus that is connected to all system stations. The station requesting the bus gains parallel bus ownership if its decision number is has the highest given priority. The requesting or calling station gives then the address of the responding station along with its own address an address / data bus and at the same time gives a command via a command bus the answering station. The calling station gives a caller ready signal (REQ RDY), when it is ready to continue exchanging data. Similarly there the responding station issues a REPLY RDY signal when it is ready to continue data transfer is ready. Only when the two ready signals are pending the data on the address / data bus are considered valid. A data transfer operation is terminated by the calling station sending an end-of-cycle signal (EOC) with the REQ RDY signal.

A bus station that sends a message to another station wishes to send the serial bus according to the invention encapsulates the data message and sends it using your message controller after it has determined that the serial bus is not in use.

A responding station that receives the message sends in Acknowledgment signal (ACK) to the calling station during a predetermined interframe period, which follows the serial message. When a collision is detected on the bus the serial bus stations initiate a collision re-transmission arbitration cycle (collision retransmit arbitration cycle), which determines the ownership or occupancy of the serial bus appropriately allocates.

The local bus according to the invention constitutes a high-speed parallel bus with large bandwidth to local storage - and processing resources for the primary processor of a station. Data is shared between a primary (or secondary) processor and a local memory resource corresponding to the local Transfer bus protocol. All events on the local bus are transferred to the internal Clock cycles of the primary processor. If a responding station has the required Data operation (e.g. a write or read operation) in the case of the bus clock cannot execute a defined frequency, it can emit a WAIT signal, which causes the state and the information content of the local bus for the next Clock cycle are kept unchanged. Using a WAIT signal does it the answering stations possible at a lower speed than the Primary processor to work by inserting a delay while WAIT pending.

In the following, the invention is illustrated by means of one in the drawing Embodiment explained in more detail. The drawing shows: FIG. 1 a data processing system, suitable for implementing the teachings of the present invention; Fig. 2 is a block diagram of the main components of the message control logic provided in accordance with the invention; 3 schematically shows the various sub-bus structures used according to the invention Parallel system bus; Figure 4 is a timing diagram illustrating the parallel system bus protocol for illustrates data transfer between stations coupled to the parallel bus; Figures 5a and 5b are signal flow diagrams showing the sequence of operations one calling station coupled to the parallel bus for receiving data from a responding Station on the bus illustrated; 6 shows the allocation of lines of the control bus during the calling and answering phases; Fig. 7 is a flow chart showing the sequence of through a responding station coupled to the parallel bus performs logical operations for data transmission to a calling station illustrated; Fig. 8 schematically a requested message transmission over the parallel bus; 9 is a block diagram the main components of the serial message controller used to transmit messages via the serial bus according to the invention; Fig. 10 is a schematic representation the bus state detector circuit of the serial message controller; 11a the Data encapsulation structure for the transmission of messages between with the invention Bus structure coupled stations; Figure 11b shows the confirmation message structure that in the case of the serial bus to acknowledge a message transmission via the serial Bus is used; Fig. 12a is a signal flow diagram showing the sequence of through a represents logical operations performed over the serial bus by sending station; Figure 12b is a flow diagram illustrating the sequence of logical operations that at the same time by stations via the serial bus to detect message collisions to be executed; Fig. 12c is a signal flow diagram showing the sequence of those logic Operations represents which of stations over the serial Bus to detect and receive messages; Fig. 13 the deterministic end-of-collision decision cycle derived from the serial Bus is used; 14 schematically shows the various sub-bus structures which are included in the local bus according to the invention; Fig. 15 is a timing diagram showing the Illustrates a decision cycle for gaining access to the local bus; Figure 16 is a timing diagram illustrating local bus usage of WAIT; 17 is a timing diagram showing read access of the local bus with WAIT and exceptional conditions illustrates; 18 is a timing diagram showing the local bus block transfer and illustrates the continuation failure report; 19 is a timing diagram showing the illustrates local bus arbitration, pipeline operation and WAIT if the local bus is active under the control of the calling primary station; Fig. 20 is a timing diagram; which illustrates the local bus arbitration and WAIT when the local bus is on initially under the control of the calling primary station; 21 is a timing diagram, which illustrates the local bus block transfer and exception conditions; and 22 is a timing diagram showing the exclusive operations on the local Bus illustrated under a lock signal.

General system description A multiple bus system architecture is specified and an improved data transfer method for transferring data between a variety of data processing resources or system elements. In the following Description, special numbers, bytes, registers, addresses, Times, signals, etc. are given. However, it is clear to those skilled in the art that the invention can also be used without these special details. On the other hand will be known circuits and components indicated in the form of blocks of a block diagram, so as not to overload the description of the invention with unnecessary details.

Reference is made to FIG. 1 below. The invention can be a A plurality of processing units, generally identified by the reference symbols 25 and 26, as well as peripheral devices such as global memory 30 (or other Devices such as printers, disk drives or the like.) Include. For the purposes this description covers all data processing and peripheral devices, which are coupled to the bus structure according to the invention, collectively as ~ stations1 ' designated. As shown in Figure 1, the processing units are 25, 26 and the global memory 30 for mutual data transmission via a parallel bus 35 and a serial bus 37 connected to one another. The processing units 25 and 26 each have primary processors 40 and 41, which are connected to the parallel bus 35 and the serial bus 37 are coupled via corresponding bus interface units 44 are. As will be described in more detail below, the interface units 44 an I / O logic 46 and a message control logic 50. As shown is each processing unit with local data processing resources or system elements, such as store 54 or in the case of the Processing unit 25 connected to a secondary processor 57 via a local bus 56. The processors 40 and 41 with their associated local system elements, e.g. memories 54, coupled via a local bus interface circuit 58.

As will become apparent from the following description, made possible the bus architecture according to the invention enables high-speed serial messaging between all stations coupled to the bus as well as parallel high-speed data transmission between stations. In addition, the architecture described minimizes the Processor interruption in data transmission between bus stations, including of access to the data stored in local memories 54, the local Memory 54 a local resource or a local system element for each processing unit form. As will also be described, the data transfer protocols were so for the parallel bus 35 as well as the serial bus 37 and the local bus 56 defines that minimal handshake sequences for the execution of the data transmission required are. Although in Figure 1 only two processor units coupled to the bus are shown, it is clear that the structure of the invention is the compound of a Variety of processing units and peripheral devices, such as memories, disk drives, Printers or the like.

using all the bus structures described here.

Parallel bus Reference is made to FIG. 3 below. The parallel bus 35 has address / data lines 60, which in the exemplary embodiment described thirty-two address / data lines (plus four parity lines) the addresses and Data given alternately in multiplex mode will. In addition, the parallel bus 35 includes station arbitration lines 62, which each station coupled to the parallel bus 35 the transmission of a particular Enable station decision number for bus acquisition, and a priority line 64 (high priority line), which, as the following description will show, a station to obtain a parallel bus occupancy or possession regardless of the general decision protocol. Bus ownership or occupancy can with the help of a bus interlock signal on a bus interlock line 69 can be sustained, effectively preventing other stations from being acquired by a bus be locked out. In addition, a bus request line (BREQ) 66 is provided, which enables the stations to request the parallel bus control. Furthermore is an instruction bus 68 is provided which allows the processing units 25 and 26 to Communicate commands to other bus stations. Used to denote error conditions exception lines 70 as well as clock and system control lines 72 are provided which enable suitable synchronization and control.

The parallel bus 35 performs three types of bus cycles, which are when requested be initiated by a station, e.g., by the processing unit 25, viz the "arbitration" cycle, the "transfer" cycle and the ~ exception- " Cycle. For the purposes of this description, the decision cycle defined as the parallel bus cycle in which one station attempts an attempt is made to gain exclusive control of the parallel bus 35. The decision cycle ensures that only one requesting station can start a data transfer cycle at any one time on the parallel bus 35 can perform. At the end of the decision cycle only can a single station (e.g. processing unit 26) can use the parallel bus and Exchange data with another station. During the data transfer process a system error can occur that initiates the exception cycle. Every three parallel bus cycles work together in an overlapping manner, such that other stations can execute decision cycles during an ongoing transmission cycle, to determine which station is next to occupy the parallel bus will.

As shown in FIG. 2, the message control logic 50 a message controller 80, which over a conventional bus with a buffer memory 82 is coupled, a bus control device 84 and a direct memory access (DMA) interface 86 and a FIFO marker 88. Message control logic 50 is for implementation of the parallel and serial bus protocol, gaining access to the corresponding Buses and data transfer over the DMA interface 86 between others with the parallel (as well as serial) bus and memories 54 via local bus 56 connected stations responsible.

It is assumed, for example, that the processing unit 25 data stored in the global memory 30 using the parallel bus 35 should fetch. The processing unit 25 must first be controlled via its bus control device 84 Gain access to parallel bus 35 by initiating an arbitration cycle. As as shown most clearly in the flow chart of Figures 5a and b determines that Bus control device 84 within the processing unit 25 first of all whether the bus request line (BREQ) 66 is currently active. Assuming that the processing unit 25 does not Has priority request, it must wait until the BREQ line 66 fails is claimed before they enter the resolution phase of the decision cycle can. When the BREQ line 66 is not active or claimed is, the processing unit 25 seizes the BREQ line 66 and simultaneously puts one Digital code corresponding to your specific station decision number on the station decision lines 62 (see Figures 4 and 5a). Appropriate logic within the bus control device 84 each station coupled to the parallel bus 35 dials the arbitration number (arbitration number) of the requesting station, which has the highest specified priority within a fixed number of clock cycles after initiation of the decision cycle (assuming priority line 64 is not called became). If another station, for example the processing unit 26, at the same time Requests parallel bus acquisitions and the other station requests a decision number has higher priority, the processing unit 25 must respond to an end-of-cycle signal (EOC) wait for the end of a data exchange or the release of the bus designated. When a previous bus user calls the interlock line 69 has, all stations coupled with the parallel bus 35 must release (unlock) of the parallel bus before they can gain access and try to Gaining access to the bus by placing your decision number on the station decision lines 62 repeat.

In the embodiment described, the priority is below the stations connected to the parallel bus 35 by their associated decision numbers certainly. Each station has a position ("slot") or slot on the bus 35 coupled, and a reserved "T" seizure line is with each slot position coupled. When powered up, each station is assigned a station slot identification number as well as a special decision number from a central service module (CSM) which is connected to the bus (not shown). The central service module lays a station slot -Identification number to the station decision lines 62 and sets the T-seizure line according to the assignment of the slot identification number to an L value. Setting the T-seizure line to the L value sets the slot identification number in the registers of the station. Similarly, the CSM defines a special Decision number to the station decision lines 62 and drives the T-occupancy line to an L-value (low) corresponding to the station that the decision number is to be assigned. Setting the T-seizure line to an H (high) level locks the decision number. With the one described Embodiment denotes the state of a decision line 62 whether the the number of a slot number on the remaining arbitration lines or corresponds to a decision number. This process is repeated until all Stations receive their associated slot identification and decision numbers to have. It will be clear to those skilled in the art that various other priority hierarchies between the stations, e.g., the processing units 25 and 26 can.

It is assumed that the processing unit 25 (by priority their decision number) has taken possession of or occupied the bus. The processing unit 25 holds the bus in possession or operation even after the transmission has ended.

Assignment of how the BREQ signal remains untouched. Upon finding of an ECO signal or if the bus is unoccupied, the processing unit 25 sets a Digital code corresponding to the address of the answering station (destination address) and the address of the processing unit 25 (source address) on the address / data bus, if the data contains a message. At the same time, the processing unit lays down 25 a digital code corresponding to that of the answering station (in the example described the global memory 30) to the function to be performed Command bus. As shown in Figure 4, the command bus lines are effectively split, taking various acknowledged signals from both the requesting and calling Station as well as from the responding station can be sent as soon as a requesting or calling station, e.g. processing unit 25, the various Address and command codes are applied to the parallel bus 35. The creation of addresses and Commands by the calling station (processing unit 25 in the present case Example) completes what is known as the "request phase". As shown, the actual request phase only takes one clock cycle in the case of the one described Embodiment.

At the end of the request phase, the lines of the command bus 68 rearranged again in the manner shown in FIG. In particular, will be five command lines of the calling or requesting station and five command lines assigned to the responding station to carry out the required handshake for data transmission to complete between stations. In particular, the requesting or calling station (processing unit 25 in the example described) a caller ready (REQ RDY) Signal on an appropriate command line, indicating to the responder that the calling station is available to accept data on the address / data bus 60 stands. Similarly, the answering station (in the example described the global memory 30) a REPLY RDY signal (see Figure 7), indicating to the calling station that data on the address data bus 60 is valid and can be accepted. The protocol on the parallel bus 35 is therefore conditional asserting both the answering and calling ready signals before data on the address / data bus 60 are considered valid and locked. Additional Data packets can travel between the calling and the answering station via the parallel bus 35 through subsequent decrease in the answerer-ready and caller-ready signals and their reapplication are transmitted as shown in FIG. As is shown, the calling station (in the example described, the processing unit 25> an end of cycle (EOC) signal simultaneously with the application of the REQ RDY signal. The generation and transmission of the EOC signal notifies others using the parallel bus 35 coupled stations from the end of the current transmission cycle so that the Bus occupancy or bus ownership can be transferred. As best in Figure 5b shown, a responding station (in the example described, the global Memory 30) of the calling station a data transmission error (an "exception") during their handshake section, usually by a responder-ready signal signal as soon as valid data is scanned.

A data transfer cycle error that occurred during this period of of the calling station (in this case the processing unit 25) forces the assertion of an EOC signal on the next clock cycle, whereby further data transfers are interrupted and the bus occupancy for waiting Stations is released which successfully complete the decision cycle described above have finished.

Although the example described above is a data transfer from a answering station to a calling station, which is coupled to the parallel bus 35 is shown, it is clear that data transmission from a calling station (e.g. the processing unit 26) to a responding station (e.g.

of the processing unit 25) essentially the identical protocol as shown in FIG. 4, the parallel bus protocol follows of the present invention, simply putting on both the REQ RDY and the REPLY RDY signal required before disconnecting data from the parallel bus power. Therefore, the invention allows for differences in the relative Operation speed of the calling and answering stations using the same transmission protocol.

The message control logic 50 of the present invention enables many Communication and data transmission between those coupled to the parallel bus 35 Stations (and, as will be described below, the serial bus 37) at minimal Interruption of the primary processor within the processing unit. So can for example data to the local processor 40 or alternatively to and from a special one Resource memory 54 can be transferred without the primary processor 40 being interrupted will. As will be described, the message controller 80 checks within the message control logic 50 message addresses contained within the data packets run via the parallel bus 35 and the serial bus 37 to determine whether the special station should be involved in the message transfer operation. When a particular message control device is addressed, it checks this in the message packet Type field contained and generates any required by the primary processor Interruption. On the other hand, if an interruption is not required, then then appropriate direct memory access (DMA) interface 86 information transferred to access the resource memory 54 from an external calling party Enable station.

Referring now to Figure 7, the message transfer operations using message control logic 50. Let it be for example Assume that the primary processor 41 within the processing unit 26 data to the memory directly accessible by the processing unit 25 wishes. The requesting or calling station (processing unit 26) gives one "Buffer request" to your message control device 80, which is shown as a Determination byte corresponding to the address of the determination responses, a "Type" command - Byte corresponding to a specific desired operation (in this case a Data write operation), an identification byte corresponding to the special identification number of the calling station, a byte indicating the local data address where the for the access provided by the calling station data are stored, a optional file names, as well as a length byte and finally any data (if data is to be transferred) contains. These message bytes are sent via the local internal bus 29 to the message control logic 50 of the calling or requesting Sent station. The message controller 80 of the particular calling station (in this example the processing unit 26) stores the local address and the length information within the buffer 82 or the DMA 86 of the message control logic 50

The message controller 80 also adds a byte to the request packet, which contains a special cross transmission number (ID / S) that includes the present Requirement identified. The message controller 80 sends the buffer request packet Via the bus control device 84 on the parallel bus to the responding station (in this Case the processing unit 25) using the method previously referred to Figures 4, 5a, 5b, 6 and 7 described data transmission protocol. The message control logic 50 of the responding station leaves the request transparent to the primary processor 40 of the responding processor unit 25. Determined upon receipt of the message the primary processor 40 of the processing unit 25, whether a suitable memory buffer with the length defined by the length byte length 1 ". Once the primary processor 40 has allocated the queried memory space, will generates a buffer grant message in which the type byte is a one Buffer allocation corresponds to identifying special code. In addition, the Address space of the local answering station together with the associated buffer length ("Length 2") indicates which is actually assigned by the responding station or used memory size. This amount of memory used can depend on the the calling station may deviate from the memory size required.

Eventually this will be the cross transmission identification number (ID / S) repeats designating bytes which specifically identify the particular buffer requirement. The buffer allocation data packet then becomes the message control device via the local internal bus 29 80 of the responding station, which is the local address of the buffer as well the cross transmission identification number <ID / S) and the length 2 in the DMA 86 stores and, as shown, the cross-transmission caller number (ID / R) to the generated Buffer request packet added. The buffer grant message becomes the message control logic 50 of the calling station, which is then transmitted using the DMA interface 86 retrieves data to be transmitted to the responding station and this data to the bus control device 84 for the transmission to the answering station according to the previously based on the Figures 4, 5, 6 and 7 can send the protocol discussed. The data transfer can consist of one or more data packets, as shown in FIG.

As soon as the desired data transfer has been completed, it is generated the respective message control device 80 a general completion message, whereby the primary processors of the calling and answering stations are notified that the transfer is complete. Accordingly, messages can be as well as data between the stations coupled with the bus structure according to the invention at a minimum Interruption of the primary processor stations can be transmitted and direct Memory access for data transfers under the control of the Message control logic 50 included. It can be seen that the above-described Message transmission operations as shown in FIG. 8 also from the serial bus 37 can be used.

SERIAL BUS As previously described with reference to Figure 1, can each station within the bus structure according to the invention by a serial bus 37 and / or the previously described parallel bus 35 can be coupled. While the The structure and operation of the parallel bus 35 is primarily for large, high-speed data transfer is designed between the stations coupled to the parallel bus, the serial bus according to the invention primarily fast and effective communications between the bus stations. In the example described, the serial bus has 37 a two-wire series connection with the lines designated as "SDA" and "SDB". As shown in Figure 9, the message controller 80 has, within the message control logic 50 each station a serial message controller 100 for sending and receiving Serial data to and from various stations via the serial bus 37. Both Lines of the serial bus 37 are connected to a bus state detector 110, the provides three basic output signals. Encrypted recorded from the serial bus 37 Data become one together with a signal indicative of a carrier scanning signal Decoder 115 passed. As will be described in more detail below, is determined the bus state detector 110 also determines whether there is a collision between the over the serial bus 37 pending messages has occurred. A collision determination initiation 117 connects the bus state detector 110 to serial message controller logic 124, which, like the following Description will reveal the Controls collision retransmission decision cycle according to the invention. A serial one The transmitter 128 is connected to the control unit logic 124 and each serial line SDA and SDB connected to send messages over the serial bus 37. As shown, will be Messages to be sent serially via the serial bus 37 first via internal message control lines (not shown) coupled to the control unit logic 124, which is directly linked to another Message controller circuitry 80 within the message control logic block shown in FIG 50 is coupled.

Data transmitted via the serial bus 37 are used in the case of the described preferred embodiment 180C out of phase with lines SDA and SDS given. The serial message controller logic 124 also encrypts the to be sent data in the example described using the known Manchester coding methods. Reference is made to FIG. 10 below. The bus status detector 110 generates encoded data from the received serial transmissions, collision detection and carrier scan signals. The bus state detector 110 has optional "D" locking circuits 131 (for synchronization purposes) with two similar interlock circuits 132 are connected in series. A third pair of D-latch circuits 133 is in turn connected to the output of the corresponding latch circuits 132 and a detector logic circuit 136 (Figure 10). The outputs of the D-latch circuits 132 are for both lines SDA and SDB with associated inputs A2 and B2 in Figure 10 of the detector logic circuits 136 connected. Similarly, are the Outputs of the D-latch circuits 133 with inputs A1 and B1 of the detector logic circuit 136 connected. All interlocking circuits are activated simultaneously by a clock signal, typically clocked at 20 MHz, which is determined by the detector logic circuit 136 or one external clock is generated. The use of the D-latch circuits 131, 132 and 133 enables the comparison of sequential data bits which are based on the SDA and SDB lines are received at the same time.

The bus state detector 110 according to the invention provides a simple one Method of extracting encoded data transmitted serially via the serial bus 37 as well as to determine the collisions of messages over the serial bus. As shown in Figure 10, collisions over the serial data bus easily become thereby detected that the output of the collision detection port (CD) of the bus state detector 110 is monitored. If all inputs A1, A2, B1 and B2 of the detector logic 136 are at a low level (logic zero), then both lines SDA and SDB pulled low indicating a collision as both data lines usually from each serial transmitter 128 within its associated stations are out of phase by 1800.

Therefore, a low level (L level) can be applied to all ports A1, A2, B1 and B2 of the detector logic only occur in the event of a collision on the bus, since Due to the design, a logical one on the SDA line means that a logical one is pending Requires zero on the SDB line. Similarly, the serial bus idle periods by observing the output of the carrier scan port (CS) of the bus state detector 110 determined. As shown, a bus idle period is indicated by both Lines SDA and SDB are high (H level). The carrier scan port of the detector 110 indicated an idle condition by a logic zero (low) signal. Even though the operation of the bus state detector 110 for specific logic states is described has been, it is clear to those skilled in the art that other combinations of logic states can be used in the same way.

Reference is briefly made below to FIG. 11a. All over the Messages transmitted via serial bus 37 contain a synchronization ("sync") preamble 200 required for Manchester encoding followed by one of the destination address (e.g. processing unit 26) containing byte 210. Additionally, is the source station address 220 is provided to identify the originating station sending the message. A "type byte 225" identifies the character of the information transmitted between the stations News. Examples of type commands are a buffer request, a buffer allocation or the like. The type byte 252 is followed by an identification (ID) byte 230, which is a special Identification number for the specific sending station, and a data field 235

The message is ended by an error-checking CRC (16-bit CCITT) code 240 (known) to ensure error-free transmissions via the serial bus 37. Any serial message transmitted between the stations over the bus 37 is followed of a message-free period called the "interframe space "(INS) and in the described embodiment, for example forms four byte times. All messages running over the serial bus 37 will be from the receiving station using the message acknowledgment format indicated in Figure lib acknowledged. As shown, the acknowledge signal includes a sync preamble 200 followed from an optional simple acknowledgment field 260 which is a message acknowledgment signal contains special digital code representing it. In the system described takes place acknowledgment field 260 not used; instead an acknowledgment is given denotes the sync preamble 200 followed by a bus idle period within the Interval time. If there is no sync preamble 200 and / or idle period within the IFS time is detected, an error is assumed.

Based on FIG. 12a, the message control logic 50 is used for the Sending a message over the serial bus 37 executed sequence of logical operations described. It is assumed as an example that the processing unit 25 under Using the serial bus 37, send a message to the processing unit 26 got to. The processing unit 25 first determines by examining the carrier scan (CS) output signal of the bus state detector 110, whether the serial bus 37 is currently in Use is or not. In the example described, the lack of data transfers results via the serial bus 37 so that the two lines SDA and SDB are at a high level remain (see Figure 10). A NAND operation by detector logic 136 between Lines SDA and SDB would be on the serial bus in the absence of a carrier signal 37 result in an L state. As soon as the processing unit 25 determines that the Serial bus 37 is not in use encapsulates the serial message controller logic 124 of the processing unit 25 the message using the in Figure 11a message format and sends the message to the serial sender 128 for connection to the SDA and SDB lines. As soon as the processing unit 25 has sent its message via the serial bus 37, it waits for the receipt of a Acknowledgment message from processing unit 26 during the message following space using the format shown in Figure 11b. Assuming that the acknowledgment is received within the space is the serial message cycle is now complete.

If the processing unit 25 does not receive an acknowledgment message during of the gap and the bus state detector 110 on the serial bus 37 does not Has determined a collision, the processing unit 25 repeats the data transmission after setting an identification bit with the message type byte 225 to the second Transmission as a duplicate message packet too mark. if however, bus state detector 110 detects a collision, the Processing unit 25 (as well as the other stations coupled to the serial bus 37) a serial bus resend arbitration cycle, best referred to by reference on Figures 12b, c and 13 can be described.

Due to the nature of the data transmission via the serial bus, namely the feeding of the data with a phase shift between the lines SDA and SDB, causes the sum of the conflicting messages between one or more transmitting stations that both lines SDA and SDB at an L level (low Level) go. After a collision has been established, everyone is routing with the serial bus 37 connected stations a "jam cycle", which begins with that both lines SDA and SDB are driven to a low level to the serial bus to "disturb" for a predetermined number of bit times. The stations then remain in idle or idle mode, monitor the bus status for a specified time, to allow the collision to be resolved and wait an additional period (like an IFS) to ensure that a valid jam cycle has expired is.

As soon as the congestion cycle has ended, each transmitting station begins simultaneously over predefined time slots # 0 to #N (as shown in the illustration in Figure 13). Each station coupled to the serial bus 37 becomes one assigned to the specific time periods in which your message will be re-sent. As shown in FIG. 13, each time slot can in turn be divided into several (# 0 - #M) sub-slots, each sub-slot being one with the serial bus coupled special station is assigned. In such a case everyone would Stations when counting up to a time slot with an associated part time slot initiate a congestion cycle and the partial time slots within the primary time slot (Time slot # 2 in Figure 13) start counting. As a result, the transmission decision according to the invention can be effectively used in numerous stations coupled to the serial bus 37. Although FIG. 13 illustrates the use of partial time slots, this is described Embodiment only uses a single level so that only one station a special slot is assigned.

It is assumed as an example that a collision occurs via the serial bus 37 between messages that occurred from a station "A" and a station "B" were sent. Once the collision has been established, everyone uses the serial bus 37 coupled stations in the traffic jam cycle and start the sequential counting the time slots (in the example, each time slot contains about eight bit times) starting with time slot # 0. In the example station A is the time slot Assigned to # 0. Accordingly, all of the stations coupled to the bus 37 listen in counting the time slots until station A resends its data message Has. Once station A sends its message using the one marked in FIG Has re-sent the protocol, all stations start counting the time slot again, namely with the time slot # 1. In the event that part time slots have been allocated, as in the case of time slot # 2 in Fig. 13, after a pause, sub-time slots become similarly counted down from all stations to the stations that the special part time slot was assigned to send their messages to Accordingly, the inventive collision retransmission decision protocol is essentially indicative of the fact that each coupled to the serial bus 37 Station is assigned a predefined time slot in which it sends its message can resend. This provision differs fundamentally from previous ones CSMA / CD protocols such as the "Ethernet" method (U.S. Patent 4,063 220), which simply requires that all sending stations have a randomized one Expect time before the new broadcast so that a station can finally access the Bus wins.

Local Bus The local bus 56 of the present invention forms a high speed parallel bus large bandwidth to local storage and to the processing resources of a primary Processor within a processing unit, for example 25 and 26 according to Fig. 1. All information transfers that take place on the local bus 56, relate to a requesting or calling station or an answering station. A typical calling station would be a primary processor 40 or a secondary Processor 57 using the local bus 56 as a resource or system element of the primary Processor 40 is coupled in the processing of data operations. In a similar way Thus, a typical responding station on local bus 56 is a memory resource 54. The local bus 56 therefore allows the use of several dedicated data processing resources between the primary processing station 40 and a secondary processing station 57, as far as they are coupled to the local bus 56. In the described embodiment A maximum of two "calling stations" (processors) can use the local bus 56 at the same time be coupled.

As shown in Figure 14, the local bus 56 includes address lines 300, command lines 310, data lines 315 and several control lines 320 for maintaining the system control according to the protocol for the local Bus 56. A bus request line (BUS REQ) 325 is over the local bus interface 58 (see Fig. 1) between the secondary calling station 57 and the primary calling station Station 40 switched on. A bus acknowledgment is provided in a similar manner (BUS ACK) line 330 between the secondary responder 57 and the primary Response station 40 signals to identify the acknowledgment of the transfer of bus ownership. A bus clock line 335 is coupled to the primary calling station 40 such that that the local bus 56 synchronizes with the internal clock of the primary processor can be. Accordingly, all bus events are integral multiples of the bus clock period defined, and the start and end of each event or its duration have a defined relationship to the edge of the bus clock signal.

All bus data transfer operations consist of three types of Events known as cycles: the "arbitration" cycle, the ~ transfer "cycle and the" exception "cycle. The decision cycle ensures that one and only one calling station (either the primary or the secondary processor) a data transfer over a local bus 56 at any given time can initiate. In the example described, this will be the primary calling station 40 control over the local bus 56 in the absence of a bus request by the secondary calling station 57 given. Hence the primary calling station needs 40 only to enter the arbitration cycle when the secondary calling station 57 is coupled to the local bus and when the local bus is currently under control the secondary calling station is busy (note that the processing unit 26 of FIG. 1 does not have a secondary processor on its local bus, so you primary processor does not have to make a decision for bus occupancy).

The local bus decision cycle according to the invention is described below with reference to FIG described. When the secondary calling station 57 use the local bus 56 requests, it applies a bus request signal (BUS REQ) the bus request line 325. The primary calling station 40 acknowledges the bus request the secondary calling station by generating a bus acknowledgment signal (BUS ACK) on bus acknowledge line 330, releasing bus ownership to the secondary calling station 57 passes. The secondary calling station 57 can then appropriate Address and command signals on address lines 300 and command lines 310 to a local bus resource, e.g. to memory 54, to obtain the required initiate special bus operation. The creation of the address and command information by a calling station (processor) is referred to as the "request phase" and takes at least two clock cycles in the example. The responding station (for example a memory resource 54) can then suitable data (in the case of a read operation) onto data lines 315 for reception by secondary calling station 57 Use the protocols described below. The secondary calling Station 57 issues upon completion of the desired operation by the responding station the bus request line 325 free, thereby returning bus ownership to the primary calling station 40 goes back.

With reference to FIG. 16, the particular use according to the invention of a WAIT signal described. The WAIT signal can be used by anyone on the local bus 56 coupled answering stations are used to extend the response phase, by injecting delay clock cycles. When pipelining is in progress (The request phase of an ongoing bus operation overlaps with the response phase of a previous bus operation), the application of the WAIT signal can be initiated by the responding station serving previous bus operation to an extension of the Carry out the request phase of the current bus operation. As shown in Fig. 16, the primary processor 40 has a request (using address lines 300 and command lines 310) to a responder coupled to local bus 56 Station given. The answering station serving the previous bus operation has during the first clock cycle of the request phase of the current bus operation develops a WAIT signal indicating to the primary requesting station 40 that that the responding station serving its previous bus operation is not in was able to store the address and command information during the current bus clock cycle to record. If the addressed answering station needs additional time, in order to gain access and to give the requested data to the local bus, the assert a WAIT signal on the last clock cycle of the request phase. The requesting The station must continue developing the WAIT signal until the appropriate one Number of access delay cycles has been entered. Using the WAIT signal to develop delay cycles on local bus 56 would be in that Common case when the primary processor 40 is at a speed higher than the access time of, for example, a local memory resource 54 is working, since as will be recalled, the local bus 56 operates at the same frequency as the primary Processor 40 is clocked.

As shown in FIG. 16, the assertion of the WAIT signal results in the first clock cycle of the request phase to a continuation of the request phase the primary calling station for an additional two clock cycles. Hence that pushes WAIT signal actually introduces a delay in the state of the local bus lines but does not change the standard local bus protocol. Though any requirement on the local bus 56 for a minimum of two clock periods a responding station can respond to the request at any time after it has been received answers. In other words, an answering station can be as fast as an Clock cycle after Creating a request (zero cycle delay) answer even though the calling station (the primary or secondary processor) has the Request still created or maintained.

It can be seen that the application of a WAIT signal after the first Clock cycle of a request phase (i.e. during the second clock cycle) none Has an influence on the special request phase and only the response phase through extension influenced by the inserted time delays. For example, according to begins 16 shows the request phase of the second bus operation of the primary calling station during that clock cycle in which the response phase of a previous Bus operation should be terminated. When a WAIT signal has caused the Response phase of the previous bus operation by an additional one or more Clock cycles is delayed, the request phase of the second bus operation becomes corresponding be expanded. An application of the WAIT signal during the first clock cycle of the Response phase (of the last clock cycle of the request) leads to a delay in the response of the responding station up to the clock cycle at which the WAIT signal is picked up by the answering station. In the described embodiment only the current responder has the right to the WAIT signal during a response phase to develop or create a given bus operation.

Figure 17 illustrates the use of the WAIT signal by a respondent Station during the response phase and the exception cycles according to the invention. As shown, the primary calling station has a request (address and command information) on the address lines 300 and the command lines 310. There is no WAIT signal was pending the request from the primary processor during the first clock cycle the request phase only has the minimum time of two clock cycles.

The responding station placed depending on the request the WAIT signal during the first clock cycle of the response phase (last clock cycle the request phase), which indicates to all bus stations that the requested Bus operation is not carried out until the WAIT signal has been picked up, and that all other bus functions are delayed accordingly. In the example the answering station only needed one cycle as an access delay to get from the primary calling station to be read and recorded at the same time with the application of their response to the data lines 315, the WAIT signal. the Decrease in the WAIT signal during the response phase is signaled to the calling station either that the read data on the local bus is valid and is being scanned or that the "write data" entered by the calling station read in and the write operation has been terminated by the responding station is.

As shown in Figure 17, an answering station must be the calling Station (processor) of any error or exception related to the issued Teach the request phase during the first data transfer period of the response phase. In other words, in the described embodiment all exceptions are made for a request during the first data transfer period of the response phase reported. When a WAIT signal during the last clock cycle of the request phase is not pending, an exception is made for this request phase in this last one Clock cycle displayed. Exceptions for data are made while the data is being created is reported on the data bus 315 immediately following clock cycle (Figure 17).

Figures 18 and 21 show the exception report log of the present invention for requests, dates, and "continuation" exceptions. As in As shown in Figure 14, control lines 320 contain address (AERR) and data errors (DERR) lines which are arranged between all stations on the local bus 56 are. As previously described, exceptions are made for a requirements phase such as from a primary calling station 40 during the first data transmission period reported to the answering phase of the calling station. Similarly, there are exceptions for data applied to data lines 315 during data application immediately following clock cycle reported. According to the invention, continuation exceptions are made on the address error signal line (AERR) over the local bus to which the bus operation is taking place executing calling stations reported. The AERR signal indicates that the data applied to the data bus is not accepted by the expected responding station and shows that what is really a continuation error (i.e., a physical limit (overflow) error) has occurred. A continuation bug can occur in the case of block transfers when the responding station receives the Responder data address advances after each operation and the admissible address range of the answering station. In such a case the respondent shows Station to the calling station that a continuation error has occurred. These is done by activating the AERR line during the period in which the requested Data should be valid. Therefore, all continuation errors are concurrent with reported to the clock cycle in which the data would otherwise be valid. Continuation errors can also be reported by a responding station, which does not handle block transfers when there is a block transfer request Has. When a WAIT signal has been applied, this period is delayed accordingly.

Reference is now made to FIG. 19, in which the capability of the local bus 56 for "pipeline" operation by allowing one to overlap Request phase of a given calling station bus operation with the response phase the previous bus operation is shown. In the example described there primary processor 40 its first phase of request on the address and command lines.

The primary calling station (processor) 40 can perform its second bus operation initiate immediately after the end of the current request phase, if the first bus operation is not a block transfer. If the first bus operation is a Block transfer is the second bus operation can be up to that clock cycle cannot be initiated in which the last data transmission period is the first Bus operation is expected.

Figure 20 shows the case where the primary calling station 40 has access to local bus 56 and secondary calling station 57 has gained bus access required. As shown, the secondary processor 57 seizes the BUS REQ line during the primary calling station's request phase. The primary calling Station may not use the local bus before the one following the end of its response phase Enable the clock cycle for the secondary calling station. As shown, begins the secondary calling station 57 request phase on the clock cycle that follows the clock cycle at which the BUS ACK is set by the primary calling station 40 is.

Figure 20 also shows the time at which the secondary calling station 57 the lines upon completion of their answering phase for the primary calling station 40 releases. As indicated, is the earliest time the secondary will be calling Station can return the occupancy of the bus to the primary calling station, the the clock cycle following the last clock cycle of their response phase. This is because of this that achieved the secondary responding station 57 receives its BUS REQ signal resets.

In the following clock cycle, the primary calling station 40 must use the BUS Reset or delete ACK signal and can initiate the request phase of a new bus operation kick off.

In the example shown in FIG. 20, the answering station has 40 the WAIT signal during the first clock cycle of the response phase of the secondary calling station, which means that data is created for an additional clock cycle is delayed. Resetting or deleting the WAIT signal in the following cycle indicates that read data on the data lines is valid and from the requesting Station must be accepted. The WAIT signal is also used for the one-clock delay to be introduced in the response phase of the bus operation of the secondary responding station.

In addition to the WAIT control signal, the local bus 56 contains others Control lines, e.g. LOCK, which is a signaling mechanism through which each other exclusive bus operations can be enforced. The LOCK signal is from a and from all respondents coupled to the local bus 56 Stations received. The LOCK signal can be set by the calling station, who has possession of or access to the bus at a given point in time.

All responding stations must monitor the LOCK signal, and if they are involved in the bus operation when the LOCK is set, they must be non-local Lock or lock bus ports and keep them locked until LOCK is reset. It is the responsibility of both the primary and the secondary calling Stations do not release their occupancy of the bus until they belong Set of mutually exclusive bus operations completed and LOCK reset or is deleted. As shown in Figure 22, the effect of the LOCK signal is when calling a mutually exclusive condition, which it a given Bus station enables a sequence of bus operations with a responding station without another calling station answering it in the meantime Station can use. If the local bus has 56 multiport answering stations, the mutual exclusion function requires a lockout of all non-local ones Bus ports.

Although Figures 15 through 22 referring to a primary or secondary Station based on data of a storage resource 54 or the like. access and data from Obtaining this resource, have been described, it is clear that the same data transfer protocol can also be used in the event that a calling station (processor) Data to a memory resource 54, processor, or other data processing device writes. In the case of a write operation, a responding station can by using of the WAIT signal introduce pauses within the bus state so that buffers are allocated and data can be received and checked for errors. The requesting station, which data inputs during a write operation, the data input must be on the Extend the next clock cycle if the WAIT signal is also set in this clock cycle is (see Figure 21).

As the above description has shown, the invention provides a special system bus architecture and data transmission protocols are available that were not previously known in the prior art. The parallel bus according to the invention 35 allows large amounts of data to be transferred at high speed between with stations or participants coupled to the bus, for example data transmissions between processing units, global memories or other data processing devices. Similarly, the serial bus 37 according to the invention enables an effective Message transmission between Stations or participants within the bus structure, thereby eliminating message passing traffic on the parallel bus 35 will. In addition, the local bus 56 provides a high speed parallel bus large bandwidth for data transfer between a primary processor and a Large number of local resources without affecting the available bandwidth of others System buses.

- blank page -

Claims (24)

CLAIMS 1. High speed multiple bus structure for transmission of data between several data processing devices (~ stations "), of which at least a station one via a local parallel bus with at least one responding Station-coupled primary processor, characterized in that address lines (300) for the transmission of address information with the primary processor (40) and the answering station (54) are coupled that command lines (310) for transmission of command information with the primary processor (40) and the responding station (54) are coupled that data lines (315) for data transmission with the primary processor (40) and the responding station (54) are coupled and that a WAIT signal generating device is connected to the responding station (54), whose WAIT signal to the local bus (56) coupled stations (25, 57) can be transmitted, with further bus operations be delayed until the WAIT signal is cleared, so that data on the local Data bus regardless of differences between the operating speeds of the answering station (54) and the primary processor (40) are transferable. 2. Bus structure according to claim 1, characterized in that the local Bus (56) also has a clock line (335) which is so connected to the primary processor (40) and the responding station (54) is coupled that all events on the local bus (56) as an integer multiple of the operating rate of the primary processor (40) are clocked. 3. Bus structure according to claim 1 or 2, characterized in that the arrangement is made so that a during the first clock cycle of the address and data information (a "request") of the primary processor (40) asserted WAIT signal the primary processor continues creating the address and data information (request) leaves until the WAIT signal is cleared. 4. bus structure according to claim 3, characterized in that the setting of the WAIT signal after the first clock cycle of the request from the primary processor (40) to a delay in all further bus operations, with the exception of termination the request of the primary processor. 5. Bus structure according to claim 4, characterized in that after deletion of the WAIT signal by the responding station (54) further bus operations beginning during the erase clock cycle. 6. Bus structure according to claim 5, characterized in that that the Primary processor request to the corresponding address and command lines (300, 310) for a minimum of two clock cycles in the absence of a WAIT signal during the first clock cycle of the request is left pending. 7. Bus structure according to one of claims 1 to 6, characterized in that that a secondary processor (57) is coupled to the local bus (56) that the secondary processor a bus request signal generating device for applying a bus request signal (BUS REQ) via one coupled to the primary and secondary processors (40, 57) Bus request line (325) to the primary processor (40), the queuing of the BUS REQ signal, a request from the secondary processor (57) to gain access to the local bus (56), and that the primary processor (40) one Has bus acknowledgment signal generating device which has a bus acknowledgment signal (BUS ACK) via one coupled to the primary and secondary processors (40, 57) Bus acknowledgment line (330) is applied to the secondary processor (57), the application of the BUS ACK signal by the primary processor (40) a bus access assignment for indicates the secondary processor (57). 8. bus structure according to claim 7, characterized in that the arrangement is made so that the presence of the BUS REQ and BUS ACK signals and the absence a WAIT signal to the secondary processor (57) the application of address or command information (a "request") on the address or command lines (300, 310). 9. bus structure according to claim 8, characterized in that the responding Station (54) terminate a bus operation after the first clock cycle of a request can. 10. Bus structure according to claim 9, characterized in that the responding Station (54) has an exception signal generator, the exception signals as a function from a request developed during the first clock cycle in which the respondent Station (54) can respond to the request. 11. Bus structure according to claim 10, characterized in that the answering station (54) signal generating means for generating continuation exception signals depending on a request from a processor (40, 57) during that Clock cycle in which valid data is applied to the data lines (315) should, has. 12. Bus structure according to claim 11, characterized in that the Primary and secondary processors (40, 57) lock signal -Means of production for applying a locking signal to at least one responding station (54) have, the application of the locking signal causing each responding Station (25, 57) only accepts requests from the calling processor until the lock signal is deleted. 13. Method for data transmission in a bus structure between several Data processing equipment ("stations"), at least one of which has one local parallel bus primary processor connected to at least one responding station characterized in that an address of the responding station representing digital code generated and coupled to the stations of the local bus Address lines are applied that a command to the responding station representative Digital code is generated and transmitted that perform a desired operation on with the Stations of the local bus coupled command lines denotes that one with WAIT line coupled to the stations is monitored for a WAIT signal and if the WAIT signal is detected, further bus operations are delayed until the WAIT signal is cleared and that data is on with all stations on the local bus coupled data lines according to the operation identified by the command signal be recorded so that data between stations coupled to the local bus and responding stations can delay further bus operations, until the WAIT signal is cleared. 14. The method according to claim 13, characterized in that clock signals are generated synchronously with the internal clock operation of the primary processor and that the clock signals to a clock line coupled to each station on the local bus are created so that all local bus operations as integer multiples of the Clock signals of the primary processor are clocked. 15. The method according to claim 13 or 14, characterized in that the application of the WAIT signal during the first clock cycle of the application of the address and data information (a "request") required by the primary processor makes that the primary processor creates the address and data information (request) continues until the WAIT signal is cleared. 16. The method according to claim 15, characterized in that the application of the WAIT signal after the first clock cycle of the request from the primary processor to a delay in all further bus operations, with the exception of the termination of the Request of the primary processor, leads. 17. The method according to claim 16, characterized in that after deletion of the WAIT signal by the responding station further bus operations, beginning during the erase clock cycle. 18. The method according to any one of claims 15 to 17, characterized in that that the requirement of the primary processor on the associated lines for a minimum of two clock cycles in the absence of a WAIT signal during the first clock cycle the requirement is maintained. 19. The method according to any one of claims 15 to 18, characterized in, that the responding station initiate a bus operation after the first clock cycle of a request can finish. 20. The method according to any one of claims 15 to 19, characterized in, that from the responding station errors in a request from a processor indicative Exceptions during the first clock cycle in which the responding station can respond to the request. 21. The method according to any one of claims 13 to 20, characterized in that that from a secondary processor a bus request signal (BUS REQ) via a with Bus request line coupled to the primary and secondary processors to the primary processor is applied, whereby an access request from the secondary processor to the local Bus is displayed and that a bus acknowledgment signal (BUS ACK) is applied to the secondary processor via a bus acknowledgment line, whereby from the primary processor assigning bus access for the secondary processor is shown. 22. The method according to claim 21, characterized in that when queuing the BUS REQ and BUS ACK signals and, in the absence of a WAIT signal, the application of Address and command information ("request") on the address or command lines is allowed. 23. The method according to claim 22, characterized in that of the continuation exception signals indicating an address error at the responding station generated in response to a processor request during that clock cycle, in which valid data should be applied to the data lines. 24. The method according to any one of claims 15 to 23, characterized in that that generated by the processors and a lock signal to at least one answering station can be transmitted and that the interlocking signal causes that the answering station only accepts requests from the calling processor, until the interlock signal is cleared.