DE3435816A1 - DEVICE FOR NUMERICAL SIGNAL PROCESSING - Google Patents

Description

PRINZ, μξΓ§Ερ,: · ΒμΜΚΕ:. & PARTNER

Patent Attorneys European Patent Attorney's

/ S

2 B. September 1984 THOMSON-CSF
173, vol. Haussmann
75008 PARIS / France

our reference: T 3725

Device for numerical signal processing

The invention relates to a device for numerical signal processing.

Such processing is different from processing in the field of computer science by the volume of operations carried out (which, by at least an order of magnitude greater than the processing power of a general-purpose processor) as well as by the Persistence of the algorithms (since the transformations carried out over time on the signal to be processed consist of unchangeable elementary sequences of operations, which may be invariable or temporal enter coefficients that change only slowly compared to the calculation frequency).

There are known two types of devices that perform numerical signal processing, one of them a multiprocessor structure (abbreviated MIMD for

Multiple Instruction Stream, Multiple Data Stream), while the other has a multi-operator structure (abbreviated SIMD for Simple Instruction Stream, Multiple Data Stream).
.

In the case of the multiprocessor structure, the device consists from several processors, which are related to each other and each with their own sequential control, Computing unit, memory, etc. have. With such a structure, a Breakdown of the processing sequence into a more or less linear sequence of elementary transformations with made a specialization of the processors depending on these elementary transformations. Around to carry out this processing sequence the processors, which are often organized in "pipe-line", each have one or more of these successive elementary ones Transformations. So they are at least differentiated by their program.

There is another possibility for performing signal processing by means of a multiprocessor structure is to carry out the complete processing sequence in each processor, but only on a part of the samples of the input signal, with the processors alternating in time to ensure uninterrupted consideration of the input-side samples. The processors then no longer have to be made different from one another by their program. But there is an output-side sample in general is calculated from a sequence of input-side samples, the sequences of input-side Samples stored in the memories of the various processors overlap to a large extent, which results in poor use of the entire storage volume. In such an embodiment e.g. calculate N processors at the same time

N output-side samples from sequences of η input-side Samples stored in the memories of these operators, the first samples of the sequences are spaced from one another by one sampling period. The same input sample must can therefore be stored in as many memories as there are samples in a sequence (if η <N), which results in poor utilization of the available storage volume.

...

In the case of the multi-operator structure, the device has only via a sequential control, which controls several operators in the same way (whereby an operator that occasionally is called an elementary processor, consists of a memory and a computing unit), and it an exchange unit is generally provided for exchange between operators of the "ring bus" type. The device applies the same program to the sequences of different upstream samples at. With a multi-operator structure, the problem of signal processing can only be solved to that extent how it can be "parallelized", i.e. broken down into identical tasks that are carried out on different Sequences of input signals are carried out: There are as many signal streams as operators. This is true for example in the case of filter processing for each output signal from the probes of an antenna is carried out: The signal of each probe is applied to an operator belonging to this probe. Disadvantageous with such a structure it is therefore expedient to use it only for a few types of signal processing is.

The device according to the invention is in terms of their Structure related to the multi-operator devices and therefore structurally has the advantage of a single sequence control, which multiple operators in the same way

controls, but is functional with the second type of multiprocessor device application described above related, but by a special organization of the input-side samples in the different Storage and, in correlation with this, poor utilization of these memories due to a special addressing of the storage volume present in this embodiment is avoided.

^T h ^e apparatus according to the invention for numerical signal processing includes means for sensing samples of the signal to be processed, N operators, each of which contains a computing unit and a memory in which the samples of the stored signal to be processed, a sequence control which the N operators in controls in the same way, addressing means for addressing during writing and reading of the N memories, the N arithmetic units being connected to one another by a ring bus, each of the N memories having a zone which is reserved for the storage of incoming samples in B segments (numbered from 0 to B-1) are organized, each containing S samples, further N segments of the same number b (where b can take the values 0 to B-1) the N memories are limited by identical addresses * and a group of number b, where the address of a sample in the so for the N operator The memory zone obtained is then defined by the coordinates (b, n, s), where η denotes the number of the operator (n takes the values from 0 to N-1), b the group number and s the relative address of these samples in the segment which is determined by the pair (b, n) (where s takes the values from 0 to S-1), and wherein the means for write addressing the N memories comprise means for sequentially storing the samples of the signal to be processed in the order of their arrival in the memory zone thus obtained with increasing write priorities according to the

/ ■. ". ■ '■ -

Address, inside a segment, the operator number and the group number.

Furthermore, the read addressing means comprise the N memories Means, for each memory access triggered by the sequencer, to each of the N memories two addresses to be supplied, namely: *

^A p ^{= A} INF ^{+ S} p ^{Una A} c = ^A SUP ^{+ S} p 10

and each operator of the number η comprises means to select A if η is greater than or equal to η, or to select A if η is less than η, where A _T "" and A _{gU p are the original addresses of} the two adjacent groups with denote the numbers b and b +1 and in which (b, η, s) denote the coordinates of the pilot sample relative to the memory access under consideration or the sample which of the N samples read out from the N operators during the memory access under consideration have been recorded for the longest period of time.

Further advantages and features of the invention result from the following description of exemplary embodiments and from the drawing, to which reference is made. In the drawing show:

1 shows a schematic overview of the organization

the input-side samples in the ver-30, different memories of the invention

Contraption;

2a shows a schematic overview of the organization of the input-side samples in the various Saving the invention

Device for an example of numerical processing, its successive steps are shown in Fig. 2b;

mm CC -

3 shows a block diagram of the device according to the invention in a first embodiment;

4 shows a block diagram of a second embodiment ■ the device;

5 shows a schematic representation for the purpose of illustration the method for reading out samples stored on the input side;

Fig. 6a and 6b ■ · -

Flowcharts showing the various steps of the read address calculation for the stored show upstream samples; and

Fig. 7 is a block diagram showing exchanges

for exchange with the external environment of the device shows.

The example shown in Fig. 1 corresponds to the case where the number N of operators is 4. A number η is assigned to each operator (n from 0 to N-1). In a set of B is adjacent to the memory of each operator Zones delimited, where each zone is referred to as a segment and each has the same capacity of S words for storing the samples. This set of B segments begins in each of the N memories same original address, and a group or "band" denotes a set of N segments that go through identical addresses are limited and belong to different operators.

The position of a sample in the N memories is then determined by the coordinates (b, n, s), where η is the Designates the number of the operator in which this sample is stored (n between 0 and N-1), b denotes the Group number is (b from 0 to B-1) and s is the relative

address of the sample in the segment determined by the pair (b, n) (s from 0 to S-1).

In the so-organized Save the eingangsseiti- 'stored 5 gen Abtasproben sequentially, it is that only one of the variables (b, n, s) is incremented, the variable s changes slowest fastest and the variable b itself. The coordinates (b (t), n (t), s (t)) of the sample X (i) which is written at a point in time t are thus derived from the coordinates

(b (t-1), n (t-1), s (t-D) derived from the sample X (i-1), which is written at time t-1, as follows:

s (t) = s (t-1) + 1 (modulo S)
if s (t) = 0, η (t) = η (t-1) + 1 (modulo N) if s (t) t 0, η (t) = (t-1)

if η (t) = 0 et s (t) = 0, b (t) = b (t-1) + 1 (modulo B) if η (t) f 0 et s (t) ^ 0, b (t ) = b (t-1)

The example of FIG. 1 will now be used to describe the manner in which the input-side samples are written into the memory organized in this way is described. With f + 1 the number of input samples required. X to obtain an output sample Y, and the following values are given as an example viewed from N, B, S and f: N = 4, B = 2, S = 3 and f = 3.

The detection of NS (equal to 12) on the input side is of interest Samples X (i) (where i is an index that is incremented with each sample period), e.g. X (15) to X (26), this detection extending over a period of time called the repetition sequence is (denoted by R) and is NS Tech (i.e. 12 Tech), where Tech is the time interval between two consecutive upstream samples is (or sampling period) while the upstream samples

X (3) to X (14) were detected during the previous' repetition sequence R-1 and, inter alia, the input-side Samples X (O) through X (2) during the repetition sequence R-2 were detected.

In the course of the same repetition sequence, the acquisition (denoted by A) of input-side samples takes place and the processing (denoted by T) of input-side samples already acquired at the same time.

IQ In the course of the repetition sequence R, NS (ie 12) samples X (1.5) to X (26) on the input side are acquired, and during a computing time that is equal to T with T ύ NS Tech, NS + f (ie 15) on the input side Samples X (O) through X (14) processed. For the processing

This is because f further samples are taken into account required as it is applied to sequences of f + 1 upstream samples.

That memory zone which contains the input-side samples that are required for processing during a repetition sequence are required, so will occupied by NS + f words. Since the same sample on the input side is repeated several times in the course of the calculation T is used to obtain multiple output samples, this zone must be used for writing each new input-side sample locked during the time of the calculation T within this repetition sequence stay. The acquired samples must therefore be available in the case of two groups or bands Zone with capacity 2NS- (NS + f) samples, i.e.

NS-f samples, are stored. So two groups or bands are sufficient, provided that T £ (NS-f) is Tech. In the example under consideration, T _c equals 6 Tech, and (NS-f) Tech equals 9 Tech.

In Fig. 1 is an example of the position of 2 NS + f on the input side Samples X (O) through X (26) shown (which

are indicated by their indices from 0 to 26), in the various memories and in the course of the Repetition sequence R, on the one hand with regard to the processing T of NS + f input-side samples X (O) bis X (14) and on the other hand with respect to the detection A of NS input-side samples X (15) to X (26) in the course this same repetition sequence. The samples X (O), X (D and X (2) captured during the repetition sequence R-2 have e.g. the coordinates. (1,2, .1) (1,2,2) and (1,3,0), and those of samples X (.3) through X (14) acquired during the repetition sequence R-1, are (3,1,1) to (3,0,0). These samples are shown with hatching in a first direction (with the exception of samples X (12) through X (14), which are shown with vertical hatching because they correspond the additional samples mentioned above) to make it clear that these are samples, which are kept from one repetition sequence to the next. Samples X (O) through X (14) are those which are processed during the computing time T in the course of the repetition sequence R.

During the repetition sequence R in rhythm samples X (15) through X (26) captured upon arrival then the coordinates (0,3,1.) to (1,3,0) are assigned. Samples X (21) to X (26) were included in one hatchings inclined in the second direction to make it clear that these are samples, which were recorded outside the computing time T in the course of the repetition sequence under consideration. The samples X (15) to X (20) are shown with cross-hatching, which means that their acquisition occurs simultaneously with the processing (T) of the samples that were detected during the previous iteration sequences.

The position of the input-side samples X (12) to X (38) in FIG. 1 is based on the same principle

different memories in the course of the repetition sequence R + 1 drawn.

The manner of reading from the memories organized in this way will now be described with reference to FIGS. 2a and 2b will be described by way of an example of processing similar to transversal type digital filtering is equivalent to.

The Trans-. formation is defined as follows:

f
Y (n) = Σ C. X (nj)

J = O ³
15th

where Y (n) denotes the output sample, which is obtained from f + 1 input-side samples X (n-j) by assigning them to the coefficients C. be provided. To illustrate this example, a number of coefficients f + 1 is chosen equal to 4, with a number N of operators equal to 4, a number B of bands equal to 3 and a number S of samples equal to 4 per segment.

It is assumed that the device previously has the input side Samples X (i), e.g. X (O) to X (44), their distribution in the various memories is shown in Fig. 2a, and the calculation of the output side samples Y (i) will be described.

The elementary transformations carried out for this purpose are shown in FIG. 2b, where on the abscissa each column represents a different operator, while the ordinate represents the machine time divided into computing cycles where the left column indicates the elementary transformation that is carried out simultaneously by the four operators for the upstream samples X (i)

which are designated by a single number i.

As a pilot sample with the coordinates (b, η, s) in relation to a given calculation cycle, the sample probe X (i) denotes that of all probing pr-above, which is carried out simultaneously by the various operators during processed during this computation cycle is the oldest (i.e. the one with the smallest index -i).

IQ At the beginning of the calculation (time t _Q ), the first samples X (10), X (14), X (18) and X (22), which are each spaced by S = 4 samples, are simultaneously performed by the operators with the Numbers 2,3,0 and 1 read out, the pilot sample then being X (10) with coordinates (0,2,2). Samples X (10) and X (14), both of which lie in the band numbered 0, are read out with the same address A, which is referred to as the pilot address, with reference to a pilot sample X (10) which is within of this tape lies, while the samples X (18) and X (22), both of which lie in the tape with the number 1, are read out with the same address A, which is referred to as the "copilot address". These four samples are simultaneously multiplied by the appropriate coefficient CU, which is supplied by the sequential control system, in the arithmetic units.

The same happens in the following computing cycle the samples X (11), X (15), X (19) and X (23) multiplied by C2, where X (11) is the pilot sample is.

At this stage of processing, the calculations started in each of the operators cannot be completed there because not all required samples are available in a considered operator. The calculation will then continued in the neighboring operator that has the sequence of required operand samples. For this purpose, the in each arithmetic unit

Intermediate results obtained are transferred to the neighboring processing unit: Four exchanges occur at the same time. For example, C ₃ X (IO) + C ^ X (H) is transferred from the arithmetic unit of operator 2 to the arithmetic unit of operator 3.

In general terms, an operator n, in which a calculation cannot be ended, transfers its partial result ¹ to the neighboring operator n + 1 (modulo N), which either - in the case of f £ S - completes the process or a transfer to the neighboring operator n + 2 (modulo N) (namely for f> S) until all f + 1 samples are used up. With each transition to a neighboring operator, the read address again assumes the value that designates an initial sample of a segment.

The calculations are continued until the four correlation results Y {13), Y (17), Y (21) and Y (25) are obtained, which - as shown in Fig. 2a - are arranged in a memory zone of that operator who completes the calculation, which shows the advantage of minimizing the computation time.

The calculations are continued using samples X (11), X (15), X (19) and X (23) as initial samples, the pilot sample then being the one labeled X (11). By the same process as described above, four results Y (14), Y (18), Y (22) and Y (26) are obtained _{within the same calculation time T c.}

At time T ₁ , NS, ie 16, output-side samples Y (13) to Y (28) are calculated because the initial samples (X (10), X (11), X (12) etc.) are around one sampling period spaced from each other. If in general

-νΚΓ-

Formulate the initial samples by k samples are spaced apart, NS / k output side samples Y are obtained.

To compute the next sample Y (29), samples X (26) through X (29) must be available, ie "three samples that were previously used (f = 3) plus a new sample. The" oldest "sample is X (26-), and the same address configuration ^w;. i ^e i ^m at time t is found again, but with a shift * to a tape at the time t- | there are 16 samples, which are no longer needed and can be replaced with new samples.

This example of numerical signal processing illustrates the inventive principle. In signal processing If the algorithms remain the same, this leads to temporal parallelism. According to the invention, this Temporal parallelism exploited as follows: Under the condition that a sufficiently large section beforehand has been acquired by operand samples, multiple processings can then be performed in parallel by applying the same elementary transformations simultaneously to groups of samples, the equidistant taps along a captured section correspond.

The exploitation of this parallelism requires a special design of the multi-operator structure, which is now under With reference to Fig. 3 will be described, which shows the structure of the device according to a first embodiment of the Invention shows.

As in the case of the multi-operator structure, this device comprises a single sequential control 1, which _{controls in an identical manner N operators (2 Q} to 2 -._ J, each one arithmetic unit (3 _Q to 3 _N _ ..) and a memory (4 _{Q to} 4 _N _ ₁ ) included.

According to the invention, that memory zone which is reserved for the storage of the samples is in Ribbons and organized in segments as previously described and in this first embodiment provides the sequencer 1 at each point in time defined by the memory cycle, two read addresses: one Pilot address A for access to tape b, which

P. P.

contains the pilot sample for that memory cycle, and a copilot address A for access to the neighboring one Band b +1 (modulo B), as well as the number η of the operator in which the pilot sample is stored is.

Each operator 2 contains a comparator (5 _Q to 5 "..) which receives the number η of the pilot operator and its own number η and sends a control signal to an address selector 6 through which an address Ad is supplied to the memory 4 of the associated operator which is either equal to the pilot address A (if η 2; η) or equal to the pilot address A (if η <η). In addition to the pilot address A and the copilot address A _c and the number η, the sequencer 1 generates the operation _{code to manage the arithmetic units 3 n} and access to the memories 4, as well as the coefficients required for processing. The N computing units 3 ₀ to 3 _N-1 are connected to one another via a ring bus.

The computing units 3 contain suitable circuits for processing the real or complex samples. These circuits are from specialized groups of elementary operators and test groups, which are designed in such a way that they are necessary for processing apply the required algorithms (FFT algorithm, e.g. for image processing).

Addresses A and A are not calculated sequentially, because then the computation time is incompatible with

the signal throughput required at the memories of the operators were.

The calculation is broken down into two phases performed by two different circuits: a first Phase of calculation in relative sizes by means of a circuit called the main PLC control, and a phase of calculation in absolute values, carried out by a. Circuit acting as sub-sequencer referred to as. The phase of the calculation in absolute values for a given memory access takes place in parallel with the phase of calculation in relative values at the next Memory access.

The calculation in relative values consists in the coordinates (b, η, s) of the pilot sample. The calculation is carried out by incrementing when known the number INC of samples that separate two consecutive pilot samples from each other. if (b (t), η (t), s (t)) are the coordinates of the pilot sample for one computation cycle that at a point in time t takes place while (b (t + 1), η (t + 1) and s (t + 1))

PP P

are the coordinates of the pilot sample for the computation cycle that takes place at time t + 1. / and INC (t + 1) are the Is the number of samples that separate these two pilot samples, then:

s (t + 1) = s (t) + INC (t + 1) (modulo S) P P

s (t) + INC (t + 1) -s (t + 1). r -_ £ P- -

S - s

η (t + 1) = η (t) + C. (modulo N) ppi

η (O + Cj-iid + l)
^C 2 ⁼

2 ⁼ N

b (t + 1) = b Jt) ₊ C ₂ (modulo B)

-tr-

In a practical embodiment, tests are carried out according to the algorithm according to FIG. 6a. With the one before Example of processing described, INC was constant and equal to 1.

The calculation in absolute values consists in calculating the pilot address A (t) and the copilot address A (t) at a point in time t, with knowledge of the original _addresses A _ "" (t) and · Α αττη (t) of two adjacent bands, Which

XMJc oUJr

the zone processed at this point in time t overlaps, using the following relationships

^A p ^{(t) = A} INF ^{(t) + S} p ^{t)

^A C ^(t) = ^A SUP ^{(t) + S} p ^(t)
15th

where A (t) and A (t) depend on b (t) and s (t) denotes the relative address of the pilot sample at this point in time t in the segment to which it belongs in the processed zone / during A _Sü p ( t) is equal to A-rjjpit) ^{+ s} (where S is the number of samples per segment).

Each time the pilot sample enters a new band, the sub-sequencer adds the number S to the values of A _INF and A. The slave sequencer also receives the value of the original address ORG of the storage zone of the input-side samples for the redefinition of A _._ and A " _Tirt , if the pilot output

XJNJc oUir

tastprobe passes from band B-1 to band 0. The concrete meaning of the variable Ä. A. A, "", Α., .. ",

C ρ XiNr bUr

s and ORG can be seen from Fig. 5, where as an example the storage zone of the upstream samples in the memories of four operators is shown and where the processed zone, which straddles two successive bands, is indicated by hatching.

In the flow chart of Figure 6b, these are from the sub-sequencer operations performed.

U ■ ·:

The main sequence control and the sub-sequence control are for example designed as a computing unit which is assigned to a working memory which can be downloaded and contains instructions for performing the operations set forth in the flowchart.

In the embodiment variant shown in FIG. 4, the "calculation of the addresses * A and Ά is decentralized in performed by each of the operators, while in the embodiment according to FIG. 3 they are centralized in the sub-sequencer he follows.

This variant has the advantage over that described above that it reduces the number of connections between sequencer and operators decreased. The sequencer 1 is simplified and provides the coordinates η and s of the pilot sample and a control variable CA for calculating the address. Any operator but also contains the comparator 5 and an address calculation circuit 8, which the read address (A or A) to the memory 4 supplies.

For each computation cycle, the circuits 8 with the sequencer 1 carry out those operations that are in the Flow charts of Figures 6a and 6b are provided.

Each circuit 8 is implemented, for example, by a computing unit. · ·

The structure of the device according to the invention also differs from the structure of the multi-operator devices by means of exchange with the outside environment, i.e. the detection of the input side Samples and the delivery of the samples on the output side. In particular, enables the acquisition an organization of the samples in memory into segments and bands.

Vl

The means for the exchange with the outside environment, which are shown in FIG. 7, contain in a first embodiment a channel 10, which is referred to as "word-for-word input / output" and the operators 2 _Q to .2. J _-1 connects and also makes it possible to continuously fill up the memory zone which is reserved for the storage of the input-side samples and to empty the memory zone which is reserved for the storage of the output-side samples. "The mechanisms by which the addressing and the Read and write control are of a known type and of the DMA (direct memory access) type in order to make the flow of programs and exchanges with the outside environment independent of one another. The connections between the channel 10 and the memories 4 _Q to 4 _N-1 take place via bidirectional amplifiers 11 _Q to ¹¹ NT

The channel 10 is shared by two DMA controllers 12 and 13, an input and an output, which the Supply the write address of the input-side samples or the read address of the output-side samples. These addresses are obtained by successive increments in order to determine the sequential position of the input-side and take into account downstream samples, which in the manner described above by three Levels is defined: bands, segments and operators.

The exchanges are in the "word-for-word" mode of operation selective between storage and external environment: only the designated operator carries out a storage cycle.

In order to now carry out signal processing in which identical tasks are applied, the exchange processes between the storage tank and the outside environment can also be carried out in the "parallel" mode of operation. The capture and the output are then done simultaneously in all operators, each of them having a special one

"Parallel input / output" (14 _Q to 14 _Ν-1 ), whereby the connections between channels and operators are also made via bidirectional amplifiers (15 _Q to 1S _n-1 ).

These two embodiments are shown in FIG. 7, one of them is selected via mode selectors 16 _Q b _-1 , which is one of the two rows of directional
^Select ^ N-1.

one of them via mode selectors 16 _Q bis

v bidirectional amplifiers 11 _Q to 11 _N _i or 15 _Q to

The type of sampling or processing performed does not essentially change the device. In particular, it can be an image processing.

Claims (8)

• · PRINZ, LEISER, föüklKE! &. PARTNER Patent Attorneys ■ European Patent Attorneys r · * ---'-— Rtiittaart s? 3 4 3 5 8 1 i y j%> ~ September 1984 THOMSON - CSF 173, Bd. Haussmann 75008 PARIS / France Our reference: T 3725 patent claims 1. Device for numerical signal processing, with devices for capturing samples of the signal to be processed, N operators (2), each of which contains a computing unit (3) and a memory (4), which in particular the. Contains samples of the signal to be processed, a sequential control (1) which controls the N operators in an identical manner, write addressing means and read addressing means for the N memories, the N arithmetic units being connected to one another by a ring bus (7), characterized in that each of the N memories (3 _n ) has a zone which is reserved for the storage of input-side samples which are organized in B segments (numbered from 0 to B-1) each containing S samples, where N Segments of the same number b (b from 0 to B-1) of the N memories are delimited by identical addresses and form a band with the number b, the address of a sample in the so for the The memory zone obtained by N operators is defined by the coordinates (b, n, s), where η denotes the number of the operator (n from 0 to N-1), b denotes the volume number and s the relative address of this sample in the segment indicated by the Pair (b, n) is determined (where s takes the values from 0 to S-1), and in which the write addressing means of the N memories _{comprise means (10, 11 n} , 12, 13) for sequential storage of the To ensure samples of the signal to be processed in the rhythm of their arrival in the memory zone obtained in this way according to increasing write priorities according to the address inside a segment, operator number and tape number. 2. Apparatus according to claim 1, characterized in that the read addressing means of the N memories _{contain means (1 or 1, 8 n} ) for supplying two read addresses to each of the N memories for each memory access commanded by the sequencer (1), namely: A _p = A _INF + s _p and A _c = Ag _üp + s _p , and that each operator (2 _n ) of the number η _{comprises means (5 n} , 6 or 5.8) to select A when η is greater than or equal to η, or to select A when η is less than η, where A and A _gp denote the Or jump addresses of two adjacent bands with the numbers b and b +1, while (b, η, s) denote the coordinates of the pilot sample for the memory access under consideration or the sample which is among the N samples included in the N operators were read out during the memory access under consideration since the longest time they were recorded. 3. Apparatus according to claim 2, characterized in that the means for supplying the addresses A and A means include, for each memory access, the coordinates of the pilot sample for the subsequent memory access to be calculated by incrementing the coordinates the pilot sample for the memory access in progress by a number equal to the number of samples which separate two consecutive samples that are used for the same processing be turned. . , 4. Apparatus according to claim 1 or 2, characterized in that means for supplying the addresses Ά and A P c Means (1 or 1, 8 _n ) comprise, for each memory access, the original addresses A_ _N _ (t + 1) and A _sup (t + 1) of two adjacent bands with the numbers b (t + 1) and b +1 (t + 1), of which the lower band with the number b (t + 1) contains the pilot sample for the subsequent memory access, by incrementing the original address A _{IN_} , (t) for the currently present memory access by a number , which is equal to the number S of samples per segment if the pilot sample for the subsequent memory access changes to a different band compared to the current memory access, but without returning to the band with the number 0, by retaining the original address A_ _N _ (t) if there is no change to another band compared to the currently present memory access, or by allocation of the original address (ORG) of the zone which is reserved for the storage of incoming samples in the N memories, if a The tape is changed by returning to tape number 0, with the original _address A OT1D (t + 1) des O Ujt upper band number b +1 (t + t) is obtained in all cases by adding the number S of samples per segment to the original _address A INp (t + 1). 5. Device according to one of claims 2 to 4, characterized in that the means for supplying the pilot address and the copilot address a master sequencer. contain, which with each memory access the pilot and copilot addresses are calculated for this memory access, as well as a sub-sequencer which, with each memory access, the coordinates of the pilot sample calculated for the subsequent memory access. 6. Device according to one of claims 2 to 5, characterized characterized in that the means for providing the addresses A and A are arranged in the sequence control (1). P c 7. Device according to one of claims 2 to 5, characterized in that .the means for supplying the addresses A. and A are partially (8n) located in each of the N operators. 8. Device according to one of claims 1 to 7, characterized characterized in that the means for acquiring samples of the signal to be processed has N input / output channels (14), which are connected to the N memories (4), whereby exchanges between memory and Outdoor environment in "parallel operation" are made possible.