DE3342354A1 - SOFT PROGRAMMABLE LOGIC ARRANGEMENT - Google Patents

Description

Henkel, Pfenning, Feiler, Hänzel & Meinig

Control Data Corporation Minneapolis, Minn., V.St.A.

Patent attorneys

European patent attorneys Approved representatives' before the E Patent Office

D 'phii G Henke ^!
D: pi-! Ng J pfenning Be " ¹ "D'rer. Nat. L- Fei- .e ^r Mjic'-e 'Dip, -Ing W Hanzei M-uici". =' Dip ^ -Phys K H . M & nig. Be "" Dr. Ing A Butenscnon. Ben.n

Möhlstrasse 37
D-8000 Munich 30

Tel. 069 / 982085-87 Telex 0529802 hnkid Teiegramme eilipsoic

CDC 758-WG

November 23, 1983 / wa

Soft programmable logic arrangement

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The invention relates to a (soft) programmable one Logic arrangement or field (logic array) known type of circuit.

Programmable logic arrays are typically built into the chips of large integrated circuits (LSI) or very large integrated circuits (VLSI) incorporated. Such chips are of a type in which after the special logical function of the circuit is not determined during manufacture. A programmable logic array chip is designed so that its logical function can be determined later. Most of those previous chips are permanently programmable insofar as they contain fusible elements or other elements, which are permanently blown or melted to determine the logical function of the device. The invention now relates to "soft" (soft) programmable devices, each repeated with the same or different logical functions by means of a process of entering logical function data, also known as identification data, can be programmed. Although a softly programmable logic arrangement the loading of identification data required in order to be able to work is provided by the logic arrangement according to the invention is not simply a storage device. The identification data is used to store the specific control logical functions that are carried out at certain logical levels or stages in the arrangement should. In addition, chips according to the invention are arranged in four quadrants or sectors and have control circuits provided on each chip so that on one

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Chip several, independent arrangements with common function control are located.

An arrangement according to US Pat. No. 3,818,252 is known with a number of word and digit lines as inputs to an arrangement which has fusible elements for the programmable elements. This US PS shows effectively a variation of a programmable standard logic order with two levels for the generation of a product sum type Function, but it takes on the inventive soft programmable multilevel logic arrangement in no way ahead. US Pat. No. 4,233,667 also describes a programmable logic arrangement, however relating to Construction and performance is different from that of the invention.

US Pat. No. 3,912,914 describes a programmable switch module which can be used for any special large switch function to be used can be designed extremely complex, because the programming control for each switching function to their Control must be led away from the chip concerned by individual wires. The logic arrangement according to the invention is programmed by introducing a stream of identification data representing the various logical Control elements as a result of a labeling process. Other publications, e.g. the U.S. Patents 3,855,536, 3,976,983, and 4,293,783, all describe Logic arrangements that either require programming control via external logic pins, or which are subject to restrictions with regard to the specific, feasible logical functions.

The invention thus relates to a softly programmable logic arrangement which is used to implement special logic

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Functions is controllable by adding a stream of identification data which is latched in the logic arrangement in order to execute the programmed Initiate logic function. Logic arrangements according to the invention can be on a chip in sectors with common programming logic for different sectors can be combined into groups. With the described Embodiment four quadrants or sectors are shown.

The logic arrangement according to the invention is constructed from a number of logic levels or levels, each logic level contains a number of specific logic elements. In the described embodiment, there are two primary types provided by logic elements. The first type consists of a logical functional element or just one Functional element. Such a system has a number of inputs and is capable of all possible ones at these inputs perform logical operations. A special embodiment of the invention uses functional elements with three entrances and one exit as a building block. This function element contains data inputs that are saved as Control bits can be used for an 8: 1 multiplexer, the eight inputs of which are latched and the represent programmable logic inputs for controlling the output functions at the data output of the multiplexer.

The second type of logic element used in accordance with the invention is a pass / hold device that can be set to either a specific input signal to be locked until it is clocked, or to allow this as an output (s signal) regardless of the data input. In the illustrated embodiment, the causes Passing function also an inversion.

By using four levels of functional elements, combined with four levels of passage / holding functional elements with different logic connections between the levels, can essentially cover a number of Inputs every functional logical output can be achieved. A ninth logical level for output release as well as tri-state buffer elements ensure full control of all logical output levels. The connections or links of the logical elements at the various levels in the logic arrangement according to the invention enable a logical function to occur or to be switched through at all eight levels of logic as output signals at earlier (upstream) logic levels. The outputs (signals) of the second, third and fourth levels of the functional outputs can thus be used directly as outputs or output signals of the logic arrangement are gated.

In the following a preferred embodiment of the invention is explained in more detail with reference to the drawing. Show it:

1A to 1C side by side from left to right seen lying down, a detailed logic circuit diagram of an arrangement according to the invention,

Figure 2 is a detailed logic diagram of a

of the functional elements according to the invention in the arrangement according to FIGS. 1A to 1C, 30th

Figure 3 is a detailed logic diagram of one used in the arrangement of Figures 1A-1C Passage / holding device,

Figure 4 is a detailed logic diagram of a

output enable logic elements shown in Figure 1C ,

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5 shows a logic circuit diagram for a control circuit in the arrangement according to FIGS. 1A to 1C,

Figure 6 is a logic diagram of the control circuit

for the identification logic used to control the arrangement according to FIG. 1 and

7 shows a simplified logic circuit diagram of the on-order according to FIGS. 1A to 1C, in which only

the essential logical connections or links are shown.

1A to 1C show in the specified combination a "soft" programmable logic device 10 in accordance with the invention. The logical data is transferred to the entered on the left side of the display and run through the various logical levels, so that output signals corresponding to the predetermined programmed logic functions on the right-hand side of the illustration appear.

Several functional elements 12, 14, 16, 18, 20, 22, 24 and 26 form the first logical level of the logic arrangement 10 according to the invention. The functional elements 12-26 are each constructed identically; the structure of the functional element 12 is illustrated in detail in FIG. Each functional element has three data inputs, the data inputs of the functional element 12 with A, B and C with standing for the relevant functional element Additional digits are designated. A similar notation is used for the data inputs of all eight functional elements the first logical level is used. Each of the functional elements 12-26 has a single output which is connected to the rest of the logic arrangement 10

is bound. A second level of logic consists of six Functional elements 28-38, which are connected to six passage / holding devices 40-50, which in turn each have the same structure; the device 40 is shown in detail in FIG. These six port / holding devices 40-50 form the third level of the illustrated embodiment, and the outputs of this Devices are connected as shown.

The fourth level of logic in this embodiment consists of four functional elements 52-58 which take their input signals in the manner shown and whose outputs are connected as inputs to four pass / hold devices 60-66 which form the fifth logic level. The sixth logic level consists of two functional elements 68 and _70f, the outputs of which supply input signals to functional / pass-through elements 72 and 74, which represent an eighth logic level. In FIGS. 1A to 1C, each functional element is denoted by a number preceded by the letters FE in front of a special element number. Similarly, all of the passageway / holding devices are designated with a special number preceded by the letters FP.

The output logic according to the invention consists of one two-stage element that can be viewed as having a single function. The first stage each of these elements is an output enable gate 80 which is shown in detail in FIG. Each of these Gate 80 is connected to a tri-state buffer 82, which has possible high, low and floating outputs. The floating output slides with the signal level on the output line, if it is assumed that other active logic devices are connected to the same logic line.

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devices are connected. The output function of the embodiment shown is thus represented by 12 Pairs of exit devices with twelve exit enable gates 80, 84, 88, 92, 96, 100, 104, 108, 112, 116, 12C and 124 are determined. Each of these gates is a tri-state buffer 82, 86, 90, 94, 98, 102, 106, 110, 114, 118, 122 and 126, respectively.

The logic arrangement according to FIGS. 1A to 1C can preferably can be construed as a quadrant or sector of four identical quadrants or sectors that are on one single VLSI chip to be arranged. In another embodiment, a different number of sectors may have apply a common tax system. A single VLSI chip thus contains four arranged in quadrants Circuits according to FIGS. 1A to 1C together with a single control circuit of the type shown in FIGS. 5 and 6. The circuit of FIG. 6 is designed so that it four separate circuits of the type shown in Figures 1A to 1C able to control. The various input control lines according to FIG. 1A originate from the control circuit according to Fig. 6, which will be explained in more detail later.

The outputs of the control circuit to the individual quadrants of the arrangement are each with a 3 inputs Outputs converting decoder 140 (Fig. 1A) connected. The input lines C5, C4 and C3 come from the control circuit 6, while the control line C9 for switching the decoder on or off as a function of of which of the four quadrants is addressed serves. Similarly, a 2 input / 4 output decoder is obtained 142 the input signals from the circuit according to FIG. 6, the line C8 for switching the deactivation on and off

encoder according to the input signals shown in FIG. 6 is used. AND gates 144, 146 and 148 control the output or the output (fanout) of the necessary control signals to load the program for the programmable Perform logic function.

Fig. 2 illustrates a logical function element used in the illustrated embodiment. Each FunktionseTament has an 8: 1-bit multiplexer 200, where the output FD represents the data output. Data input is through input signal lines A, B and C, which are the selection control lines of the multiplexer, but form data inputs to the functional element. For each of the eight input lines of the multiplexer there is an AND gate / set latch circuit 202-216 intended. The functional or identifying data inputs used to control the functional output of the Multiplexers 200 take place on program inputs SO - S7.

The free signal and the write enable signal functions are used in conjunction with the control logic according to FIG. 6 will be explained in more detail. When programmed with a functional input, each of the set latches will hold 202-216 this functional input for all operations of the circuit. The free signal sets all gates to zero as part of the initialization process. The write enable signal must be sent to Writing or programming of any functions can be enabled.

It is known that an 8: 1 bit multiplexer with three Control inputs can use a 3-bit control signal to select each of the possible inputs as an output. On the other hand, it is known that any logical function of three data bits is either a high or a

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must be low data bit. Through appropriate programming the eight input bits to multiplexer 200 with high and low bits can be taken care of that the output of the multiplexer 200 any logical function of the three data bit inputs to the Control lines A-C can be. This represents the logical structure of the functional element 12, which is a building block of the present arrangement operates in accordance with the invention.

In Fig. 3 is the passage / retainer 40 which is similar to the other such devices in the illustrated Embodiment corresponds, illustrated with its detailed logical scheme. The device 40 consists of a set / reset AND gate locking element 220, a flip-flop 222 and a gate (element) 224, which are connected in the manner shown. If element 220 is set as part of the labeling function, the data will cause input from the previous one Section that the AND gate 224 and the element work as a data pass circuit and the data at Invert the run without any significant time delay. If element 220 is not set, the Letting the data through the unit in addition to the data input initiating a clock signal which flip-flop 222 enables gate 224 lets the data through.

4, the output enable circuit 80 consists of a set / reset latch circuit 230 in conjunction with a gate (element) 232. If the latter is switched through (on), the buffer is dependent on Data input to the buffer correspondingly high or low. When the output enable line of gate 232 is not enabled is, the assigned buffer is in the out or floating state regardless of the data input. the

Input control lines to output enable gate 232 operate as follows: H holds the gate in the locked state or force it into this state; F is a test input and effects the forced release of the output; and E is the normal enable function input.

Fig. 5 shows the control system register 281 which the FORCE control function input for gate 283 according to FIG. 1C as well as for the respective other, similar quadrants supplies.

Fig. 6 shows a control circuit according to the invention for controlling the circuit of Fig. 1 as one of four identical circuits. The circuit 300 has a control clock (generator) 302. The input identification data flow is delivered at input 304. The input test data flow must be in a standard computer area as a function of the test maintenance logic system outside of the normal data paths as part of the initialization function be provided. The clock 302 performs a set, clear and forget function. This means, it prepares a monostable signal to control the various clear bits at the clear output 306, so that all circuits are initially cleared, but since a monostable signal is being formed, this needs to be done The extinguishing signal does not have to be thrown off, it automatically drops out.

Decoder 308 works in conjunction with counter 310 to provide an 8 bit output channel for the common Gating to the various functional element units 12. The input serial flow of data a 1-bit channel is controlled by the counter 310 with the decoder 308 so that for each functional element

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ment, such as the function element 12, which is addressed by the 8-bit output selection channel 310, the program inputs triggered sequentially. Counter 312 provides output control signals on lines C (Fig. 1) to control which selection logic on which functional element 12 or which passage holding device 40 for the addressing of the programming function is triggered. The counter also controls the addressing of the relevant Output enable element.

FIG. 7 shows, in a simplified schematic representation, the arrangement according to the invention according to FIGS. 1A to 1C. the Logic devices are only shown symbolically, and the various programming and control function lines are not shown. The reference numerals 12, 16, 18, 20, 22, 24 and 26 thus serve in FIG. 7, as well as in Fig. 1A, for designating functional elements because the device and the function can be viewed as the same. Fig. 7 thus shows the same logic system as in Figures 1A to 1C with eight levels of logic and one Output level, which form the soft (soft) programmable logic arrangement 10. The only major difference in Fig. 7 is that the two-stage pairs of output elements as shown in Fig. 1C in Fig. 7 are summarized to a single output element in a simplified manner. The combined exit release gate and tri-state buffer devices are thus designated in Figure 7 by the numerals 82A, 86A, ..., 126A to show the correspondence to the tri-state buffers 82, 86, 90, ..., 126 of Figure 1C.

The soft programmable logic arrangement according to the invention is one of the solutions to logic constructions recurring problems designed, namely the "sticking" of parts of a system in or with simple

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control functions. This must be distinguished from significant arithmetic functions, such as adding and multipliers, which are usually specially designed. Although the logic arrangement according to the invention could be designed to form an addition or multiplication function if it were not special effective. The logic arrangement according to the invention can be regarded as particularly effective for the implementation of scatter, residual or "sticking" functions of the kind used to complete the logic of an arithmetic or Boolean operating system are required in a computer. If a computer system e.g. four separate 16-bit adders or multipliers that operate separately in a 16-bit operating mode (mode), then it would be appropriate to use a to use soft programmable logic to provide control and logic functions to the to let four separate systems work in parallel in a 64-bit operating mode. It is not intended that the Softly programmable logic arrangement to supplement or implement the entire control section of a basic computer unit is used. Assigned microcode and assigned arithmetic or Boolean functions more economical for such large constructions. On the other hand, the soft programmable logic arrangement works advantageous for functions such as overflow detection in an arithmetic logic unit or control panel for three-state busbar purposes.

For the production of programmable logic arrangements, fusible element or melt-through techniques have hitherto usually been used applied. However, there is no viable or economical way to introduce it a fusible programmable logic in very large

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integrated circuits. The invention meets this need by providing either combined or sequential logic functions that can be selected by the user and mixed as a result of identification data.

The basic functional element of the logic arrangement according to the Invention is a logic unit or functional element 12 that can be configured to any logical To realize the function of three inputs. A number of logical levels or stages of these elements are interconnected to form the logic arrangement as a whole. A first stage of these elements is with the input pins linked, and the outputs of this first stage of functional elements control the downstream Level of functional elements.

In the illustrated embodiment, four are separate Groups of functional elements provided. There are four separate groups of on a single VLSI chip Logic arrangements arranged; each of these arrangements is called a sector or quadrant because it is a of four identical versions. There are eight in each quadrant or sector of the logic array Functional elements in a first stage connected to 24 input pins. Six functional elements are in a second logical level or level, four functional elements in a third logical level and finally two functional elements arranged in a last or fourth logical level or stage. All function level outputs the second stage and the following stages are connected to chip output pins, in addition to the Delivery of the output to downstream output levels. This means that the user can take up to six

compare simple logical equations or up to 12 logical mixed expression equations or just two complex logical equations using the can realize various combinations of functional elements in logical level arrangements. The most complex Equation programmed for a given logic arrangement of the type shown in Figures 1A through 1C can include seven functional elements with 21 input pins.

At the output of every functional element in every stage, with the exception of those of the first stage, there is a selectable flip-flop or a pass / hold unit. Each flip-flop is selectable to act as a single cycle holding register acts or lets the data through immediately, without data locking and with minimal delay. Each Flip-flop has an input which, for test purposes, can use the Forced deletion of all flip-flops allowed under system control.

Associated with each chip output pin is an output element which is the tri-state control line of each output pin buffer controls. A user can forcibly switch the output pin to permanent enable, that is, the data output is never turned off and an input pin associated with each of the four quadrants is enabled around the tri-state line of each output pin of a quadrant.

Each functional element (e.g. 12) contains an 8: 1 multiplexer, driven by eight memory latch circuits, and three selection inputs A-C that are used to select the state of the one interlocking circuit to the multiplex (er) output be decoded. The eight data locking circuits are set and cleared in order to

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to realize the desired logical function of the inputs A - C. The eight data latch circuits constitute a full truth table for three inputs, which allows the execution of any logical function of three bits, by setting and clearing the required data lock circuits. As a simple example FD = A B C is performed by clearing all data latches, with the exception of the interlocking circuit assigned to S7, which is set. The truth table for each required Logical function can easily be determined according to various logical methods known per se.

All interlock circuits are initialized by a circuit which is generated by the control unit according to FIG. 6 is controlled. All interlocks are cleared at the same time and then sequentially through over data incoming test data output pin 304 is conditionally set. The locking bit is used in each functional element Zero (latch bit zero) is first keyed through, whereupon the (other) bits in sequence up to the last bit 7 be scanned.

The pass / hold flip-flop 40 of FIG. 3 is a 2: 1 multiplexer, which is controlled by a locking bit assigned to the locking bits 202 in the functional element 12 corresponds. These lock bits are also operated in the same way under the same control functions that from the unit of Fig. 6 are controlled. When the lock bit is cleared, the input data from the controlling functional element directly to the output of the multiplexer and from there to the output pin and to the following functional elements, if available. In doing so, the data is

-> 6—

animals. This must be taken into account when writing the logical equations of downstream levels of the functional elements will. If the lock bit is or is set, the output of the flip-flop is with the Multiplexer output connected. It should be noted that in this case the data from input to output is not inverted, as is the case with pass-through. This inversion change between flip-flop and pass mode poses no problem because the data latch circuit only writes in once when the power is switched on. It cannot therefore be changed during operation. The fact that the Data inverted can be accounted for by generating the logical complement of the required logical function in the functional element controlling the relevant input.

The flip-flop 222 becomes continuous without any gate control Hung, clocked. This means that to form a state sequential Switching the output signal of the function to a chip input as an input signal must be switched back to the defining logical equations. It is a reset input to the data flip-flop is present, which comes from the operation control unit according to FIG. 6 and which is used to initialize the flip-flops for Operation or testing can be used. The output enable device 80 of Figure 4 is with the tri-state control line connected to each functional output pin. The output release has three different ones Modes of operation.

The first operating mode of the output enable is a storage data bit, that - if it is set - the relevant three-state control line when the output is enabled

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holds high except that the output pin is forced by the output shutdown shutoff bus can be switched off or de-energized. 5

The second mode of operation or operating condition is that when the data bit is cleared, the common input / output pin for each output enable device in a quadrant, the three-state control line can control. A high level on this pin gives all output buffers and the corresponding free the logic array quadrants except for the hold open bus in turn can override the enable line.

In the third operating mode, each output can be forcibly switched on in a quadrant (output enabled) by means of a function bit in the control system register 281 according to FIG. 5. Four individual control bits are therefore provided. While it is expected that this facility is normally used for maintenance purposes (become), their application in system operation is not in the way. The control system interface function 6 represents an integral part of the soft programmable logic arrangement and enables an initialization with identification data. This is because the logic arrangement has no function until the maintenance system loads the data lock circuits which determine the selected logical function.

The data locking circuits that provide the required Realizing logical functions are loaded by first inserting all data locking circuits into all quadrants were then solved individually if necessary with the data coming from the test data input. There is a bit counter on the chip

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-as-

seen counting from O-767. Of the 768 counting steps 736 counts are bit lock units for 184 lock units in each quadrant, plus 8 additional ones Counting steps. Each function lock unit is set when the test data input bit is a "1" is whereupon the counter is incremented or counts up. This counter is simply triggered by "1" (bumped) when the input bit is a "0". The function bit description at for the control functions are as follows: The WRITEF function is active if bit "1" of the Control Register is set or is when a test scan input pin is active. The WRITEF function must be active in order to write in the function description interlocking units to enable. The WRITEF function can be in the same control word as the functions INITF and CLEARF must be included. When the WRITEF function is active and the test clock enable input pin is the is high, the state of the test data input pen becomes written into the currently addressed locking unit.

The INITF function is or will be activated if bit 2 of the control register is or is set when the test scan input pin is active. INITF performs two functions: 1) It clears the address counters, which select the individual function locking bits, down to zero; and 2) it also clears all interstage flip-flops in all four logical quadrant arrangements.

INITF is a monostable function insofar as it only lasts for one clock on the leading edge when the Test connection is active. This means that this function is in the same function control word as (the Function) WRITEF can be present to write the function description interlocking

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to simplify the necessary control sequences. this is done by holding the test clock enable control line low or inactive when the Test switch-through signal is carried to the high level. After a delay of at least two clock cycles, the test clock enable signal can be taken to the high level and the description lock units are written.

The CLEARF function is or is enabled if bit 3 of the control register is set when the scan probe input pin is active. This function clears all function description locking units in all Quadrant to zero. This must be done when the power is switched on when writing to the logic arrangement for the first time, and can be done at other times to change the chip function. The CLEARF function is not necessary if the description locking unit holding a zero is changed to "1" shall be. A function WRITEF / INITF is used at uses a data flow that consists entirely of zeros, with the exception of ones at the required change points, consists. CLEARF is a monostable function in that it only lasts for one clock cycle on the leading edge of an effective test switch-through signal is active. This means that this function is in the same Function control word such as WRITEF can be included to supply the control sequences to (in) the function description interlocking units to enroll. This is done by activating the test cycle release (line) on the is held low while the test enable signal is led to the high level. After a delay of at least two clock cycles, the Test cycle enable (line) brought to the high level and the description lock units are described.

The four functions FORCEFO to F0RCEF3, bits 4, 5, 6 and 7, respectively, of control register 281 force all of the output pins in the relevant quadrant in the active state. The function overrides the state of the output enable pin, the blocking busbar as well as the state of any function description interlocking unit in the output enable gates. While it can be assumed that these function bits are mainly used by diagnostic equipment they can also be used in normal system operation. The four bits are on the leading edge of a test clock enable signal loaded into a static holding register.

The BLOCKF function is active or effective if bit of the control register is active when the test key input is active. This feature deactivates all output pins in all quadrants, and it overrides the output enable pins and the state of any functional description locking unit in one of the output enabling devices. The function BLOCKF forces the blocking busbar into the shutdown mode while it does not override any active FORCEF function.

The logic arrangement according to the invention offers various advantages. On the one hand, it is to be carried out for each Function designed. If the part or arrangement in the system is moved from one place to another, it executes the logical equations for the new location without physically changing the part. The delay of a logic signal through the part is the complexity of the logic equation to be implemented proportional. Multiple simple equations or fewer, more complex equations can be processed, which means

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the designer of logic circuits has greater design freedom. The logic arrangement is realized variable functions on a fixed set of inputs as opposed to the pre-established fixed equations at variable inputs in the prior art. The flip-flops forming part of the logic path can used to implement state equations or deactivated to execute combined logic.

The functional elements of the first level feed those of the second level. The individual functional elements of the The second level can then control their own output pin or functional elements that control output pins dining on a third level. The latter can in turn control outputs on a fourth level. Based on these Link or link, all outputs of the second level of the arrangement can be active, so that up to six comparatively simple equations can be solved in the arrangement. With increasing complexity Larger equations, the elements of the third and fourth levels can be used to create more and more Let elements of the first and second level become part of the logical equation and thus become increasingly complex solve logical equations.

The two logical types of solution can be used at the same time. In other words, some simple, logical ones Equations should provide signals that can also be used in more complex logical equations. The exits the second and third levels can be active at the same time as those of the third and fourth levels, so that simple and complex logical functions are generated or carried out at the same time. By choosing the State of the passage / holding devices, namely whether they

Holding or letting data through, some of the logical equations can be state equations and others pure be combined linkage equations.

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Claims (15)

Claims 1. Softly programmable logic arrangement, characterized by several logical levels formed from functional elements, each with logical inputs and outputs that have a predetermined Function of the input are, each functional element with (its) inputs for accepting data inputs and data outputs, which represent logical equations of the data inputs, is connected and each functional element has a plurality of inputs connected to at least one output, so that the output can be any logical function of the inputs, and each functional element is one of the number of possible Output states equivalent number of locking units for holding a predetermined logical indication the assigned initial state according to the executed logical function, through a number of stages of flip-flop pass units for taking the outputs from one of the logic ones Stages connected to the inputs as well as to the inputs of another of the logic stages and to the output the outputs connected to the logic arrangement, these units each having a logic state invert and let this pass without delay or a logical function until it is enabled able to lock, depending on a predetermined logical function to be performed, and through a control unit to all functional elements and flip-flop pass units for the execution of a predetermined set logical function. 2. Arrangement according to claim 1, characterized by a first logic level of eight for the acceptance of system data inputs switched function elements, a second logical level of six with the outputs functional elements connected to the first logical level, a third stage of six flip-flop pass units connected to the outputs of the second logic stage, a fourth logic stage of four functional elements connected to the outputs of the third stage, a fifth stage of four flip-flop pass units connected to the outputs of the fourth stage, a sixth logic stage from two functional elements connected to the outputs of the fifth stage, a seventh stage from two flip-flop pass units connected to the outputs of the sixth logic stage and
an eighth stage of twelve output enable gates connected to the outputs of the third, fifth and seventh stages. 3. Apparatus according to claim 2, characterized in that the output of each output release gate in the one Operating mode is forcibly brought to a high, low or sliding level or in another operating mode can connect the input function as an output. 4. Arrangement according to claim 2, characterized in that each functional element has three data inputs, eight has logical control inputs and an output. BATH ORIGINAL 5. Arrangement according to claim 4, characterized in that that each functional element consists of an 8: 1 multiplexer and eight AND gate / set latch circuits, which as Inputs to the multiplexer are switched, there is. 6. Soft programmable logic arrangement, characterized by a first logical level (level) of functional elements, each of which has logical function outputs as predetermined logical functions of the inputs provide a second stage from connected to the first stage Function elements for the delivery of each logical function outputs, the predetermined logical functions the entrances are a third stage of flip-flop pass units connected to the second stage for performing an inverting, instantaneous pass-through or locking function according to a predetermined function, a fourth stage of functional elements which take inputs from the third stage of the flip-flop pass units are connected and each generate logical function outputs, the predetermined logical Functions of the inputs are a fifth stage of flip-flop passage units connected to the fourth stage for performing an inverting, instantaneous passage or a locking function in accordance with a predetermined function, a sixth stage of functional elements connected to take inputs from the fourth stage of the flip-flop passage units, each of which is logical Generate function outputs as predetermined logical functions of the inputs,
a seventh stage of flip-flop pass units connected to take data inputs from the sixth stage to carry out an inverting, instantaneous pass-through or a locking function accordingly a predetermined function, an output release stage connected to the acceptance of inputs from the third, fifth and seventh stage of the flip-flop pass elements for supplying a data output for the logic arrangement and
a control unit connected to all functional elements and flip-flop passage units for controlling and testing the logic arrangement and for supplying locking inputs for setting all functional elements and flip-flop passage units for the purpose of executing or executing a predetermined logical function. 7. Arrangement according to claim 6, characterized in that each functional element has three data inputs, eight having logic control inputs and a data output and an 8: 1 multiplexer and eight AND gate / set locking circuits exists as inputs to the multiplexer. 8. Soft programmable logic arrangement, characterized by several logic sectors, each independent have logical inputs and outputs by several logical ones, each forming a sector Levels (levels) of functional elements, each logical level with its inputs for the acceptance of data input signals is switched and provides data output signals, which represent the logical equations of the data input signals, with each functional element having multiple inputs which are linked to at least one output, so that the output has a logical function of the inputs, and the functional elements being one of the number of possible output states equivalent Number of locking units to hold a logical BATH ORIGINAL -δ-1 Display of the assigned output status according to the executed logical function, through a number of stages of flip-flop pass units with inputs connected to the acceptance of the outputs from one of the logic levels as well as to the Inputs of another of the logic levels and outputs connected to the output of the sector, these Units each invert a logic state IQ and allow this through without delay or be able to lock a logical function until it is released, depending on a predetermined logical function to be executed, and
by an all sector control unit for setting all functional elements and flip-flop pass units to perform predetermined logical functions in each sector. 9. Arrangement according to claim 8, characterized in that each sector a first stage (level) of for taking data input signals switched logic elements with inputs for receiving a first set of logic signals for setting the locking units of the first level of logical elements, a second level of logical elements in the form connected to the first level of logical elements of functional elements with inputs for receiving a second set of logic signals for setting the locking units the second stage of logic elements, a third stage of flip-flop pass units with inputs for taking a third set of logic signals for setting the latch units of the flip-flop pass units of the third stage, a fourth stage connected to take inputs from the third stage flip-flop pass units logical elements with inputs for receiving a fourth set of logical signals for setting their interlocking units,
a fifth stage of flip-flop pass units connected for taking inputs from the fourth stage of the logic elements, with inputs for taking a fifth set of logic signals for setting their locking units, a sixth stage connected to take data inputs from the flip-flop pass units of the fifth stage logic elements with inputs for receiving a sixth set of logic signals for setting their interlocking units, a seventh stage of connected for taking data inputs from the logical elements of the sixth stage Flip-flop pass units with inputs for taking a seventh set of logic signals for setting their locking units and an eighth stage of for taking inputs from third, fifth and seventh stages of flip-flop pass elements Switched gates for the delivery of data output signals for the logic arrangement and with inputs to the Includes taking an eighth set of logic signals to set the latch units of the output enable gates. 10. The arrangement according to claim 9, characterized in that each functional element has three data inputs, eight having logical control inputs and a data output and an 8: 1 multiplexer and eight AND gate / set latching circuits exists as inputs to the multiplexer. BATH ORIGINAL 11. Softly programmable logic arrangement for performing a predetermined logic function on a data input function, characterized by a first level (level) of logic elements each in the form of a functional element with several data input / receiving lines, at least one data output line and means for removing and locking for the to be performed Function representative control signals and each switched to accept data inputs to the system and a first set of logic signals to set the locking units (latches) of these logic elements,
by a second stage of logic elements connected to the logic elements of the first stage in the form of functional elements each with a plurality of data input / reception lines connected to the first stage, at least one data output line and means for taking and locking of control signals representative of the function to be performed and each switched for taking data inputs to the second stage and a second set of logic signals for setting the locking elements of these logic elements, by a third stage of logic elements, connected to the second stage, of flip-flop pass units including means for taking and locking a third set of logic signals for controlling the from the function performed by the flip-flop pass units, by a fourth level of logic elements in each case Form of functional elements each with several data input / reception lines, at least one data output line and means for removing and locking Control signals representative of the function to be performed and each switched to accept inputs from the third stage flip-flop pass units, as well as means for removing and locking a fourth set of logic signals for setting the locking elements these functional elements for the purpose of executing the predetermined logical function, by a fifth stage of logic elements, connected to the fourth stage, of flip-flop pass units having means for taking and locking a fifth set of logic signals for controlling the from function carried out by these units, through a sixth level of logical elements with the Fifth stage connected functional elements with each a plurality of data input / reception lines, at least one data output line and means for removing and Locking of control signals representative of the function to be carried out for the acceptance of data inputs from the fifth stage flip-flop pass units, and having means for removing a sixth set of logs Signals to set the locking elements of these functional elements for the execution of the predetermined logical functions, cry through seventh stage from associated with the sixth stage logical elements of flip-flop transmission units, each with a number of data input / reception lines, at least one data output line and means for removing and locking for the to be executed predetermined function representative control signals and through an output release level for the acceptance of Inputs of the third, fifth and seventh stage of the flip-flop pass units is switched to one To provide data output for the logic arrangement. BATH ORIGINAL 12. The arrangement according to claim 11, characterized in that each functional element has three data inputs, eight logical Has control inputs and a data output and consists of an 8: 1 multiplexer and eight AND gate / set interlock circuits exists as inputs to the multiplexer. 13. Arrangement according to claim 11, characterized in that a control unit for supplying a series flow of control signals for input into all locking elements of the functional elements as well as a flow of locking setting control signals, in order to effect the setting of the relevant locking control signal in the corresponding locking element, is provided. 14. Arrangement according to claim 11, characterized in that a clock control unit for controlling the scanning the relevant control signals to the corresponding functional elements in the order of the logical Stages in the operation of the logic arrangement is provided. 15. Arrangement according to claim 11, characterized in that that a counter can be incremented when the individual control signals are received in the input series data flow and the The output count of the counter controls the addressing of the functional elements.